@ -25,29 +25,27 @@
# include <asm/cache.h>
# include <asm/cache.h>
# include <watchdog.h>
# include <watchdog.h>
void flush_cache ( ulong start_addr , ulong size )
void flush_cache ( ulong start_addr , ulong size )
{
{
# ifndef CONFIG_5xx
# ifndef CONFIG_5xx
ulong addr , end_addr = start_addr + size ;
ulong addr , start , end ;
if ( CONFIG_SYS_CACHELINE_SIZE ) {
start = start_addr & ~ ( CONFIG_SYS_CACHELINE_SIZE - 1 ) ;
addr = start_addr & ( CONFIG_SYS_CACHELINE_SIZE - 1 ) ;
end = start_addr + size - 1 ;
for ( addr = start_addr ;
addr < end_addr ;
addr + = CONFIG_SYS_CACHELINE_SIZE ) {
asm ( " dcbst 0,%0 " : : " r " ( addr ) ) ;
WATCHDOG_RESET ( ) ;
}
asm ( " sync " ) ; /* Wait for all dcbst to complete on bus */
for ( addr = start_addr ;
for ( addr = start ; addr < = end ; addr + = CONFIG_SYS_CACHELINE_SIZE ) {
addr < end_addr ;
asm volatile ( " dcbst 0,%0 " : : " r " ( addr ) : " memory " ) ;
addr + = CONFIG_SYS_CACHELINE_SIZE ) {
WATCHDOG_RESET ( ) ;
asm ( " icbi 0,%0 " : : " r " ( addr ) ) ;
WATCHDOG_RESET ( ) ;
}
}
}
asm ( " sync " ) ; /* Always flush prefetch queue in any case */
/* wait for all dcbst to complete on bus */
asm ( " isync " ) ;
asm volatile ( " sync " : : : " memory " ) ;
for ( addr = start ; addr < = end ; addr + = CONFIG_SYS_CACHELINE_SIZE ) {
asm volatile ( " icbi 0,%0 " : : " r " ( addr ) : " memory " ) ;
WATCHDOG_RESET ( ) ;
}
asm volatile ( " sync " : : : " memory " ) ;
/* flush prefetch queue */
asm volatile ( " isync " : : : " memory " ) ;
# endif
# endif
}
}