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arm: rmobile: koelsch: Remove NOR-Flash support

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Koelsch board has NOR-Flash. But user uses SPI-Flash ROM instead of NOR-Flash.
This removed the setting of NOR-Flash.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
master
Nobuhiro Iwamatsu 11 years ago committed by Nobuhiro Iwamatsu
parent ec9b386e26
commit e44154ef0a
3 changed files with 0 additions and 215 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 183
      board/renesas/koelsch/koelsch.c
  2. 1
      boards.cfg
  3. 31
      include/configs/koelsch.h

183
board/renesas/koelsch/koelsch.c
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@ -23,168 +23,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define s_init_wait(cnt) \
({ \
u32 i = 0x10000 * cnt; \
while (i > 0) \
i--; \
})
#define dbpdrgd_check(bsc) \
({ \
while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
; \
})
#if defined(CONFIG_NORFLASH)
static void bsc_init(void)
{
struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
/* LBSC */
writel(0x00000020, &lbsc->cs0ctrl);
writel(0x00000020, &lbsc->cs1ctrl);
writel(0x00002020, &lbsc->ecs0ctrl);
writel(0x00002020, &lbsc->ecs1ctrl);
writel(0x077F077F, &lbsc->cswcr0);
writel(0x077F077F, &lbsc->cswcr1);
writel(0x077F077F, &lbsc->ecswcr0);
writel(0x077F077F, &lbsc->ecswcr1);
/* DBSC3 */
s_init_wait(10);
writel(0x0000A55A, &dbsc3_0->dbpdlck);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x80000000, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000006, &dbsc3_0->dbpdrga);
writel(0x0001C000, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FD2480, &dbsc3_0->dbpdrgd);
writel(0x00000010, &dbsc3_0->dbpdrga);
writel(0xF004649B, &dbsc3_0->dbpdrgd);
writel(0x0000000F, &dbsc3_0->dbpdrga);
writel(0x00181EE4, &dbsc3_0->dbpdrgd);
writel(0x0000000E, &dbsc3_0->dbpdrga);
writel(0x33C03812, &dbsc3_0->dbpdrgd);
writel(0x00000003, &dbsc3_0->dbpdrga);
writel(0x0300C481, &dbsc3_0->dbpdrgd);
writel(0x00000007, &dbsc3_0->dbkind);
writel(0x10030A02, &dbsc3_0->dbconf0);
writel(0x00000001, &dbsc3_0->dbphytype);
writel(0x00000000, &dbsc3_0->dbbl);
writel(0x0000000B, &dbsc3_0->dbtr0);
writel(0x00000008, &dbsc3_0->dbtr1);
writel(0x00000000, &dbsc3_0->dbtr2);
writel(0x0000000B, &dbsc3_0->dbtr3);
writel(0x000C000B, &dbsc3_0->dbtr4);
writel(0x00000027, &dbsc3_0->dbtr5);
writel(0x0000001C, &dbsc3_0->dbtr6);
writel(0x00000005, &dbsc3_0->dbtr7);
writel(0x00000018, &dbsc3_0->dbtr8);
writel(0x00000008, &dbsc3_0->dbtr9);
writel(0x0000000C, &dbsc3_0->dbtr10);
writel(0x00000009, &dbsc3_0->dbtr11);
writel(0x00000012, &dbsc3_0->dbtr12);
writel(0x000000D0, &dbsc3_0->dbtr13);
writel(0x00140005, &dbsc3_0->dbtr14);
writel(0x00050004, &dbsc3_0->dbtr15);
writel(0x70233005, &dbsc3_0->dbtr16);
writel(0x000C0000, &dbsc3_0->dbtr17);
writel(0x00000300, &dbsc3_0->dbtr18);
writel(0x00000040, &dbsc3_0->dbtr19);
writel(0x00000001, &dbsc3_0->dbrnk0);
writel(0x00020001, &dbsc3_0->dbadj0);
writel(0x20082008, &dbsc3_0->dbadj2);
writel(0x00020002, &dbsc3_0->dbwt0cnf0);
writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
writel(0x00000015, &dbsc3_0->dbpdrga);
writel(0x00000D70, &dbsc3_0->dbpdrgd);
writel(0x00000016, &dbsc3_0->dbpdrga);
writel(0x00000006, &dbsc3_0->dbpdrgd);
writel(0x00000017, &dbsc3_0->dbpdrga);
writel(0x00000018, &dbsc3_0->dbpdrgd);
writel(0x00000012, &dbsc3_0->dbpdrga);
writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
writel(0x00000013, &dbsc3_0->dbpdrga);
writel(0x1A868300, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
writel(0x00000014, &dbsc3_0->dbpdrga);
writel(0x300214D8, &dbsc3_0->dbpdrgd);
writel(0x0000001A, &dbsc3_0->dbpdrga);
writel(0x930035C7, &dbsc3_0->dbpdrgd);
writel(0x00000060, &dbsc3_0->dbpdrga);
writel(0x330657B2, &dbsc3_0->dbpdrgd);
writel(0x00000011, &dbsc3_0->dbpdrga);
writel(0x1000040B, &dbsc3_0->dbpdrgd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000071, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x2100FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x110000DB, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000181, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x0000FE01, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000000, &dbsc3_0->dbbs0cnt1);
writel(0x01004C20, &dbsc3_0->dbcalcnf);
writel(0x014000AA, &dbsc3_0->dbcaltr);
writel(0x00000140, &dbsc3_0->dbrfcnf0);
writel(0x00081860, &dbsc3_0->dbrfcnf1);
writel(0x00010000, &dbsc3_0->dbrfcnf2);
writel(0x00000001, &dbsc3_0->dbrfen);
writel(0x00000001, &dbsc3_0->dbacen);
}
#else
#define bsc_init() do {} while (0)
#endif /* CONFIG_NORFLASH */
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
@ -196,9 +34,6 @@ void s_init(void)
/* QoS */
qos_init();
/* BSC */
bsc_init();
}
#define MSTPSR1 0xE6150038
@ -213,18 +48,6 @@ void s_init(void)
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define PMMR 0xE6060000
#define GPSR4 0xE6060014
#define IPSR14 0xE6060058
#define set_guard_reg(addr, mask, value) \
{ \
u32 val; \
val = (readl(addr) & ~(mask)) | (value); \
writel(~val, PMMR); \
writel(val, addr); \
}
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
@ -238,13 +61,7 @@ int board_early_init_f(void)
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
#if defined(CONFIG_NORFLASH)
/* SCIF0 */
set_guard_reg(GPSR4, 0x34000000, 0x00000000);
set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
set_guard_reg(GPSR4, 0x00000000, 0x34000000);
#endif
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */

1
boards.cfg
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@ -367,7 +367,6 @@ Active arm armv7 omap5 ti omap5_uevm
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com>

31
include/configs/koelsch.h
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@ -32,15 +32,9 @@
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
#define CONFIG_CMD_FLASH
#define CONFIG_SYS_TEXT_BASE 0x00000000
#else
/* SPI flash boot is default. */
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SYS_TEXT_BASE 0xE6304000
#endif
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@ -109,29 +103,6 @@
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_BASE 0x00000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
/* ENV setting */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
CONFIG_SYS_MONITOR_LEN)
#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SH_QSPI
@ -142,8 +113,6 @@
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_ADDR 0xC0000
#endif /* CONFIG_SYS_USE_BOOT_NORFLASH */
/* Common ENV setting */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_SECT_SIZE (256 * 1024)

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