This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch>master
Sanchayan Maity
10 years ago
committed by
Tom Rini
parent
7a90a1f260
commit
e7b860fa4d
@ -0,0 +1,18 @@ |
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if TARGET_COLIBRI_VF |
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config SYS_CPU |
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default "armv7" |
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config SYS_BOARD |
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default "colibri_vf" |
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config SYS_VENDOR |
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default "toradex" |
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config SYS_SOC |
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default "vf610" |
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config SYS_CONFIG_NAME |
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default "colibri_vf" |
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endif |
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@ -0,0 +1,6 @@ |
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Colibri VFxx |
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M: Stefan Agner <stefan.agner@toradex.com> |
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S: Maintained |
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F: board/toradex/colibri_vf/ |
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F: include/configs/colibri_vf.h |
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F: configs/colibri_vf_defconfig |
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@ -0,0 +1,7 @@ |
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#
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# Copyright 2013 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := colibri_vf.o
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@ -0,0 +1,361 @@ |
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/*
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* Copyright 2015 Toradex, Inc. |
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* |
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* Based on vf610twr.c: |
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/iomux-vf610.h> |
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#include <asm/arch/ddrmc-vf610.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/clock.h> |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <i2c.h> |
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#include <g_dnl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
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PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) |
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#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ |
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PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) |
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#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ |
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PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) |
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int dram_init(void) |
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{ |
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static const struct ddr3_jedec_timings timings = { |
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.tinit = 5, |
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.trst_pwron = 80000, |
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.cke_inactive = 200000, |
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.wrlat = 5, |
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.caslat_lin = 12, |
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.trc = 21, |
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.trrd = 4, |
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.tccd = 4, |
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.tfaw = 20, |
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.trp = 6, |
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.twtr = 4, |
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.tras_min = 15, |
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.tmrd = 4, |
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.trtp = 4, |
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.tras_max = 28080, |
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.tmod = 12, |
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.tckesr = 4, |
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.tcke = 3, |
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.trcd_int = 6, |
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.tdal = 12, |
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.tdll = 512, |
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.trp_ab = 6, |
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.tref = 3120, |
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.trfc = 64, |
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.tpdex = 3, |
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.txpdll = 10, |
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.txsnr = 48, |
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.txsr = 468, |
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.cksrx = 5, |
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.cksre = 5, |
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.zqcl = 256, |
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.zqinit = 512, |
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.zqcs = 64, |
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.ref_per_zq = 64, |
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.aprebit = 10, |
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.wlmrd = 40, |
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.wldqsen = 25, |
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}; |
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ddrmc_setup_iomux(); |
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ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2); |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
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return 0; |
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} |
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static void setup_iomux_uart(void) |
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{ |
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static const iomux_v3_cfg_t uart_pads[] = { |
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NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL), |
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}; |
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); |
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} |
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static void setup_iomux_enet(void) |
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{ |
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static const iomux_v3_cfg_t enet0_pads[] = { |
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NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL), |
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}; |
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imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); |
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} |
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static void setup_iomux_i2c(void) |
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{ |
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static const iomux_v3_cfg_t i2c0_pads[] = { |
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VF610_PAD_PTB14__I2C0_SCL, |
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VF610_PAD_PTB15__I2C0_SDA, |
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}; |
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imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); |
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} |
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#ifdef CONFIG_NAND_VF610_NFC |
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static void setup_iomux_nfc(void) |
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{ |
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static const iomux_v3_cfg_t nfc_pads[] = { |
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VF610_PAD_PTD23__NF_IO7, |
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VF610_PAD_PTD22__NF_IO6, |
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VF610_PAD_PTD21__NF_IO5, |
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VF610_PAD_PTD20__NF_IO4, |
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VF610_PAD_PTD19__NF_IO3, |
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VF610_PAD_PTD18__NF_IO2, |
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VF610_PAD_PTD17__NF_IO1, |
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VF610_PAD_PTD16__NF_IO0, |
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VF610_PAD_PTB24__NF_WE_B, |
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VF610_PAD_PTB25__NF_CE0_B, |
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VF610_PAD_PTB27__NF_RE_B, |
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VF610_PAD_PTC26__NF_RB_B, |
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VF610_PAD_PTC27__NF_ALE, |
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VF610_PAD_PTC28__NF_CLE |
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}; |
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imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); |
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} |
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#endif |
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#ifdef CONFIG_FSL_ESDHC |
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struct fsl_esdhc_cfg esdhc_cfg[1] = { |
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{ESDHC1_BASE_ADDR}, |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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/* eSDHC1 is always present */ |
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return 1; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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static const iomux_v3_cfg_t esdhc1_pads[] = { |
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NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), |
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NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), |
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}; |
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
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imx_iomux_v3_setup_multiple_pads( |
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esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); |
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
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} |
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#endif |
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static inline int is_colibri_vf61(void) |
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{ |
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struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; |
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/*
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* Detect board type by Level 2 Cache: VF50 don't have any |
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* Level 2 Cache. |
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*/ |
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return !!mscm->cpxcfg1; |
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} |
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static void clock_init(void) |
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{ |
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; |
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struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; |
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u32 pfd_clk_sel, ddr_clk_sel; |
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clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, |
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CCM_CCGR0_UART0_CTRL_MASK); |
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clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, |
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CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); |
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clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, |
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CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | |
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CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | |
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CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK); |
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clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, |
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CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); |
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clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, |
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CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | |
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CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); |
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clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, |
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CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); |
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clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, |
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CCM_CCGR7_SDHC1_CTRL_MASK); |
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clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, |
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CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); |
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clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, |
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CCM_CCGR10_NFC_CTRL_MASK); |
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clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | |
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ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | |
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ANADIG_PLL5_CTRL_DIV_SELECT); |
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if (is_colibri_vf61()) { |
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clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | |
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ANADIG_PLL2_CTRL_POWERDOWN, |
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ANADIG_PLL2_CTRL_ENABLE | |
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ANADIG_PLL2_CTRL_DIV_SELECT); |
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} |
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clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, |
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ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); |
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clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, |
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CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); |
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/* See "Typical PLL Configuration" */ |
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if (is_colibri_vf61()) { |
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pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1); |
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ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0); |
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} else { |
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pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3); |
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ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1); |
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} |
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clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | |
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CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | |
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CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | |
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CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | |
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CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | |
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ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) | |
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CCM_CCSR_SYS_CLK_SEL(4)); |
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clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, |
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CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | |
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CCM_CACRR_ARM_CLK_DIV(0)); |
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clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, |
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CCM_CSCMR1_ESDHC1_CLK_SEL(3) | |
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CCM_CSCMR1_NFC_CLK_SEL(0)); |
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clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, |
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CCM_CSCDR1_RMII_CLK_EN); |
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clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, |
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CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | |
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CCM_CSCDR2_NFC_EN); |
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clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, |
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CCM_CSCDR3_NFC_PRE_DIV(5)); |
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clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, |
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CCM_CSCMR2_RMII_CLK_SEL(2)); |
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} |
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static void mscm_init(void) |
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{ |
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struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; |
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int i; |
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for (i = 0; i < MSCM_IRSPRC_NUM; i++) |
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writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); |
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} |
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int board_phy_config(struct phy_device *phydev) |
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{ |
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if (phydev->drv->config) |
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phydev->drv->config(phydev); |
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return 0; |
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} |
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int board_early_init_f(void) |
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{ |
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clock_init(); |
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mscm_init(); |
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setup_iomux_uart(); |
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setup_iomux_enet(); |
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setup_iomux_i2c(); |
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#ifdef CONFIG_NAND_VF610_NFC |
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setup_iomux_nfc(); |
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#endif |
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return 0; |
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} |
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#ifdef CONFIG_BOARD_LATE_INIT |
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int board_late_init(void) |
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{ |
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struct src *src = (struct src *)SRC_BASE_ADDR; |
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/* Default memory arguments */ |
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if (!getenv("memargs")) { |
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switch (gd->ram_size) { |
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case 0x08000000: |
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/* 128 MB */ |
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setenv("memargs", "mem=128M"); |
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break; |
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case 0x10000000: |
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/* 256 MB */ |
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setenv("memargs", "mem=256M"); |
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break; |
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default: |
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printf("Failed detecting RAM size.\n"); |
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} |
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} |
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if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT) |
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== SRC_SBMR2_BMOD_SERIAL) { |
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printf("Serial Downloader recovery mode, disable autoboot\n"); |
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setenv("bootdelay", "-1"); |
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} |
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return 0; |
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} |
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#endif /* CONFIG_BOARD_LATE_INIT */ |
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int board_init(void) |
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{ |
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struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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/*
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* Enable external 32K Oscillator |
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* |
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* The internal clock experiences significant drift |
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* so we must use the external oscillator in order |
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* to maintain correct time in the hwclock |
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*/ |
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setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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if (is_colibri_vf61()) |
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puts("Board: Colibri VF61\n"); |
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else |
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puts("Board: Colibri VF50\n"); |
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return 0; |
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} |
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@ -0,0 +1,17 @@ |
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/* |
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* Copyright 2014 Toradex, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer docs/README.imxmage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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#include <asm/imx-common/imximage.cfg> |
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/* image version */ |
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IMAGE_VERSION 2 |
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/* Boot Offset 0x400, valid for both SD and NAND boot */ |
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BOOT_OFFSET FLASH_OFFSET_STANDARD |
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@ -0,0 +1,3 @@ |
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" |
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CONFIG_ARM=y |
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CONFIG_TARGET_COLIBRI_VF=y |
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@ -0,0 +1,234 @@ |
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/*
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* Copyright 2015 Toradex, Inc. |
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* |
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* Configuration settings for the Toradex VF50/VF61 module. |
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* |
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* Based on vf610twr.h: |
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <asm/arch/imx-regs.h> |
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#include <config_cmd_default.h> |
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#define CONFIG_VF610 |
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#define CONFIG_SYS_THUMB_BUILD |
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#define CONFIG_USE_ARCH_MEMCPY |
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#define CONFIG_USE_ARCH_MEMSET |
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#define CONFIG_SYS_GENERIC_BOARD |
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#define CONFIG_ARCH_MISC_INIT |
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#define CONFIG_DISPLAY_CPUINFO |
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#define CONFIG_DISPLAY_BOARDINFO |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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|
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#define CONFIG_CMD_FUSE |
||||
#ifdef CONFIG_CMD_FUSE |
||||
#define CONFIG_MXC_OCOTP |
||||
#endif |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
#define CONFIG_FSL_LPUART |
||||
#define LPUART_BASE UART0_BASE |
||||
|
||||
/* Allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
||||
#define CONFIG_VERSION_VARIABLE |
||||
#define CONFIG_SYS_UART_PORT (0) |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_CMD_ASKENV |
||||
|
||||
/* NAND support */ |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_NAND_VF610_NFC |
||||
#define CONFIG_SYS_NAND_SELF_INIT |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR |
||||
|
||||
/* Dynamic MTD partition support */ |
||||
#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */ |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
||||
#define MTDIDS_DEFAULT "nand0=vf610_nfc" |
||||
#define MTDPARTS_DEFAULT "mtdparts=vf610_nfc:" \ |
||||
"128k(vf-bcb)ro," \
|
||||
"1408k(u-boot)ro," \
|
||||
"512k(u-boot-env)," \
|
||||
"-(ubi)" |
||||
|
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1 |
||||
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
||||
|
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_EXT3 |
||||
#define CONFIG_CMD_EXT4 |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_RBTREE |
||||
#define CONFIG_LZO |
||||
#define CONFIG_CMD_FS_GENERIC |
||||
#define CONFIG_CMD_BOOTZ |
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_MTD_UBI_FASTMAP |
||||
#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */ |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_MII |
||||
#define IMX_FEC_BASE ENET1_BASE_ADDR |
||||
#define CONFIG_FEC_XCV_TYPE RMII |
||||
#define CONFIG_FEC_MXC_PHYADDR 0 |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_MICREL |
||||
|
||||
#define CONFIG_IPADDR 192.168.10.2 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_SERVERIP 192.168.10.1 |
||||
|
||||
#define CONFIG_BOOTDELAY 1 |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
#define CONFIG_LOADADDR 0x80008000 |
||||
#define CONFIG_FDTADDR 0x84000000 |
||||
|
||||
/* We boot from the gfxRAM area of the OCRAM. */ |
||||
#define CONFIG_SYS_TEXT_BASE 0x3f408000 |
||||
#define CONFIG_BOARD_SIZE_LIMIT 524288 |
||||
|
||||
#define SD_BOOTCMD \ |
||||
"sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \
|
||||
"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
|
||||
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
|
||||
"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
|
||||
"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
|
||||
"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
|
||||
#define NFS_BOOTCMD \ |
||||
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
|
||||
"nfsboot=run setup; " \
|
||||
"setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \
|
||||
"${setupargs} ${vidargs}; echo Booting from NFS...;" \
|
||||
"dhcp ${kernel_addr_r} && " \
|
||||
"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
|
||||
"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
|
||||
#define UBI_BOOTCMD \ |
||||
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
|
||||
"ubi.fm_autoconvert=1\0" \
|
||||
"ubiboot=run setup; " \
|
||||
"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \
|
||||
"${setupargs} ${vidargs}; echo Booting from NAND...; " \
|
||||
"ubi part ubi && ubifsmount ubi0:rootfs && " \
|
||||
"ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \
|
||||
"ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
|
||||
"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"kernel_addr_r=0x82000000\0" \
|
||||
"fdt_addr_r=0x84000000\0" \
|
||||
"kernel_file=zImage\0" \
|
||||
"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
|
||||
"fdt_board=eval-v3\0" \
|
||||
"defargs=\0" \
|
||||
"console=ttyLP0\0" \
|
||||
"setup=setenv setupargs " \
|
||||
"console=tty1 console=${console}" \
|
||||
",${baudrate}n8 ${memargs}\0" \
|
||||
"setsdupdate=mmc rescan && set interface mmc && " \
|
||||
"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
|
||||
"source ${loadaddr}\0" \
|
||||
"setusbupdate=usb start && set interface usb && " \
|
||||
"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
|
||||
"source ${loadaddr}\0" \
|
||||
"setupdate=run setsdupdate || run setusbupdate\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
SD_BOOTCMD \
|
||||
NFS_BOOTCMD \
|
||||
UBI_BOOTCMD |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_SYS_PROMPT "Colibri VFxx # " |
||||
#undef CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE \ |
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_CMD_MEMTEST |
||||
#define CONFIG_SYS_MEMTEST_START 0x80010000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x87C00000 |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ |
||||
|
||||
/* Physical memory map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM (0x80000000) |
||||
#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* Environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#define CONFIG_ENV_OFFSET (12 * 64 * 1024) |
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_NAND |
||||
#define CONFIG_ENV_SIZE (64 * 2048) |
||||
#define CONFIG_ENV_RANGE (4 * 64 * 2048) |
||||
#define CONFIG_ENV_OFFSET (12 * 64 * 2048) |
||||
#endif |
||||
|
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_CMD_BOOTZ |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue