Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok. Detail verification message please see doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>master
Rick Chen
7 years ago
committed by
Tom Rini
parent
373b900341
commit
e8e39597a3
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#
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# Copyright (C) 2017 Andes Technology Corporation
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# Rick Chen, Andes Technology Corporation <rick@andestech.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-y := cpu.o
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/*
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* Copyright (C) 2017 Andes Technology Corporation |
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* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/* CPU specific code */ |
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#include <common.h> |
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#include <command.h> |
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#include <watchdog.h> |
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#include <asm/cache.h> |
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/*
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* cleanup_before_linux() is called just before we call linux |
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* it prepares the processor for linux |
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* |
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* we disable interrupt and caches. |
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*/ |
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int cleanup_before_linux(void) |
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{ |
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disable_interrupts(); |
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/* turn off I/D-cache */ |
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return 0; |
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} |
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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disable_interrupts(); |
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panic("nx25-ae250 wdt not support yet.\n"); |
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} |
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@ -0,0 +1,291 @@ |
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/* |
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* Startup Code for RISC-V Core |
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* |
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* Copyright (c) 2017 Microsemi Corporation. |
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* Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
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* |
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* Copyright (C) 2017 Andes Technology Corporation |
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm-offsets.h> |
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#include <config.h> |
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#include <common.h> |
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#include <elf.h> |
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#include <asm/encoding.h> |
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#ifdef CONFIG_32BIT |
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#define LREG lw |
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#define SREG sw |
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#define REGBYTES 4 |
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#define RELOC_TYPE R_RISCV_32 |
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#define SYM_INDEX 0x8 |
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#define SYM_SIZE 0x10 |
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#else |
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#define LREG ld |
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#define SREG sd |
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#define REGBYTES 8 |
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#define RELOC_TYPE R_RISCV_64 |
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#define SYM_INDEX 0x20 |
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#define SYM_SIZE 0x18 |
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#endif |
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.section .text |
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.globl _start
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_start: |
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j handle_reset |
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nmi_vector: |
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j nmi_vector |
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trap_vector: |
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j trap_entry |
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.global trap_entry
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handle_reset: |
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la t0, trap_entry |
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csrw mtvec, t0 |
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csrwi mstatus, 0 |
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csrwi mie, 0 |
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/* |
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* Do CPU critical regs init only at reboot, |
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* not when booting from ram |
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*/ |
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#ifdef CONFIG_INIT_CRITICAL |
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jal cpu_init_crit /* Do CPU critical regs init */ |
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#endif |
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/* |
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* Set stackpointer in internal/ex RAM to call board_init_f |
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*/ |
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call_board_init_f: |
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li t0, -16 |
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li t1, CONFIG_SYS_INIT_SP_ADDR |
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and sp, t1, t0 /* force 16 byte alignment */ |
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#ifdef CONFIG_DEBUG_UART |
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jal debug_uart_init |
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#endif |
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call_board_init_f_0: |
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mv a0, sp |
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jal board_init_f_alloc_reserve |
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mv sp, a0 |
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jal board_init_f_init_reserve |
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mv a0, zero /* a0 <-- boot_flags = 0 */ |
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la t5, board_init_f |
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jr t5 /* jump to board_init_f() */ |
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/* |
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* void relocate_code (addr_sp, gd, addr_moni) |
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* |
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* This "function" does not return, instead it continues in RAM |
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* after relocating the monitor code. |
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* |
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*/ |
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.globl relocate_code
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relocate_code: |
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mv s2, a0 /* save addr_sp */ |
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mv s3, a1 /* save addr of gd */ |
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mv s4, a2 /* save addr of destination */ |
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/* |
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*Set up the stack |
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*/ |
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stack_setup: |
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mv sp, s2 |
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la t0, _start |
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sub t6, s4, t0 /* t6 <- relocation offset */ |
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beq t0, s4, clear_bss /* skip relocation */ |
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mv t1, s4 /* t1 <- scratch for copy_loop */ |
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la t3, __bss_start |
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sub t3, t3, t0 /* t3 <- __bss_start_ofs */ |
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add t2, t0, t3 /* t2 <- source end address */ |
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copy_loop: |
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LREG t5, 0(t0) |
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addi t0, t0, REGBYTES |
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SREG t5, 0(t1) |
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addi t1, t1, REGBYTES |
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blt t0, t2, copy_loop |
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/* |
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* Update dynamic relocations after board_init_f |
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*/ |
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fix_rela_dyn: |
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la t1, __rel_dyn_start |
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la t2, __rel_dyn_end |
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beq t1, t2, clear_bss |
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add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */ |
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add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */ |
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/* |
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* skip first reserved entry: address, type, addend |
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*/ |
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bne t1, t2, 7f |
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6: |
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LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ |
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li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ |
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bne t5, t3, 8f /* skip non-RISCV_RELOC entries */ |
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LREG t3, -(REGBYTES*3)(t1) |
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LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */ |
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add t5, t5, t6 /* t5 <-- location to fix up in RAM */ |
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add t3, t3, t6 /* t3 <-- location to fix up in RAM */ |
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SREG t5, 0(t3) |
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7: |
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addi t1, t1, (REGBYTES*3) |
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ble t1, t2, 6b |
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8: |
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la t4, __dyn_sym_start |
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add t4, t4, t6 |
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9: |
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LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ |
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srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ |
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andi t5, t5, 0xFF /* t5 <--- relocation type */ |
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li t3, RELOC_TYPE |
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bne t5, t3, 10f /* skip non-addned entries */ |
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LREG t3, -(REGBYTES*3)(t1) |
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li t5, SYM_SIZE |
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mul t0, t0, t5 |
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add s1, t4, t0 |
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LREG t5, REGBYTES(s1) |
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add t5, t5, t6 /* t5 <-- location to fix up in RAM */ |
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add t3, t3, t6 /* t3 <-- location to fix up in RAM */ |
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SREG t5, 0(t3) |
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10: |
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addi t1, t1, (REGBYTES*3) |
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ble t1, t2, 9b |
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/* |
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* trap update |
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*/ |
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la t0, trap_entry |
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add t0, t0, t6 |
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csrw mtvec, t0 |
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clear_bss: |
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la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ |
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add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ |
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la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ |
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add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ |
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li t2, 0x00000000 /* clear */ |
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beq t0, t1, call_board_init_r |
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clbss_l: |
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SREG t2, 0(t0) /* clear loop... */ |
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addi t0, t0, REGBYTES |
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bne t0, t1, clbss_l |
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/* |
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* We are done. Do not return, instead branch to second part of board |
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* initialization, now running from RAM. |
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*/ |
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call_board_init_r: |
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la t0, board_init_r |
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mv t4, t0 /* offset of board_init_r() */ |
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add t4, t4, t6 /* real address of board_init_r() */ |
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/* |
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* setup parameters for board_init_r |
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*/ |
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mv a0, s3 /* gd_t */ |
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mv a1, s4 /* dest_addr */ |
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/* |
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* jump to it ... |
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*/ |
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jr t4 /* jump to board_init_r() */ |
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/* |
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* trap entry |
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*/ |
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trap_entry: |
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addi sp, sp, -32*REGBYTES |
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SREG x1, 1*REGBYTES(sp) |
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SREG x2, 2*REGBYTES(sp) |
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SREG x3, 3*REGBYTES(sp) |
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SREG x4, 4*REGBYTES(sp) |
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SREG x5, 5*REGBYTES(sp) |
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SREG x6, 6*REGBYTES(sp) |
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SREG x7, 7*REGBYTES(sp) |
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SREG x8, 8*REGBYTES(sp) |
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SREG x9, 9*REGBYTES(sp) |
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SREG x10, 10*REGBYTES(sp) |
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SREG x11, 11*REGBYTES(sp) |
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SREG x12, 12*REGBYTES(sp) |
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SREG x13, 13*REGBYTES(sp) |
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SREG x14, 14*REGBYTES(sp) |
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SREG x15, 15*REGBYTES(sp) |
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SREG x16, 16*REGBYTES(sp) |
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SREG x17, 17*REGBYTES(sp) |
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SREG x18, 18*REGBYTES(sp) |
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SREG x19, 19*REGBYTES(sp) |
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SREG x20, 20*REGBYTES(sp) |
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SREG x21, 21*REGBYTES(sp) |
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SREG x22, 22*REGBYTES(sp) |
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SREG x23, 23*REGBYTES(sp) |
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SREG x24, 24*REGBYTES(sp) |
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SREG x25, 25*REGBYTES(sp) |
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SREG x26, 26*REGBYTES(sp) |
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SREG x27, 27*REGBYTES(sp) |
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SREG x28, 28*REGBYTES(sp) |
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SREG x29, 29*REGBYTES(sp) |
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SREG x30, 30*REGBYTES(sp) |
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SREG x31, 31*REGBYTES(sp) |
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csrr a0, mcause |
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csrr a1, mepc |
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mv a2, sp |
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jal handle_trap |
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csrw mepc, a0 |
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/* |
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* Remain in M-mode after mret |
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*/ |
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li t0, MSTATUS_MPP |
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csrs mstatus, t0 |
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LREG x1, 1*REGBYTES(sp) |
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LREG x2, 2*REGBYTES(sp) |
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LREG x3, 3*REGBYTES(sp) |
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LREG x4, 4*REGBYTES(sp) |
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LREG x5, 5*REGBYTES(sp) |
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LREG x6, 6*REGBYTES(sp) |
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LREG x7, 7*REGBYTES(sp) |
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LREG x8, 8*REGBYTES(sp) |
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LREG x9, 9*REGBYTES(sp) |
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LREG x10, 10*REGBYTES(sp) |
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LREG x11, 11*REGBYTES(sp) |
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LREG x12, 12*REGBYTES(sp) |
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LREG x13, 13*REGBYTES(sp) |
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LREG x14, 14*REGBYTES(sp) |
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LREG x15, 15*REGBYTES(sp) |
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LREG x16, 16*REGBYTES(sp) |
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LREG x17, 17*REGBYTES(sp) |
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LREG x18, 18*REGBYTES(sp) |
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LREG x19, 19*REGBYTES(sp) |
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LREG x20, 20*REGBYTES(sp) |
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LREG x21, 21*REGBYTES(sp) |
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LREG x22, 22*REGBYTES(sp) |
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LREG x23, 23*REGBYTES(sp) |
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LREG x24, 24*REGBYTES(sp) |
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LREG x25, 25*REGBYTES(sp) |
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LREG x26, 26*REGBYTES(sp) |
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LREG x27, 27*REGBYTES(sp) |
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LREG x28, 28*REGBYTES(sp) |
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LREG x29, 29*REGBYTES(sp) |
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LREG x30, 30*REGBYTES(sp) |
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LREG x31, 31*REGBYTES(sp) |
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addi sp, sp, 32*REGBYTES |
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mret |
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#ifdef CONFIG_INIT_CRITICAL |
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cpu_init_crit: |
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ret |
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#endif |
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@ -0,0 +1,69 @@ |
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/* |
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* Copyright (C) 2017 Andes Technology Corporation |
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* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_ARCH("riscv") |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = ALIGN(4); |
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.text : |
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{ |
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arch/riscv/cpu/nx25/start.o (.text) |
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*(.text) |
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} |
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. = ALIGN(4); |
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.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
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. = ALIGN(4); |
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.data : { |
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__global_pointer$ = . + 0x800; |
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*(.data*) |
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} |
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. = ALIGN(4); |
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.got : { |
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__got_start = .; |
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*(.got.plt) *(.got) |
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__got_end = .; |
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} |
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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. = ALIGN(4); |
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/DISCARD/ : { *(.rela.plt*) } |
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.rela.dyn : { |
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__rel_dyn_start = .; |
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*(.rela*) |
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__rel_dyn_end = .; |
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} |
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. = ALIGN(4); |
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.dynsym : { |
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__dyn_sym_start = .; |
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*(.dynsym) |
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__dyn_sym_end = .; |
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} |
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. = ALIGN(4); |
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_end = .; |
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.bss : { |
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__bss_start = .; |
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*(.bss) |
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. = ALIGN(4); |
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__bss_end = .; |
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} |
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} |
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