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avr32: rename mmu.h definitions

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Prefix mmu.h PAGE_xxx definitions with MMU_ in order to prevent a naming
conflict with other definitions.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
master
Andreas Bießmann 10 years ago
parent 26db7903f5
commit e9ed41cc5c
9 changed files with 55 additions and 55 deletions
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  1. 8
      arch/avr32/cpu/at32ap700x/mmu.c
  2. 6
      arch/avr32/include/asm/arch-at32ap700x/mmu.h
  3. 12
      board/atmel/atngw100/atngw100.c
  4. 18
      board/atmel/atngw100mkii/atngw100mkii.c
  5. 12
      board/atmel/atstk1000/atstk1000.c
  6. 12
      board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
  7. 12
      board/in-circuit/grasshopper/grasshopper.c
  8. 18
      board/mimc/mimc200/mimc200.c
  9. 12
      board/miromico/hammerhead/hammerhead.c

8
arch/avr32/cpu/at32ap700x/mmu.c
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@ -7,7 +7,7 @@ void mmu_init_r(unsigned long dest_addr)
uintptr_t vmr_table_addr; uintptr_t vmr_table_addr;
/* Round monitor address down to the nearest page boundary */ /* Round monitor address down to the nearest page boundary */
dest_addr &= PAGE_ADDR_MASK; dest_addr &= MMU_PAGE_ADDR_MASK;
/* Initialize TLB entry 0 to cover the monitor, and lock it */ /* Initialize TLB entry 0 to cover the monitor, and lock it */
sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V)); sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V));
@ -36,7 +36,7 @@ int mmu_handle_tlb_miss(void)
unsigned int fault_pgno; unsigned int fault_pgno;
int first, last; int first, last;
fault_pgno = sysreg_read(TLBEAR) >> PAGE_SHIFT; fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT;
vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR); vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR);
/* Do a binary search through the VM ranges */ /* Do a binary search through the VM ranges */
@ -60,8 +60,8 @@ int mmu_handle_tlb_miss(void)
/* Got it; let's slam it into the TLB */ /* Got it; let's slam it into the TLB */
uint32_t tlbelo; uint32_t tlbelo;
tlbelo = vmr->phys & ~PAGE_ADDR_MASK; tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK;
tlbelo |= fault_pgno << PAGE_SHIFT; tlbelo |= fault_pgno << MMU_PAGE_SHIFT;
sysreg_write(TLBELO, tlbelo); sysreg_write(TLBELO, tlbelo);
__builtin_tlbw(); __builtin_tlbw();

6
arch/avr32/include/asm/arch-at32ap700x/mmu.h
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@ -13,9 +13,9 @@
#include <asm/sysreg.h> #include <asm/sysreg.h>
#define PAGE_SHIFT 20 #define MMU_PAGE_SHIFT 20
#define PAGE_SIZE (1UL << PAGE_SHIFT) #define MMU_PAGE_SIZE (1UL << MMU_PAGE_SHIFT)
#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1)) #define MMU_PAGE_ADDR_MASK (~(MMU_PAGE_SIZE - 1))
#define MMU_VMR_CACHE_NONE \ #define MMU_VMR_CACHE_NONE \
(SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D)) (SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D))

12
board/atmel/atngw100/atngw100.c
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@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{ {
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE, | MMU_VMR_CACHE_NONE,
}, { }, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK, | MMU_VMR_CACHE_WRBACK,
}, },
}; };

18
board/atmel/atngw100mkii/atngw100mkii.c
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@ -23,21 +23,21 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{ {
/* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */ /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE, | MMU_VMR_CACHE_NONE,
}, { }, {
/* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */ /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
.virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT, .virt_pgno = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT, .nr_pages = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT,
.phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT) .phys = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE, | MMU_VMR_CACHE_NONE,
}, { }, {
/* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */ /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK, | MMU_VMR_CACHE_WRBACK,
}, },
}; };

12
board/atmel/atstk1000/atstk1000.c
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@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{ {
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE, | MMU_VMR_CACHE_NONE,
}, { }, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK, | MMU_VMR_CACHE_WRBACK,
}, },
}; };

12
board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
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@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{ {
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE, | MMU_VMR_CACHE_NONE,
}, { }, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK, | MMU_VMR_CACHE_WRBACK,
}, },
}; };

12
board/in-circuit/grasshopper/grasshopper.c
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@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{ {
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE, | MMU_VMR_CACHE_NONE,
}, { }, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK, | MMU_VMR_CACHE_WRBACK,
}, },
}; };

18
board/mimc/mimc200/mimc200.c
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@ -20,19 +20,19 @@
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{ {
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE, | MMU_VMR_CACHE_NONE,
}, { }, {
.virt_pgno = EBI_SRAM_CS2_BASE >> PAGE_SHIFT, .virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT, .nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
.phys = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT) .phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE, | MMU_VMR_CACHE_NONE,
}, { }, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK, | MMU_VMR_CACHE_WRBACK,
}, },
}; };

12
board/miromico/hammerhead/hammerhead.c
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@ -21,14 +21,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{ {
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE, | MMU_VMR_CACHE_NONE,
}, { }, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK, | MMU_VMR_CACHE_WRBACK,
}, },
}; };

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