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dm: x86: spi: Convert ICH SPI driver to driver model PCI API

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At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.

Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.

This patch includes Bin's fix-up patch from here:

   https://patchwork.ozlabs.org/patch/569478/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
master
Simon Glass 9 years ago committed by Bin Meng
parent fffe25db04
commit f2b85ab5e6
13 changed files with 461 additions and 442 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 3
      arch/x86/cpu/coreboot/pci.c
  2. 7
      arch/x86/cpu/irq.c
  3. 47
      arch/x86/cpu/ivybridge/bd82x6x.c
  4. 46
      arch/x86/dts/bayleybay.dts
  5. 8
      arch/x86/dts/broadwell_som-6896.dts
  6. 5
      arch/x86/dts/chromebook_link.dts
  7. 10
      arch/x86/dts/chromebox_panther.dts
  8. 40
      arch/x86/dts/crownbay.dts
  9. 39
      arch/x86/dts/galileo.dts
  10. 46
      arch/x86/dts/minnowmax.dts
  11. 6
      arch/x86/dts/qemu-x86_i440fx.dts
  12. 6
      arch/x86/dts/qemu-x86_q35.dts
  13. 152
      drivers/spi/ich.c

3
arch/x86/cpu/coreboot/pci.c
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@ -14,7 +14,8 @@
#include <pci.h>
static const struct udevice_id generic_pch_ids[] = {
{ .compatible = "intel,pch" },
{ .compatible = "intel,pch7" },
{ .compatible = "intel,pch9" },
{ }
};

7
arch/x86/cpu/irq.c
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@ -97,6 +97,7 @@ static int create_pirq_routing_table(void)
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
int parent;
int i;
int ret;
@ -106,7 +107,11 @@ static int create_pirq_routing_table(void)
return -EINVAL;
}
ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG,
/* TODO(sjg@chromium.org): Drop this when PIRQ is a driver */
parent = fdt_parent_offset(blob, node);
if (parent < 0)
return -EINVAL;
ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
"reg", &addr);
if (ret)
return ret;

47
arch/x86/cpu/ivybridge/bd82x6x.c
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@ -3,12 +3,12 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <pch.h>
#include <asm/lapic.h>
#include <asm/pci.h>
#include <asm/arch/bd82x6x.h>
@ -16,6 +16,8 @@
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
#define BIOS_CTRL 0xdc
void bd82x6x_pci_init(pci_dev_t dev)
{
u16 reg16;
@ -96,6 +98,7 @@ static int bd82x6x_probe(struct udevice *dev)
return 0;
}
/* TODO(sjg@chromium.org): Move this to the PCH init() method */
int bd82x6x_init(void)
{
const void *blob = gd->fdt_blob;
@ -116,6 +119,47 @@ int bd82x6x_init(void)
return 0;
}
static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
{
u32 rcba;
dm_pci_read_config32(dev, PCH_RCBA, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
rcba = rcba & 0xffffc000;
*sbasep = rcba + 0x3800;
return 0;
}
static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
{
return PCHV_9;
}
static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
{
uint8_t bios_cntl;
/* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
if (protect) {
bios_cntl &= ~BIOS_CTRL_BIOSWE;
bios_cntl |= BIT(5);
} else {
bios_cntl |= BIOS_CTRL_BIOSWE;
bios_cntl &= ~BIT(5);
}
dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
return 0;
}
static const struct pch_ops bd82x6x_pch_ops = {
.get_sbase = bd82x6x_pch_get_sbase,
.get_version = bd82x6x_pch_get_version,
.set_spi_protect = bd82x6x_set_spi_protect,
};
static const struct udevice_id bd82x6x_ids[] = {
{ .compatible = "intel,bd82x6x" },
{ }
@ -126,4 +170,5 @@ U_BOOT_DRIVER(bd82x6x_drv) = {
.id = UCLASS_PCH,
.of_match = bd82x6x_ids,
.probe = bd82x6x_probe,
.ops = &bd82x6x_pch_ops,
};

46
arch/x86/dts/bayleybay.dts
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@ -65,23 +65,6 @@
};
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64dw", "spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x006e0000 0x00010000>;
};
};
};
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
@ -133,8 +116,11 @@
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
irq-router@1f,0 {
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch9";
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "ibase";
intel,ibase-offset = <0x50>;
@ -175,7 +161,10 @@
PCI_BDF(0, 30, 5) INTB PIRQB
PCI_BDF(0, 31, 3) INTB PIRQB
/* PCIe root ports downstream interrupts */
/*
* PCIe root ports downstream
* interrupts
*/
PCI_BDF(1, 0, 0) INTA PIRQA
PCI_BDF(1, 0, 0) INTB PIRQB
PCI_BDF(1, 0, 0) INTC PIRQC
@ -194,6 +183,25 @@
PCI_BDF(4, 0, 0) INTD PIRQC
>;
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64dw",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x006e0000 0x00010000>;
};
};
};
};
};
fsp {

8
arch/x86/dts/broadwell_som-6896.dts
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@ -29,7 +29,10 @@
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
};
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch9";
spi {
#address-cells = <1>;
@ -41,4 +44,7 @@
memory-map = <0xff000000 0x01000000>;
};
};
};
};
};

5
arch/x86/dts/chromebook_link.dts
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@ -186,9 +186,9 @@
intel,pch-backlight = <0x04000000>;
};
pch {
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,bd82x6x", "intel,pch";
compatible = "intel,bd82x6x", "intel,pch9";
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
@ -200,6 +200,7 @@
1 0 0 0 0 0 0 0>;
/* Enable EC SMI source */
intel,alt-gp-smi-enable = <0x0100>;
spi {
#address-cells = <1>;
#size-cells = <0>;

10
arch/x86/dts/chromebox_panther.dts
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@ -51,7 +51,10 @@
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xf000>;
};
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch9";
spi {
#address-cells = <1>;
@ -61,7 +64,8 @@
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64", "spi-flash";
compatible = "winbond,w25q64",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
@ -69,6 +73,8 @@
};
};
};
};
};
tpm {
reg = <0xfed40000 0x5000>;

40
arch/x86/dts/crownbay.dts
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@ -72,17 +72,6 @@
stdout-path = "/serial";
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
reg = <0>;
compatible = "sst,25vf016b", "spi-flash";
memory-map = <0xffe00000 0x00200000>;
};
};
microcode {
update@0 {
#include "microcode/m0220661105_cv.dtsi"
@ -170,8 +159,11 @@
};
};
irq-router@1f,0 {
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch7";
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
@ -200,11 +192,12 @@
/*
* Topcliff PCI devices
*
* Note on the Crown Bay board, Topcliff chipset
* is connected to TunnelCreek PCIe port 0, so
* its bus number is 1 for its PCIe port and 2
* for its PCI devices per U-Boot current PCI
* bus enumeration algorithm.
* Note on the Crown Bay board, Topcliff
* chipset is connected to TunnelCreek
* PCIe port 0, so its bus number is 1
* for its PCIe port and 2 for its PCI
* devices per U-Boot current PCI bus
* enumeration algorithm.
*/
PCI_BDF(1, 0, 0) INTA PIRQA
PCI_BDF(2, 0, 1) INTA PIRQA
@ -233,6 +226,19 @@
PCI_BDF(2, 12, 4) INTC PIRQC
>;
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
reg = <0>;
compatible = "sst,25vf016b",
"spi-flash";
memory-map = <0xffe00000 0x00200000>;
};
};
};
};
};

39
arch/x86/dts/galileo.dts
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@ -79,8 +79,11 @@
current-speed = <115200>;
};
irq-router@1f,0 {
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch7";
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
@ -111,21 +114,6 @@
PCI_BDF(2, 0, 0) INTD PIRQA
>;
};
};
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
};
spi {
#address-cells = <1>;
@ -135,7 +123,8 @@
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64", "spi-flash";
compatible = "winbond,w25q64",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
@ -143,5 +132,21 @@
};
};
};
};
};
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
};
};

46
arch/x86/dts/minnowmax.dts
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@ -150,8 +150,11 @@
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
irq-router@1f,0 {
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "pci8086,0f1c", "intel,pch9";
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "ibase";
intel,ibase-offset = <0x50>;
@ -192,7 +195,10 @@
PCI_BDF(0, 30, 5) INTB PIRQB
PCI_BDF(0, 31, 3) INTB PIRQB
/* PCIe root ports downstream interrupts */
/*
* PCIe root ports downstream
* interrupts
*/
PCI_BDF(1, 0, 0) INTA PIRQA
PCI_BDF(1, 0, 0) INTB PIRQB
PCI_BDF(1, 0, 0) INTC PIRQC
@ -211,6 +217,25 @@
PCI_BDF(4, 0, 0) INTD PIRQC
>;
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "stmicro,n25q064a",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x006f0000 0x00010000>;
};
};
};
};
};
fsp {
@ -269,23 +294,6 @@
};
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "stmicro,n25q064a", "spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x006f0000 0x00010000>;
};
};
};
microcode {
update@0 {
#include "microcode/m0130673322.dtsi"

6
arch/x86/dts/qemu-x86_i440fx.dts
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@ -51,8 +51,11 @@
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
irq-router@1,0 {
pch@1,0 {
reg = <0x00000800 0 0 0 0>;
compatible = "intel,pch7";
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 4>;
@ -65,5 +68,6 @@
>;
};
};
};
};

6
arch/x86/dts/qemu-x86_q35.dts
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@ -62,8 +62,11 @@
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
irq-router@1f,0 {
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch9";
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
@ -82,5 +85,6 @@
>;
};
};
};
};

152
drivers/spi/ich.c
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@ -5,14 +5,14 @@
*
* This file is derived from the flashrom project.
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <pch.h>
#include <pci.h>
#include <pci_ids.h>
#include <spi.h>
#include <asm/io.h>
#include "ich.h"
@ -27,9 +27,7 @@
#endif
struct ich_spi_platdata {
pci_dev_t dev; /* PCI device number */
int ich_version; /* Controller version, 7 or 9 */
bool use_sbase; /* Use SBASE instead of RCB */
enum pch_version ich_version; /* Controller version, 7 or 9 */
};
struct ich_spi_priv {
@ -122,40 +120,16 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
}
/*
* Check if this device ID matches one of supported Intel PCH devices.
*
* Return the ICH version if there is a match, or zero otherwise.
*/
static int get_ich_version(uint16_t device_id)
{
if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
return 7;
if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
(device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||
device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC ||
device_id == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC)
return 9;
return 0;
}
/* @return 1 if the SPI flash supports the 33MHz speed */
static int ich9_can_do_33mhz(pci_dev_t dev)
static int ich9_can_do_33mhz(struct udevice *dev)
{
u32 fdod, speed;
/* Observe SPI Descriptor Component Section 0 */
pci_write_config_dword(dev, 0xb0, 0x1000);
dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
/* Extract the Write/Erase SPI Frequency from descriptor */
pci_read_config_dword(dev, 0xb4, &fdod);
dm_pci_read_config32(dev->parent, 0xb4, &fdod);
/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
speed = (fdod >> 21) & 7;
@ -163,59 +137,22 @@ static int ich9_can_do_33mhz(pci_dev_t dev)
return speed == 1;
}
static int ich_find_spi_controller(struct ich_spi_platdata *ich)
{
int last_bus = pci_last_busno();
int bus;
if (last_bus == -1) {
debug("No PCI busses?\n");
return -ENODEV;
}
for (bus = 0; bus <= last_bus; bus++) {
uint16_t vendor_id, device_id;
uint32_t ids;
pci_dev_t dev;
dev = PCI_BDF(bus, 31, 0);
pci_read_config_dword(dev, 0, &ids);
vendor_id = ids;
device_id = ids >> 16;
if (vendor_id == PCI_VENDOR_ID_INTEL) {
ich->dev = dev;
ich->ich_version = get_ich_version(device_id);
if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
ich->use_sbase = true;
return ich->ich_version == 0 ? -ENODEV : 0;
}
}
debug("ICH SPI: No ICH found.\n");
return -ENODEV;
}
static int ich_init_controller(struct ich_spi_platdata *plat,
static int ich_init_controller(struct udevice *dev,
struct ich_spi_platdata *plat,
struct ich_spi_priv *ctlr)
{
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint32_t sbase_addr;
uint8_t *sbase;
pci_read_config_dword(plat->dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
ulong sbase_addr;
void *sbase;
/* SBASE is similar */
pci_read_config_dword(plat->dev, 0x54, &sbase_addr);
sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
pch_get_sbase(dev->parent, &sbase_addr);
sbase = (void *)sbase_addr;
debug("%s: sbase=%p\n", __func__, sbase);
if (plat->ich_version == 7) {
struct ich7_spi_regs *ich7_spi;
if (plat->ich_version == PCHV_7) {
struct ich7_spi_regs *ich7_spi = sbase;
ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
ich7_spi = (struct ich7_spi_regs *)sbase;
ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich7_spi->opmenu);
@ -228,13 +165,9 @@ static int ich_init_controller(struct ich_spi_platdata *plat,
ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
ctlr->preop = offsetof(struct ich7_spi_regs, preop);
ctlr->base = ich7_spi;
} else if (plat->ich_version == 9) {
struct ich9_spi_regs *ich9_spi;
} else if (plat->ich_version == PCHV_9) {
struct ich9_spi_regs *ich9_spi = sbase;
if (plat->use_sbase)
ich9_spi = (struct ich9_spi_regs *)sbase;
else
ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich9_spi->opmenu);
@ -258,9 +191,9 @@ static int ich_init_controller(struct ich_spi_platdata *plat,
/* Work out the maximum speed we can support */
ctlr->max_speed = 20000000;
if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev))
if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev))
ctlr->max_speed = 33000000;
debug("ICH SPI: Version %d detected at %p, speed %ld\n",
debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
plat->ich_version, ctlr->base, ctlr->max_speed);
ich_set_bbar(ctlr, 0);
@ -487,7 +420,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
if (ret < 0)
return ret;
if (plat->ich_version == 7)
if (plat->ich_version == PCHV_7)
ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
else
ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
@ -682,30 +615,30 @@ int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
return 0;
}
static int ich_spi_probe(struct udevice *bus)
static int ich_spi_probe(struct udevice *dev)
{
struct ich_spi_platdata *plat = dev_get_platdata(bus);
struct ich_spi_priv *priv = dev_get_priv(bus);
struct ich_spi_platdata *plat = dev_get_platdata(dev);
struct ich_spi_priv *priv = dev_get_priv(dev);
uint8_t bios_cntl;
int ret;
ret = ich_init_controller(plat, priv);
/* Check the ICH version */
plat->ich_version = pch_get_version(dev->parent);
ret = ich_init_controller(dev, plat, priv);
if (ret)
return ret;
/*
* Disable the BIOS write protect so write commands are allowed. On
* v9, deassert SMM BIOS Write Protect Disable.
*/
if (plat->use_sbase) {
/* Disable the BIOS write protect so write commands are allowed */
ret = pch_set_spi_protect(dev->parent, false);
if (ret == -ENOSYS) {
bios_cntl = ich_readb(priv, priv->bcr);
bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
bios_cntl |= 1; /* Write Protect Disable (WPD) */
ich_writeb(priv, bios_cntl, priv->bcr);
} else {
pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
if (plat->ich_version == 9)
bios_cntl &= ~BIT(5);
pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
} else if (ret) {
debug("%s: Failed to disable write-protect: err=%d\n",
__func__, ret);
return ret;
}
priv->cur_speed = priv->max_speed;
@ -713,18 +646,6 @@ static int ich_spi_probe(struct udevice *bus)
return 0;
}
static int ich_spi_ofdata_to_platdata(struct udevice *bus)
{
struct ich_spi_platdata *plat = dev_get_platdata(bus);
int ret;
ret = ich_find_spi_controller(plat);
if (ret)
return ret;
return 0;
}
static int ich_spi_set_speed(struct udevice *bus, uint speed)
{
struct ich_spi_priv *priv = dev_get_priv(bus);
@ -757,7 +678,7 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash
*/
if (plat->ich_version == 7) {
if (plat->ich_version == PCHV_7) {
slave->mode_rx = SPI_RX_SLOW;
slave->mode = SPI_TX_BYTE;
}
@ -785,7 +706,6 @@ U_BOOT_DRIVER(ich_spi) = {
.id = UCLASS_SPI,
.of_match = ich_spi_ids,
.ops = &ich_spi_ops,
.ofdata_to_platdata = ich_spi_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
.priv_auto_alloc_size = sizeof(struct ich_spi_priv),
.child_pre_probe = ich_spi_child_pre_probe,

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