@ -1,25 +1,50 @@
/*
/*
* MPC8349 Internal Memory Map * ( C ) Copyright 2004 - 2006 Freescale Semiconductor , Inc .
* Copyright ( c ) 2004 Freescale Semiconductor . *
* Eran Liberty ( liberty @ freescale . com ) * MPC83xx Internal Memory Map
*
* History :
* 20060601 : Daveliu ( daveliu @ freescale . com )
* TanyaJiang ( tanya . jiang @ freescale . com )
* Unified variable names for mpc83xx
* 2005 : Mandy Lavi ( mandy . lavi @ freescale . com )
* support for mpc8360e
* 2004 : Eran Liberty ( liberty @ freescale . com )
* Initialized for mpc8349
* based on :
* MPC8260 Internal Memory Map
* Copyright ( c ) 1999 Dan Malek ( dmalek @ jlc . net )
* MPC85xx Internal Memory Map
* Copyright ( c ) 2002 , 2003 Motorola Inc .
* Xianghua Xiao ( x . xiao @ motorola . com )
*
* This program is free software ; you can redistribute it and / or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation ; either version 2 of
* the License , or ( at your option ) any later version .
*
* This program is distributed in the hope that it will be useful ,
* but WITHOUT ANY WARRANTY ; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE . See the
* GNU General Public License for more details .
*
* You should have received a copy of the GNU General Public License
* along with this program ; if not , write to the Free Software
* Foundation , Inc . , 59 Temple Place , Suite 330 , Boston ,
* MA 02111 - 1307 USA
* *
* based on :
* - MPC8260 Internal Memory Map
* Copyright ( c ) 1999 Dan Malek ( dmalek @ jlc . net )
* - MPC85xx Internal Memory Map
* Copyright ( c ) 2002 , 2003 Motorola Inc .
* Xianghua Xiao ( x . xiao @ motorola . com )
*/ */
# ifndef __IMMAP_8349__ # ifndef __IMMAP_83xx__
# define __IMMAP_8349__ # define __IMMAP_83xx__
# include <config.h>
# include <asm/types.h> # include <asm/types.h>
# include <asm/i2c.h> # include <asm/i2c.h>
/*
/*
* Local Access Window . * Local Access Window .
*/ */
typedef struct law8349 { typedef struct law83xx {
u32 bar ; /* LBIU local access window base address register */ u32 bar ; /* LBIU local access window base address register */
/* Identifies the 20 most-significant address bits of the base of local
/* Identifies the 20 most-significant address bits of the base of local
* access window n . The specified base address should be aligned to the * access window n . The specified base address should be aligned to the
@ -28,12 +53,12 @@ typedef struct law8349 {
# define LAWBAR_BAR 0xFFFFF000 # define LAWBAR_BAR 0xFFFFF000
# define LAWBAR_RES ~(LAWBAR_BAR) # define LAWBAR_RES ~(LAWBAR_BAR)
u32 ar ; /* LBIU local access window attribute register */ u32 ar ; /* LBIU local access window attribute register */
} law8349 _t ; } law83xx _t ;
/*
/*
* System configuration registers . * System configuration registers .
*/ */
typedef struct sysconf8349 { typedef struct sysconf83xx {
u32 immrbar ; /* Internal memory map base address register */ u32 immrbar ; /* Internal memory map base address register */
u8 res0 [ 0x04 ] ; u8 res0 [ 0x04 ] ;
u32 altcbar ; /* Alternate configuration base address register */ u32 altcbar ; /* Alternate configuration base address register */
@ -43,11 +68,11 @@ typedef struct sysconf8349 {
# define ALTCBAR_BASE_ADDR 0xFFF00000 # define ALTCBAR_BASE_ADDR 0xFFF00000
# define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ # define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
u8 res1 [ 0x14 ] ; u8 res1 [ 0x14 ] ;
law8349 _t lblaw [ 4 ] ; /* LBIU local access window */ law83xx _t lblaw [ 4 ] ; /* LBIU local access window */
u8 res2 [ 0x20 ] ; u8 res2 [ 0x20 ] ;
law8349 _t pcilaw [ 2 ] ; /* PCI local access window */ law83xx _t pcilaw [ 2 ] ; /* PCI local access window */
u8 res3 [ 0x30 ] ; u8 res3 [ 0x30 ] ;
law8349 _t ddrlaw [ 2 ] ; /* DDR local access window */ law83xx _t ddrlaw [ 2 ] ; /* DDR local access window */
u8 res4 [ 0x50 ] ; u8 res4 [ 0x50 ] ;
u32 sgprl ; /* System General Purpose Register Low */ u32 sgprl ; /* System General Purpose Register Low */
u32 sgprh ; /* System General Purpose Register High */ u32 sgprh ; /* System General Purpose Register High */
@ -117,7 +142,7 @@ typedef struct sysconf8349 {
# define SICRH_GPIO2_H 0x00000060 # define SICRH_GPIO2_H 0x00000060
# define SICRH_TSOBI1 0x00000002 # define SICRH_TSOBI1 0x00000002
# define SICRH_TSOBI2 0x00000001 # define SICRH_TSOBI2 0x00000001
# define SICRh _RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \ # define SICRH _RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
@ -127,12 +152,12 @@ typedef struct sysconf8349 {
| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
| SICRH_TSOBI2 ) | SICRH_TSOBI2 )
u8 res6 [ 0xE4 ] ; u8 res6 [ 0xE4 ] ;
} sysconf8349 _t ; } sysconf83xx _t ;
/*
/*
* Watch Dog Timer ( WDT ) Registers * Watch Dog Timer ( WDT ) Registers
*/ */
typedef struct wdt8349 { typedef struct wdt83xx {
u8 res0 [ 4 ] ; u8 res0 [ 4 ] ;
u32 swcrr ; /* System watchdog control register */ u32 swcrr ; /* System watchdog control register */
u32 swcnr ; /* System watchdog count register */ u32 swcnr ; /* System watchdog count register */
@ -140,13 +165,14 @@ typedef struct wdt8349 {
# define SWCNR_RES ~(SWCNR_SWCN) # define SWCNR_RES ~(SWCNR_SWCN)
u8 res1 [ 2 ] ; u8 res1 [ 2 ] ;
u16 swsrr ; /* System watchdog service register */ u16 swsrr ; /* System watchdog service register */
# define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field.*/
u8 res2 [ 0xF0 ] ; u8 res2 [ 0xF0 ] ;
} wdt8349 _t ; } wdt83xx _t ;
/*
/*
* RTC / PIT Module Registers * RTC / PIT Module Registers
*/ */
typedef struct rtclk8349 { typedef struct rtclk83xx {
u32 cnr ; /* control register */ u32 cnr ; /* control register */
# define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ # define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */
# define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ # define CNR_CLIN 0x00000040 /* Input Clock Control Bit */
@ -154,21 +180,27 @@ typedef struct rtclk8349 {
# define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ # define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */
# define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) # define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
u32 ldr ; /* load register */ u32 ldr ; /* load register */
# define LDR_CLDV 0xFFFFFFFF / * Contains the 32-bit value to be
* loaded in a 32 - bit RTC counter . */
u32 psr ; /* prescale register */ u32 psr ; /* prescale register */
u32 ctr ; /* register */ # define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits.*/
u32 ctr ; /* Counter value field register */
# define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field.*/
u32 evr ; /* event register */ u32 evr ; /* event register */
# define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ # define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */
# define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ # define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */
# define RTEVR_RES ~(EVR_SIF | EVR_AIF) # define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF)
# define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit.*/
# define PTEVR_RES ~(PTEVR_PIF)
u32 alr ; /* alarm register */ u32 alr ; /* alarm register */
u8 res0 [ 0xE8 ] ; u8 res0 [ 0xE8 ] ;
} rtclk8349 _t ; } rtclk83xx _t ;
/*
/*
* Global timper module * Global timper module
*/ */
typedef struct gtm8349 { typedef struct gtm83xx {
u8 cfr1 ; /* Timer1/2 Configuration */ u8 cfr1 ; /* Timer1/2 Configuration */
# define CFR1_PCAS 0x80 /* Pair Cascade mode */ # define CFR1_PCAS 0x80 /* Pair Cascade mode */
# define CFR1_BCM 0x40 /* Backward compatible mode */ # define CFR1_BCM 0x40 /* Backward compatible mode */
@ -178,6 +210,8 @@ typedef struct gtm8349 {
# define CFR1_GM1 0x04 /* Gate mode for pin 1 */ # define CFR1_GM1 0x04 /* Gate mode for pin 1 */
# define CFR1_STP1 0x02 /* Stop timer */ # define CFR1_STP1 0x02 /* Stop timer */
# define CFR1_RST1 0x01 /* Reset timer */ # define CFR1_RST1 0x01 /* Reset timer */
# define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\
CFR1_GM1 | CFR1_STP1 | CFR1_RST1 )
u8 res0 [ 3 ] ; u8 res0 [ 3 ] ;
u8 cfr2 ; /* Timer3/4 Configuration */ u8 cfr2 ; /* Timer3/4 Configuration */
# define CFR2_PCAS 0x80 /* Pair Cascade mode */ # define CFR2_PCAS 0x80 /* Pair Cascade mode */
@ -223,13 +257,15 @@ typedef struct gtm8349 {
u16 psr2 ; /* Timer2 Prescaler Register */ u16 psr2 ; /* Timer2 Prescaler Register */
u16 psr3 ; /* Timer3 Prescaler Register */ u16 psr3 ; /* Timer3 Prescaler Register */
u16 psr4 ; /* Timer4 Prescaler Register */ u16 psr4 ; /* Timer4 Prescaler Register */
# define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */
# define GTPSR_RES ~(GTPSR_PPS)
u8 res [ 0xC0 ] ; u8 res [ 0xC0 ] ;
} gtm8349_t ; } gtm83xx _t ;
/*
/*
* Integrated Programmable Interrupt Controller * Integrated Programmable Interrupt Controller
*/ */
typedef struct ipic8349 { typedef struct ipic83xx {
u32 sicfr ; /* System Global Interrupt Configuration Register (SICFR) */ u32 sicfr ; /* System Global Interrupt Configuration Register (SICFR) */
# define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ # define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */
# define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ # define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */
@ -255,7 +291,7 @@ typedef struct ipic8349 {
# define SIIH_UART2 0x00000040 /* UART2 interrupt */ # define SIIH_UART2 0x00000040 /* UART2 interrupt */
# define SIIH_SEC 0x00000020 /* SEC interrupt */ # define SIIH_SEC 0x00000020 /* SEC interrupt */
# define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ # define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
# define SIIH_I2C2 0x00000002 /* I2C1 interrupt */ # define SIIH_I2C2 0x00000002 /* I2C2 interrupt */
# define SIIH_SPI 0x00000001 /* SPI interrupt */ # define SIIH_SPI 0x00000001 /* SPI interrupt */
# define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ # define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
@ -361,13 +397,23 @@ typedef struct ipic8349 {
u32 sifcr_l ; /* System Internal Interrupt Force Register - Low (SIIL) */ u32 sifcr_l ; /* System Internal Interrupt Force Register - Low (SIIL) */
u32 sefcr ; /* System External Interrupt Force Register (SEI) */ u32 sefcr ; /* System External Interrupt Force Register (SEI) */
u32 serfr ; /* System Error Force Register (SERR) */ u32 serfr ; /* System Error Force Register (SERR) */
u8 res3 [ 0xA0 ] ; u32 scvcr ; /* System Critical Interrupt Vector Register */
} ipic8349_t ; # define SCVCR_CVECX 0xFC000000 / * Backward (MPC8260) compatible
critical interrupt vector . */
# define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */
# define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC)
u32 smvcr ; /* System Management Interrupt Vector Register */
# define SMVCR_CVECX 0xFC000000 / * Backward (MPC8260) compatible
critical interrupt vector . */
# define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */
# define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC)
u8 res3 [ 0x98 ] ;
} ipic83xx_t ;
/*
/*
* System Arbiter Registers * System Arbiter Registers
*/ */
typedef struct arbiter8349 { typedef struct arbiter83xx {
u32 acr ; /* Arbiter Configuration Register */ u32 acr ; /* Arbiter Configuration Register */
# define ACR_COREDIS 0x10000000 /* Core disable. */ # define ACR_COREDIS 0x10000000 /* Core disable. */
# define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ # define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */
@ -401,12 +447,12 @@ typedef struct arbiter8349 {
# define AE_ATO 0x00000001 /* Address time out. */ # define AE_ATO 0x00000001 /* Address time out. */
# define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO) # define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
u8 res1 [ 0xDC ] ; u8 res1 [ 0xDC ] ;
} arbiter8349 _t ; } arbiter83xx _t ;
/*
/*
* Reset Module * Reset Module
*/ */
typedef struct reset8349 { typedef struct reset83xx {
u32 rcwl ; /* RCWL Register */ u32 rcwl ; /* RCWL Register */
# define RCWL_LBIUCM 0x80000000 /* LBIUCM */ # define RCWL_LBIUCM 0x80000000 /* LBIUCM */
# define RCWL_LBIUCM_SHIFT 31 # define RCWL_LBIUCM_SHIFT 31
@ -420,7 +466,7 @@ typedef struct reset8349 {
# define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ # define RCWL_CEVCOD 0x000000C0 /* CEVCOD */
# define RCWL_CEPDF 0x00000020 /* CEPDF */ # define RCWL_CEPDF 0x00000020 /* CEPDF */
# define RCWL_CEPMF 0x0000001F /* CEPMF */ # define RCWL_CEPMF 0x0000001F /* CEPMF */
# define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) # define RCWL_RES ~(RCWL_L BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
u32 rcwh ; /* RCHL Register */ u32 rcwh ; /* RCHL Register */
# define RCWH_PCIHOST 0x80000000 /* PCIHOST */ # define RCWH_PCIHOST 0x80000000 /* PCIHOST */
# define RCWH_PCIHOST_SHIFT 31 # define RCWH_PCIHOST_SHIFT 31
@ -480,9 +526,9 @@ typedef struct reset8349 {
# define RCER_CRE 0x00000001 /* software hard reset */ # define RCER_CRE 0x00000001 /* software hard reset */
# define RCER_RES ~(RCER_CRE) # define RCER_RES ~(RCER_CRE)
u8 res1 [ 0xDC ] ; u8 res1 [ 0xDC ] ;
} reset8349 _t ; } reset83xx _t ;
typedef struct clk8349 { typedef struct clk83xx {
u32 spmr ; /* system PLL mode Register */ u32 spmr ; /* system PLL mode Register */
# define SPMR_LBIUCM 0x80000000 /* LBIUCM */ # define SPMR_LBIUCM 0x80000000 /* LBIUCM */
# define SPMR_DDRCM 0x40000000 /* DDRCM */ # define SPMR_DDRCM 0x40000000 /* DDRCM */
@ -537,16 +583,16 @@ typedef struct clk8349 {
# define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ # define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM ) | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM )
u8 res0 [ 0xF4 ] ; u8 res0 [ 0xF4 ] ;
} clk8349 _t ; } clk83xx _t ;
/*
/*
* Power Management Control Module * Power Management Control Module
*/ */
typedef struct pmc8349 { typedef struct pmc83xx {
u32 pmccr ; /* PMC Configuration Register */ u32 pmccr ; /* PMC Configuration Register */
# define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ # define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */
# define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ # define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */
# define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) # define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
u32 pmcer ; /* PMC Event Register */ u32 pmcer ; /* PMC Event Register */
# define PMCER_PMCI 0x00000001 /* PMC Interrupt */ # define PMCER_PMCI 0x00000001 /* PMC Interrupt */
# define PMCER_RES ~(PMCER_PMCI) # define PMCER_RES ~(PMCER_PMCI)
@ -554,13 +600,12 @@ typedef struct pmc8349 {
# define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ # define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */
# define PMCMR_RES ~(PMCMR_PMCIE) # define PMCMR_RES ~(PMCMR_PMCIE)
u8 res0 [ 0xF4 ] ; u8 res0 [ 0xF4 ] ;
} pmc8349_t ; } pmc83xx_t ;
/*
/*
* general purpose I / O module * general purpose I / O module
*/ */
typedef struct gpio8349 { typedef struct gpio83xx {
u32 dir ; /* direction register */ u32 dir ; /* direction register */
u32 odr ; /* open drain register */ u32 odr ; /* open drain register */
u32 dat ; /* data register */ u32 dat ; /* data register */
@ -568,7 +613,7 @@ typedef struct gpio8349 {
u32 imr ; /* interrupt mask register */ u32 imr ; /* interrupt mask register */
u32 icr ; /* external interrupt control register */ u32 icr ; /* external interrupt control register */
u8 res0 [ 0xE8 ] ; u8 res0 [ 0xE8 ] ;
} gpio8349 _t ; } gpio83xx _t ;
/*
/*
* DDR Memory Controller Memory Map * DDR Memory Controller Memory Map
@ -582,7 +627,7 @@ typedef struct ddr_cs_bnds{
u8 res0 [ 4 ] ; u8 res0 [ 4 ] ;
} ddr_cs_bnds_t ; } ddr_cs_bnds_t ;
typedef struct ddr8349 { typedef struct ddr83xx {
ddr_cs_bnds_t csbnds [ 4 ] ; /**< Chip Select x Memory Bounds */ ddr_cs_bnds_t csbnds [ 4 ] ; /**< Chip Select x Memory Bounds */
u8 res0 [ 0x60 ] ; u8 res0 [ 0x60 ] ;
u32 cs_config [ 4 ] ; /**< Chip Select x Configuration */ u32 cs_config [ 4 ] ; /**< Chip Select x Configuration */
@ -748,7 +793,7 @@ typedef struct ddr8349{
u8 res7 [ 0xA4 ] ; u8 res7 [ 0xA4 ] ;
u32 debug_reg ; u32 debug_reg ;
u8 res8 [ 0xFC ] ; u8 res8 [ 0xFC ] ;
} ddr8349 _t ; } ddr83xx _t ;
/*
/*
* I2C1 Controller * I2C1 Controller
@ -758,7 +803,7 @@ typedef struct ddr8349{
/*
/*
* DUART * DUART
*/ */
typedef struct duart8349 { typedef struct duart83xx {
u8 urbr_ulcr_udlb ; /**< combined register for URBR, UTHR and UDLB */ u8 urbr_ulcr_udlb ; /**< combined register for URBR, UTHR and UDLB */
u8 uier_udmb ; /**< combined register for UIER and UDMB */ u8 uier_udmb ; /**< combined register for UIER and UDMB */
u8 uiir_ufcr_uafr ; /**< combined register for UIIR, UFCR and UAFR */ u8 uiir_ufcr_uafr ; /**< combined register for UIIR, UFCR and UAFR */
@ -771,7 +816,7 @@ typedef struct duart8349{
u8 udsr ; /**< DMA status register */ u8 udsr ; /**< DMA status register */
u8 res1 [ 3 ] ; u8 res1 [ 3 ] ;
u8 res2 [ 0xEC ] ; u8 res2 [ 0xEC ] ;
} duart8349 _t ; } duart83xx _t ;
/*
/*
* Local Bus Controller Registers * Local Bus Controller Registers
@ -781,7 +826,7 @@ typedef struct lbus_bank{
u32 or ; /**< Base Register */ u32 or ; /**< Base Register */
} lbus_bank_t ; } lbus_bank_t ;
typedef struct lbus8349 { typedef struct lbus83xx {
lbus_bank_t bank [ 8 ] ; lbus_bank_t bank [ 8 ] ;
u8 res0 [ 0x28 ] ; u8 res0 [ 0x28 ] ;
u32 mar ; /**< UPM Address Register */ u32 mar ; /**< UPM Address Register */
@ -830,12 +875,12 @@ typedef struct lbus8349 {
u8 res7 [ 0x28 ] ; u8 res7 [ 0x28 ] ;
u8 res8 [ 0xF00 ] ; u8 res8 [ 0xF00 ] ;
} lbus8349 _t ; } lbus83xx _t ;
/*
/*
* Serial Peripheral Interface * Serial Peripheral Interface
*/ */
typedef struct spi8349 typedef struct spi83xx
{ {
u32 mode ; /**< mode register */ u32 mode ; /**< mode register */
u32 event ; /**< event register */ u32 event ; /**< event register */
@ -845,13 +890,13 @@ typedef struct spi8349
u32 tx ; /**< transmit register */ u32 tx ; /**< transmit register */
u32 rx ; /**< receive register */ u32 rx ; /**< receive register */
u8 res1 [ 0xD8 ] ; u8 res1 [ 0xD8 ] ;
} spi8349 _t ; } spi83xx _t ;
/*
/*
* DMA / Messaging Unit * DMA / Messaging Unit
*/ */
typedef struct dma8349 { typedef struct dma83xx {
u32 res0 [ 0xC ] ; /* 0x0-0x29 reseverd */ u32 res0 [ 0xC ] ; /* 0x0-0x29 reseverd */
u32 omisr ; /* 0x30 Outbound message interrupt status register */ u32 omisr ; /* 0x30 Outbound message interrupt status register */
u32 omimr ; /* 0x34 Outbound message interrupt mask register */ u32 omimr ; /* 0x34 Outbound message interrupt mask register */
@ -920,7 +965,7 @@ typedef struct dma8349 {
u32 dmagsr ; /* 0x2A8 DMA general status register */ u32 dmagsr ; /* 0x2A8 DMA general status register */
u32 res20 [ 0x15 ] ; /* 0x2AC-0x2FF reserved */ u32 res20 [ 0x15 ] ; /* 0x2AC-0x2FF reserved */
} dma8349 _t ; } dma83xx _t ;
/* DMAMRn bits */ /* DMAMRn bits */
# define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */ # define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */
@ -939,7 +984,7 @@ typedef struct dma8349 {
/*
/*
* PCI Software Configuration Registers * PCI Software Configuration Registers
*/ */
typedef struct pciconf8349 { typedef struct pciconf83xx {
u32 config_address ; u32 config_address ;
# define PCI_CONFIG_ADDRESS_EN 0x80000000 # define PCI_CONFIG_ADDRESS_EN 0x80000000
# define PCI_CONFIG_ADDRESS_BN_SHIFT 16 # define PCI_CONFIG_ADDRESS_BN_SHIFT 16
@ -953,7 +998,7 @@ typedef struct pciconf8349 {
u32 config_data ; u32 config_data ;
u32 int_ack ; u32 int_ack ;
u8 res [ 116 ] ; u8 res [ 116 ] ;
} pciconf8349 _t ; } pciconf83xx _t ;
/*
/*
* PCI Outbound Translation Register * PCI Outbound Translation Register
@ -965,12 +1010,12 @@ typedef struct pci_outbound_window {
u8 res1 [ 4 ] ; u8 res1 [ 4 ] ;
u32 pocmr ; u32 pocmr ;
u8 res2 [ 4 ] ; u8 res2 [ 4 ] ;
} pot8349 _t ; } pot83xx _t ;
/*
/*
* Sequencer * Sequencer
*/ */
typedef struct ios8349 { typedef struct ios83xx {
pot8349 _t pot [ 6 ] ; pot83xx _t pot [ 6 ] ;
# define POTAR_TA_MASK 0x000fffff # define POTAR_TA_MASK 0x000fffff
# define POBAR_BA_MASK 0x000fffff # define POBAR_BA_MASK 0x000fffff
# define POCMR_EN 0x80000000 # define POCMR_EN 0x80000000
@ -1004,12 +1049,12 @@ typedef struct ios8349 {
u8 res1 [ 4 ] ; u8 res1 [ 4 ] ;
u32 dtcr ; u32 dtcr ;
u8 res2 [ 4 ] ; u8 res2 [ 4 ] ;
} ios8349 _t ; } ios83xx _t ;
/*
/*
* PCI Controller Control and Status Registers * PCI Controller Control and Status Registers
*/ */
typedef struct pcictrl8349 { typedef struct pcictrl83xx {
u32 esr ; u32 esr ;
# define ESR_MERR 0x80000000 # define ESR_MERR 0x80000000
# define ESR_APAR 0x00000400 # define ESR_APAR 0x00000400
@ -1124,63 +1169,63 @@ typedef struct pcictrl8349 {
# define PIWAR_IWS_512M 0x0000001C # define PIWAR_IWS_512M 0x0000001C
# define PIWAR_IWS_1G 0x0000001D # define PIWAR_IWS_1G 0x0000001D
# define PIWAR_IWS_2G 0x0000001E # define PIWAR_IWS_2G 0x0000001E
} pcictrl8349 _t ; } pcictrl83xx _t ;
/*
/*
* USB * USB
*/ */
typedef struct usb8349 { typedef struct usb83xx {
u8 fixme [ 0x2000 ] ; u8 fixme [ 0x2000 ] ;
} usb8349 _t ; } usb83xx _t ;
/*
/*
* TSEC * TSEC
*/ */
typedef struct tsec8349 { typedef struct tsec83xx {
u8 fixme [ 0x1000 ] ; u8 fixme [ 0x1000 ] ;
} tsec8349 _t ; } tsec83xx _t ;
/*
/*
* Security * Security
*/ */
typedef struct security8349 { typedef struct security83xx {
u8 fixme [ 0x10000 ] ; u8 fixme [ 0x10000 ] ;
} security8349 _t ; } security83xx _t ;
typedef struct immap { typedef struct immap {
sysconf8349 _t sysconf ; /* System configuration */ sysconf83xx _t sysconf ; /* System configuration */
wdt8349 _t wdt ; /* Watch Dog Timer (WDT) Registers */ wdt83xx _t wdt ; /* Watch Dog Timer (WDT) Registers */
rtclk8349 _t rtc ; /* Real Time Clock Module Registers */ rtclk83xx _t rtc ; /* Real Time Clock Module Registers */
rtclk8349 _t pit ; /* Periodic Interval Timer */ rtclk83xx _t pit ; /* Periodic Interval Timer */
gtm8349 _t gtm [ 2 ] ; /* Global Timers Module */ gtm83xx _t gtm [ 2 ] ; /* Global Timers Module */
ipic8349 _t ipic ; /* Integrated Programmable Interrupt Controller */ ipic83xx _t ipic ; /* Integrated Programmable Interrupt Controller */
arbiter8349 _t arbiter ; /* System Arbiter Registers */ arbiter83xx _t arbiter ; /* System Arbiter Registers */
reset8349 _t reset ; /* Reset Module */ reset83xx _t reset ; /* Reset Module */
clk8349 _t clk ; /* System Clock Module */ clk83xx _t clk ; /* System Clock Module */
pmc8349 _t pmc ; /* Power Management Control Module */ pmc83xx _t pmc ; /* Power Management Control Module */
gpio8349 _t pgio [ 2 ] ; /* general purpose I/O module */ gpio83xx _t pgio [ 2 ] ; /* general purpose I/O module */
u8 res0 [ 0x200 ] ; u8 res0 [ 0x200 ] ;
u8 DDL_DDR [ 0x100 ] ; u8 DDL_DDR [ 0x100 ] ;
u8 DDL_LBIU [ 0x100 ] ; u8 DDL_LBIU [ 0x100 ] ;
u8 res1 [ 0xE00 ] ; u8 res1 [ 0xE00 ] ;
ddr8349 _t ddr ; /* DDR Memory Controller Memory */ ddr83xx _t ddr ; /* DDR Memory Controller Memory */
i2c_t i2c [ 2 ] ; /* I2C1 Controller */ i2c_t i2c [ 2 ] ; /* I2C1 Controller */
u8 res2 [ 0x1300 ] ; u8 res2 [ 0x1300 ] ;
duart8349 _t duart [ 2 ] ; /* DUART */ duart83xx _t duart [ 2 ] ; /* DUART */
u8 res3 [ 0x900 ] ; u8 res3 [ 0x900 ] ;
lbus8349 _t lbus ; /* Local Bus Controller Registers */ lbus83xx _t lbus ; /* Local Bus Controller Registers */
u8 res4 [ 0x1000 ] ; u8 res4 [ 0x1000 ] ;
spi8349 _t spi ; /* Serial Peripheral Interface */ spi83xx _t spi ; /* Serial Peripheral Interface */
u8 res5 [ 0xF00 ] ; u8 res5 [ 0xF00 ] ;
dma8349 _t dma ; /* DMA */ dma83xx _t dma ; /* DMA */
pciconf8349 _t pci_conf [ 2 ] ; /* PCI Software Configuration Registers */ pciconf83xx _t pci_conf [ 2 ] ; /* PCI Software Configuration Registers */
ios8349 _t ios ; /* Sequencer */ ios83xx _t ios ; /* Sequencer */
pcictrl8349 _t pci_ctrl [ 2 ] ; /* PCI Controller Control and Status Registers */ pcictrl83xx _t pci_ctrl [ 2 ] ; /* PCI Controller Control and Status Registers */
u8 res6 [ 0x19900 ] ; u8 res6 [ 0x19900 ] ;
usb8349 _t usb ; usb83xx _t usb ;
tsec8349 _t tsec [ 2 ] ; tsec83xx _t tsec [ 2 ] ;
u8 res7 [ 0xA000 ] ; u8 res7 [ 0xA000 ] ;
security8349 _t security ; security83xx _t security ;
} immap_t ; } immap_t ;
# endif /* __IMMAP_8349 __ */ # endif /* __IMMAP_83xx __ */
Dave Liu
18 years ago
committed by
Kim Phillips