|
|
|
@ -51,6 +51,48 @@ |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
ranges; |
|
|
|
|
|
|
|
|
|
adc: adc@f8007100 { |
|
|
|
|
compatible = "xlnx,zynq-xadc-1.00.a"; |
|
|
|
|
reg = <0xf8007100 0x20>; |
|
|
|
|
interrupts = <0 7 4>; |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
clocks = <&clkc 12>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
can0: can@e0008000 { |
|
|
|
|
compatible = "xlnx,zynq-can-1.0"; |
|
|
|
|
status = "disabled"; |
|
|
|
|
clocks = <&clkc 19>, <&clkc 36>; |
|
|
|
|
clock-names = "can_clk", "pclk"; |
|
|
|
|
reg = <0xe0008000 0x1000>; |
|
|
|
|
interrupts = <0 28 4>; |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
tx-fifo-depth = <0x40>; |
|
|
|
|
rx-fifo-depth = <0x40>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
can1: can@e0009000 { |
|
|
|
|
compatible = "xlnx,zynq-can-1.0"; |
|
|
|
|
status = "disabled"; |
|
|
|
|
clocks = <&clkc 20>, <&clkc 37>; |
|
|
|
|
clock-names = "can_clk", "pclk"; |
|
|
|
|
reg = <0xe0009000 0x1000>; |
|
|
|
|
interrupts = <0 51 4>; |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
tx-fifo-depth = <0x40>; |
|
|
|
|
rx-fifo-depth = <0x40>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
gpio0: gpio@e000a000 { |
|
|
|
|
compatible = "xlnx,zynq-gpio-1.0"; |
|
|
|
|
#gpio-cells = <2>; |
|
|
|
|
clocks = <&clkc 42>; |
|
|
|
|
gpio-controller; |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
interrupts = <0 20 4>; |
|
|
|
|
reg = <0xe000a000 0x1000>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
i2c0: i2c@e0004000 { |
|
|
|
|
compatible = "cdns,i2c-r1p10"; |
|
|
|
|
status = "disabled"; |
|
|
|
@ -91,6 +133,11 @@ |
|
|
|
|
cache-level = <2>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
mc: memory-controller@f8006000 { |
|
|
|
|
compatible = "xlnx,zynq-ddrc-a05"; |
|
|
|
|
reg = <0xf8006000 0x1000>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
uart0: serial@e0000000 { |
|
|
|
|
compatible = "xlnx,xuartps"; |
|
|
|
|
status = "disabled"; |
|
|
|
@ -199,6 +246,29 @@ |
|
|
|
|
}; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
dmac_s: dmac@f8003000 { |
|
|
|
|
compatible = "arm,pl330", "arm,primecell"; |
|
|
|
|
reg = <0xf8003000 0x1000>; |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", |
|
|
|
|
"dma4", "dma5", "dma6", "dma7"; |
|
|
|
|
interrupts = <0 13 4>, |
|
|
|
|
<0 14 4>, <0 15 4>, |
|
|
|
|
<0 16 4>, <0 17 4>, |
|
|
|
|
<0 40 4>, <0 41 4>, |
|
|
|
|
<0 42 4>, <0 43 4>; |
|
|
|
|
#dma-cells = <1>; |
|
|
|
|
#dma-channels = <8>; |
|
|
|
|
#dma-requests = <4>; |
|
|
|
|
clocks = <&clkc 27>; |
|
|
|
|
clock-names = "apb_pclk"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
devcfg: devcfg@f8007000 { |
|
|
|
|
compatible = "xlnx,zynq-devcfg-1.0"; |
|
|
|
|
reg = <0xf8007000 0x100>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
global_timer: timer@f8f00200 { |
|
|
|
|
compatible = "arm,cortex-a9-global-timer"; |
|
|
|
|
reg = <0xf8f00200 0x20>; |
|
|
|
@ -222,6 +292,7 @@ |
|
|
|
|
clocks = <&clkc 6>; |
|
|
|
|
reg = <0xF8002000 0x1000>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
scutimer: timer@f8f00600 { |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
interrupts = < 1 13 0x301 >; |
|
|
|
@ -229,5 +300,34 @@ |
|
|
|
|
reg = < 0xf8f00600 0x20 >; |
|
|
|
|
clocks = <&clkc 4>; |
|
|
|
|
} ; |
|
|
|
|
|
|
|
|
|
usb0: usb@e0002000 { |
|
|
|
|
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; |
|
|
|
|
status = "disabled"; |
|
|
|
|
clocks = <&clkc 28>; |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
interrupts = <0 21 4>; |
|
|
|
|
reg = <0xe0002000 0x1000>; |
|
|
|
|
phy_type = "ulpi"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
usb1: usb@e0003000 { |
|
|
|
|
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; |
|
|
|
|
status = "disabled"; |
|
|
|
|
clocks = <&clkc 29>; |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
interrupts = <0 44 4>; |
|
|
|
|
reg = <0xe0003000 0x1000>; |
|
|
|
|
phy_type = "ulpi"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
watchdog0: watchdog@f8005000 { |
|
|
|
|
clocks = <&clkc 45>; |
|
|
|
|
compatible = "cdns,wdt-r1p2"; |
|
|
|
|
interrupt-parent = <&intc>; |
|
|
|
|
interrupts = <0 9 1>; |
|
|
|
|
reg = <0xf8005000 0x1000>; |
|
|
|
|
timeout-sec = <10>; |
|
|
|
|
}; |
|
|
|
|
}; |
|
|
|
|
}; |
|
|
|
|