Added CONFIG_NET_MULTI for VOM405 board. Added reset_phy() for VOM405 board. Patch by Matthias Fuchs, 09 Nov 2005master
Stefan Roese
20 years ago
parent
3ada834e30
commit
feaedfcf84
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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# Objects for Xilinx JTAG programming (CPLD)
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CPLD = ../common/xilinx_jtag/lenval.o \
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../common/xilinx_jtag/micro.o \
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../common/xilinx_jtag/ports.o
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OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,262 @@ |
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/*
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* (C) Copyright 2005 |
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#include <command.h> |
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#include <malloc.h> |
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extern void lxt971_no_sleep(void); |
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/* fpga configuration data - not compressed, generated by bin2c */ |
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const unsigned char fpgadata[] = |
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{ |
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#include "fpgadata.c" |
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}; |
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int filesize = sizeof(fpgadata); |
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int board_early_init_f (void) |
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{ |
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive |
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* IRQ 16 405GP internally generated; active low; level sensitive |
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* IRQ 17-24 RESERVED |
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive |
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive |
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive |
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive |
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive |
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
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*/ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr(uicer, 0x00000000); /* disable all ints */ |
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ |
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mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ |
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mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
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*/ |
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mtebc (epcr, 0xa8400000); /* ebc always driven */ |
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/*
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* Reset CPLD via GPIO12 (CS3) pin |
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*/ |
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET); |
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udelay(1000); /* wait 1ms */ |
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET); |
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udelay(1000); /* wait 1ms */ |
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return 0; |
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} |
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/* ------------------------------------------------------------------------- */ |
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int misc_init_f (void) |
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{ |
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return 0; /* dummy implementation */ |
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} |
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int misc_init_r (void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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/* adjust flash start and offset */ |
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
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gd->bd->bi_flashoffset = 0; |
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/*
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* Setup and enable EEPROM write protection |
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*/ |
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); |
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/*
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* Set NAND-FLASH GPIO signals to default |
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*/ |
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); |
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); |
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return (0); |
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} |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard (void) |
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{ |
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unsigned char str[64]; |
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int flashcnt; |
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int delay; |
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volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000); |
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volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001); |
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puts ("Board: "); |
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if (getenv_r("serial#", str, sizeof(str)) == -1) { |
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puts ("### No HW ID - assuming CMS700"); |
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} else { |
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puts(str); |
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} |
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printf(" (PLD-Version=%02d)\n", *ver_reg); |
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/*
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* Flash LEDs |
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*/ |
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for (flashcnt = 0; flashcnt < 3; flashcnt++) { |
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*led_reg = 0x00; /* LEDs off */ |
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for (delay = 0; delay < 100; delay++) |
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udelay(1000); |
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*led_reg = 0x0f; /* LEDs on */ |
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for (delay = 0; delay < 50; delay++) |
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udelay(1000); |
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} |
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*led_reg = 0x70; |
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return 0; |
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} |
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/* ------------------------------------------------------------------------- */ |
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long int initdram (int board_type) |
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{ |
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unsigned long val; |
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mtdcr(memcfga, mem_mb0cf); |
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val = mfdcr(memcfgd); |
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#if 0 |
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printf("\nmb0cf=%x\n", val); /* test-only */ |
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printf("strap=%x\n", mfdcr(strap)); /* test-only */ |
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#endif |
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return (4*1024*1024 << ((val & 0x000e0000) >> 17)); |
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} |
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/* ------------------------------------------------------------------------- */ |
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#if defined(CFG_EEPROM_WREN) |
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state |
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* 0: disable write |
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* 1: enable write |
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* Returns: -1: wrong device address |
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* 0: dis-/en- able done |
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* 0/1: current state if <state> was -1. |
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*/ |
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int eeprom_write_enable (unsigned dev_addr, int state) |
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{ |
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if (CFG_I2C_EEPROM_ADDR != dev_addr) { |
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return -1; |
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} else { |
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switch (state) { |
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case 1: |
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/* Enable write access, clear bit GPIO_SINT2. */ |
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); |
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state = 0; |
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break; |
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case 0: |
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/* Disable write access, set bit GPIO_SINT2. */ |
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); |
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state = 0; |
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break; |
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default: |
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/* Read current status back. */ |
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state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); |
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break; |
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} |
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} |
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return state; |
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} |
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int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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int query = argc == 1; |
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int state = 0; |
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if (query) { |
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/* Query write access state. */ |
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); |
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if (state < 0) { |
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puts ("Query of write access state failed.\n"); |
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} else { |
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printf ("Write access for device 0x%0x is %sabled.\n", |
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CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); |
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state = 0; |
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} |
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} else { |
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if ('0' == argv[1][0]) { |
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/* Disable write access. */ |
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); |
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} else { |
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/* Enable write access. */ |
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); |
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} |
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if (state < 0) { |
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puts ("Setup of write access state failed.\n"); |
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} |
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} |
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return state; |
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} |
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U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, |
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"eepwren - Enable / disable / query EEPROM write access\n", |
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NULL); |
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#endif /* #if defined(CFG_EEPROM_WREN) */ |
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/* ------------------------------------------------------------------------- */ |
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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#include <linux/mtd/nand.h> |
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; |
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void nand_init(void) |
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{ |
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nand_probe(CFG_NAND_BASE); |
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { |
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print_size(nand_dev_desc[0].totlen, "\n"); |
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} |
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} |
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#endif |
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void reset_phy(void) |
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{ |
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#ifdef CONFIG_LXT971_NO_SLEEP |
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/*
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* Disable sleep mode in LXT971 |
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*/ |
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lxt971_no_sleep(); |
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#endif |
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} |
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@ -0,0 +1,28 @@ |
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# esd CMS405 boards
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#
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TEXT_BASE = 0xFFFC0000
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@ -0,0 +1,101 @@ |
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/*
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <ppc4xx.h> |
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#include <asm/processor.h> |
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/*
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* include common flash code (for esd boards) |
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*/ |
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#include "../common/flash.c" |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size_b0; |
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int i; |
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uint pbcr; |
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unsigned long base_b0; |
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int size_val = 0; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0<<20); |
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} |
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/* Setup offsets */ |
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flash_get_offsets (-size_b0, &flash_info[0]); |
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/* Re-do sizing to get full correct info */ |
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mtdcr(ebccfga, pb0cr); |
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pbcr = mfdcr(ebccfgd); |
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mtdcr(ebccfga, pb0cr); |
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base_b0 = -size_b0; |
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switch (size_b0) { |
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case 1 << 20: |
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size_val = 0; |
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break; |
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case 2 << 20: |
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size_val = 1; |
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break; |
||||||
|
case 4 << 20: |
||||||
|
size_val = 2; |
||||||
|
break; |
||||||
|
case 8 << 20: |
||||||
|
size_val = 3; |
||||||
|
break; |
||||||
|
case 16 << 20: |
||||||
|
size_val = 4; |
||||||
|
break; |
||||||
|
} |
||||||
|
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); |
||||||
|
mtdcr(ebccfgd, pbcr); |
||||||
|
|
||||||
|
/* Monitor protection ON by default */ |
||||||
|
(void)flash_protect(FLAG_PROTECT_SET, |
||||||
|
-CFG_MONITOR_LEN, |
||||||
|
0xffffffff, |
||||||
|
&flash_info[0]); |
||||||
|
|
||||||
|
flash_info[0].size = size_b0; |
||||||
|
|
||||||
|
return (size_b0); |
||||||
|
} |
||||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,149 @@ |
|||||||
|
/* |
||||||
|
* (C) Copyright 2000 |
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
OUTPUT_ARCH(powerpc) |
||||||
|
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||||
|
/* Do we need any of these for elf? |
||||||
|
__DYNAMIC = 0; */ |
||||||
|
SECTIONS |
||||||
|
{ |
||||||
|
.resetvec 0xFFFFFFFC : |
||||||
|
{ |
||||||
|
*(.resetvec) |
||||||
|
} = 0xffff |
||||||
|
|
||||||
|
/* Read-only sections, merged into text segment: */ |
||||||
|
. = + SIZEOF_HEADERS; |
||||||
|
.interp : { *(.interp) } |
||||||
|
.hash : { *(.hash) } |
||||||
|
.dynsym : { *(.dynsym) } |
||||||
|
.dynstr : { *(.dynstr) } |
||||||
|
.rel.text : { *(.rel.text) } |
||||||
|
.rela.text : { *(.rela.text) } |
||||||
|
.rel.data : { *(.rel.data) } |
||||||
|
.rela.data : { *(.rela.data) } |
||||||
|
.rel.rodata : { *(.rel.rodata) } |
||||||
|
.rela.rodata : { *(.rela.rodata) } |
||||||
|
.rel.got : { *(.rel.got) } |
||||||
|
.rela.got : { *(.rela.got) } |
||||||
|
.rel.ctors : { *(.rel.ctors) } |
||||||
|
.rela.ctors : { *(.rela.ctors) } |
||||||
|
.rel.dtors : { *(.rel.dtors) } |
||||||
|
.rela.dtors : { *(.rela.dtors) } |
||||||
|
.rel.bss : { *(.rel.bss) } |
||||||
|
.rela.bss : { *(.rela.bss) } |
||||||
|
.rel.plt : { *(.rel.plt) } |
||||||
|
.rela.plt : { *(.rela.plt) } |
||||||
|
.init : { *(.init) } |
||||||
|
.plt : { *(.plt) } |
||||||
|
.text : |
||||||
|
{ |
||||||
|
/* WARNING - the following is hand-optimized to fit within */ |
||||||
|
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||||
|
|
||||||
|
cpu/ppc4xx/start.o (.text) |
||||||
|
cpu/ppc4xx/traps.o (.text) |
||||||
|
cpu/ppc4xx/interrupts.o (.text) |
||||||
|
cpu/ppc4xx/serial.o (.text) |
||||||
|
cpu/ppc4xx/cpu_init.o (.text) |
||||||
|
cpu/ppc4xx/speed.o (.text) |
||||||
|
common/dlmalloc.o (.text) |
||||||
|
lib_generic/crc32.o (.text) |
||||||
|
lib_ppc/extable.o (.text) |
||||||
|
lib_generic/zlib.o (.text) |
||||||
|
|
||||||
|
/* . = env_offset;*/ |
||||||
|
/* common/environment.o(.text)*/ |
||||||
|
|
||||||
|
*(.text) |
||||||
|
*(.fixup) |
||||||
|
*(.got1) |
||||||
|
} |
||||||
|
_etext = .; |
||||||
|
PROVIDE (etext = .); |
||||||
|
.rodata : |
||||||
|
{ |
||||||
|
*(.rodata) |
||||||
|
*(.rodata1) |
||||||
|
*(.rodata.str1.4) |
||||||
|
} |
||||||
|
.fini : { *(.fini) } =0 |
||||||
|
.ctors : { *(.ctors) } |
||||||
|
.dtors : { *(.dtors) } |
||||||
|
|
||||||
|
/* Read-write section, merged into data segment: */ |
||||||
|
. = (. + 0x00FF) & 0xFFFFFF00; |
||||||
|
_erotext = .; |
||||||
|
PROVIDE (erotext = .); |
||||||
|
.reloc : |
||||||
|
{ |
||||||
|
*(.got) |
||||||
|
_GOT2_TABLE_ = .; |
||||||
|
*(.got2) |
||||||
|
_FIXUP_TABLE_ = .; |
||||||
|
*(.fixup) |
||||||
|
} |
||||||
|
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||||
|
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||||
|
|
||||||
|
.data : |
||||||
|
{ |
||||||
|
*(.data) |
||||||
|
*(.data1) |
||||||
|
*(.sdata) |
||||||
|
*(.sdata2) |
||||||
|
*(.dynamic) |
||||||
|
CONSTRUCTORS |
||||||
|
} |
||||||
|
_edata = .; |
||||||
|
PROVIDE (edata = .); |
||||||
|
|
||||||
|
. = .; |
||||||
|
__u_boot_cmd_start = .; |
||||||
|
.u_boot_cmd : { *(.u_boot_cmd) } |
||||||
|
__u_boot_cmd_end = .; |
||||||
|
|
||||||
|
|
||||||
|
. = .; |
||||||
|
__start___ex_table = .; |
||||||
|
__ex_table : { *(__ex_table) } |
||||||
|
__stop___ex_table = .; |
||||||
|
|
||||||
|
. = ALIGN(256); |
||||||
|
__init_begin = .; |
||||||
|
.text.init : { *(.text.init) } |
||||||
|
.data.init : { *(.data.init) } |
||||||
|
. = ALIGN(256); |
||||||
|
__init_end = .; |
||||||
|
|
||||||
|
__bss_start = .; |
||||||
|
.bss : |
||||||
|
{ |
||||||
|
*(.sbss) *(.scommon) |
||||||
|
*(.dynbss) |
||||||
|
*(.bss) |
||||||
|
*(COMMON) |
||||||
|
} |
||||||
|
_end = . ; |
||||||
|
PROVIDE (end = .); |
||||||
|
} |
||||||
@ -0,0 +1,393 @@ |
|||||||
|
/*
|
||||||
|
* (C) Copyright 2005 |
||||||
|
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
/*
|
||||||
|
* CMS700.h - configuration options, board specific |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __CONFIG_H |
||||||
|
#define __CONFIG_H |
||||||
|
|
||||||
|
/*
|
||||||
|
* High Level Configuration Options |
||||||
|
* (easy to change) |
||||||
|
*/ |
||||||
|
|
||||||
|
#define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
||||||
|
#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
||||||
|
#define CONFIG_VOM405 1 /* ...on a VOM405 board */ |
||||||
|
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
||||||
|
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 9600 |
||||||
|
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||||
|
|
||||||
|
#undef CONFIG_BOOTARGS |
||||||
|
#undef CONFIG_BOOTCOMMAND |
||||||
|
|
||||||
|
#define CONFIG_PREBOOT /* enable preboot variable */ |
||||||
|
|
||||||
|
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||||
|
|
||||||
|
#define CONFIG_NET_MULTI 1 |
||||||
|
#undef CONFIG_HAS_ETH1 |
||||||
|
|
||||||
|
#define CONFIG_MII 1 /* MII PHY management */ |
||||||
|
#define CONFIG_PHY_ADDR 0 /* PHY address */ |
||||||
|
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
||||||
|
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
||||||
|
|
||||||
|
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ |
||||||
|
CONFIG_BOOTP_DNS | \
|
||||||
|
CONFIG_BOOTP_DNS2 | \
|
||||||
|
CONFIG_BOOTP_SEND_HOSTNAME ) |
||||||
|
|
||||||
|
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||||
|
CFG_CMD_DHCP | \
|
||||||
|
CFG_CMD_BSP | \
|
||||||
|
CFG_CMD_PCI | \
|
||||||
|
CFG_CMD_IRQ | \
|
||||||
|
CFG_CMD_ELF | \
|
||||||
|
CFG_CMD_NAND | \
|
||||||
|
CFG_CMD_I2C | \
|
||||||
|
CFG_CMD_DATE | \
|
||||||
|
CFG_CMD_MII | \
|
||||||
|
CFG_CMD_PING | \
|
||||||
|
CFG_CMD_EEPROM ) |
||||||
|
|
||||||
|
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||||
|
#include <cmd_confdefs.h> |
||||||
|
|
||||||
|
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||||
|
|
||||||
|
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
||||||
|
|
||||||
|
#undef CONFIG_PRAM /* no "protected RAM" */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options |
||||||
|
*/ |
||||||
|
#define CFG_LONGHELP /* undef to save memory */ |
||||||
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||||
|
|
||||||
|
#undef CFG_HUSH_PARSER /* use "hush" command parser */ |
||||||
|
#ifdef CFG_HUSH_PARSER |
||||||
|
#define CFG_PROMPT_HUSH_PS2 "> " |
||||||
|
#endif |
||||||
|
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||||
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||||
|
#else |
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||||
|
#endif |
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||||
|
#define CFG_MAXARGS 16 /* max number of command args */ |
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||||
|
|
||||||
|
#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ |
||||||
|
|
||||||
|
#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
||||||
|
|
||||||
|
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||||
|
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||||
|
|
||||||
|
#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ |
||||||
|
#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ |
||||||
|
#define CFG_BASE_BAUD 691200 |
||||||
|
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ |
||||||
|
|
||||||
|
/* The following table includes the supported baudrates */ |
||||||
|
#define CFG_BAUDRATE_TABLE \ |
||||||
|
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||||
|
57600, 115200, 230400, 460800, 921600 } |
||||||
|
|
||||||
|
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||||
|
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||||
|
|
||||||
|
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||||
|
|
||||||
|
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||||
|
|
||||||
|
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||||
|
|
||||||
|
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* RTC stuff |
||||||
|
*----------------------------------------------------------------------- |
||||||
|
*/ |
||||||
|
#define CONFIG_RTC_DS1337 |
||||||
|
#define CFG_I2C_RTC_ADDR 0x68 |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* NAND-FLASH stuff |
||||||
|
*----------------------------------------------------------------------- |
||||||
|
*/ |
||||||
|
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
||||||
|
#define SECTORSIZE 512 |
||||||
|
|
||||||
|
#define ADDR_COLUMN 1 |
||||||
|
#define ADDR_PAGE 2 |
||||||
|
#define ADDR_COLUMN_PAGE 3 |
||||||
|
|
||||||
|
#define NAND_ChipID_UNKNOWN 0x00 |
||||||
|
#define NAND_MAX_FLOORS 1 |
||||||
|
#define NAND_MAX_CHIPS 1 |
||||||
|
|
||||||
|
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
||||||
|
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ |
||||||
|
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ |
||||||
|
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ |
||||||
|
|
||||||
|
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) |
||||||
|
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) |
||||||
|
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) |
||||||
|
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) |
||||||
|
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) |
||||||
|
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) |
||||||
|
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) |
||||||
|
|
||||||
|
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) |
||||||
|
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) |
||||||
|
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) |
||||||
|
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) |
||||||
|
|
||||||
|
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* PCI stuff |
||||||
|
*----------------------------------------------------------------------- |
||||||
|
*/ |
||||||
|
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
||||||
|
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||||
|
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||||
|
|
||||||
|
#define CONFIG_PCI /* include pci support */ |
||||||
|
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ |
||||||
|
#undef CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||||
|
/* resource configuration */ |
||||||
|
|
||||||
|
#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
||||||
|
|
||||||
|
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
||||||
|
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ |
||||||
|
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ |
||||||
|
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||||
|
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ |
||||||
|
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||||
|
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ |
||||||
|
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ |
||||||
|
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* For booting Linux, the board info and command line data |
||||||
|
* have to be in the first 8 MB of memory, since this is |
||||||
|
* the maximum mapped by the Linux kernel during initialization. |
||||||
|
*/ |
||||||
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* FLASH organization |
||||||
|
*/ |
||||||
|
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
||||||
|
|
||||||
|
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||||
|
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||||
|
|
||||||
|
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||||
|
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||||
|
|
||||||
|
#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
||||||
|
#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
||||||
|
#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
||||||
|
/*
|
||||||
|
* The following defines are added for buggy IOP480 byte interface. |
||||||
|
* All other boards should use the standard values (CPCI405 etc.) |
||||||
|
*/ |
||||||
|
#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ |
||||||
|
#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ |
||||||
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#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ |
||||||
|
|
||||||
|
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||||
|
|
||||||
|
#if 0 /* test-only */
|
||||||
|
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
||||||
|
#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Start addresses for the final memory configuration |
||||||
|
* (Set up by the startup code) |
||||||
|
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||||
|
*/ |
||||||
|
#define CFG_SDRAM_BASE 0x00000000 |
||||||
|
#define CFG_FLASH_BASE 0xFFFC0000 |
||||||
|
#define CFG_MONITOR_BASE TEXT_BASE |
||||||
|
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
||||||
|
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ |
||||||
|
|
||||||
|
#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) |
||||||
|
# define CFG_RAMBOOT 1 |
||||||
|
#else |
||||||
|
# undef CFG_RAMBOOT |
||||||
|
#endif |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Environment Variable setup |
||||||
|
*/ |
||||||
|
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||||
|
#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
||||||
|
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ |
||||||
|
/* total size of a CAT24WC16 is 2048 bytes */ |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* I2C EEPROM (CAT24WC16) for environment |
||||||
|
*/ |
||||||
|
#define CONFIG_HARD_I2C /* I2c with hardware support */ |
||||||
|
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ |
||||||
|
#define CFG_I2C_SLAVE 0x7F |
||||||
|
|
||||||
|
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
||||||
|
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||||
|
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||||
|
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||||
|
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||||
|
/* 16 byte page write mode using*/ |
||||||
|
/* last 4 bits of the address */ |
||||||
|
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||||
|
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||||
|
|
||||||
|
#define CFG_EEPROM_WREN 1 |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Cache Configuration |
||||||
|
*/ |
||||||
|
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ |
||||||
|
/* have only 8kB, 16kB is save here */ |
||||||
|
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||||
|
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* External Bus Controller (EBC) Setup |
||||||
|
*/ |
||||||
|
#define CFG_PLD_BASE 0xf0000000 |
||||||
|
#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
||||||
|
|
||||||
|
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
||||||
|
#define CFG_EBC_PB0AP 0x92015480 |
||||||
|
#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
||||||
|
|
||||||
|
/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
||||||
|
#define CFG_EBC_PB1AP 0x92015480 |
||||||
|
#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ |
||||||
|
|
||||||
|
/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
||||||
|
#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
||||||
|
#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* FPGA stuff |
||||||
|
*/ |
||||||
|
#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ |
||||||
|
#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ |
||||||
|
|
||||||
|
/* FPGA program pin configuration */ |
||||||
|
#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ |
||||||
|
#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ |
||||||
|
#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ |
||||||
|
#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ |
||||||
|
#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Definitions for initial stack pointer and data area (in data cache) |
||||||
|
*/ |
||||||
|
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
||||||
|
#define CFG_TEMP_STACK_OCM 1 |
||||||
|
|
||||||
|
/* On Chip Memory location */ |
||||||
|
#define CFG_OCM_DATA_ADDR 0xF8000000 |
||||||
|
#define CFG_OCM_DATA_SIZE 0x1000 |
||||||
|
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ |
||||||
|
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ |
||||||
|
|
||||||
|
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||||
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||||
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Definitions for GPIO setup (PPC405EP specific) |
||||||
|
* |
||||||
|
* GPIO0[0] - External Bus Controller BLAST output |
||||||
|
* GPIO0[1-9] - Instruction trace outputs -> GPIO |
||||||
|
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
||||||
|
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO |
||||||
|
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
||||||
|
* GPIO0[24-27] - UART0 control signal inputs/outputs |
||||||
|
* GPIO0[28-29] - UART1 data signal input/output |
||||||
|
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs |
||||||
|
*/ |
||||||
|
/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ |
||||||
|
/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ |
||||||
|
/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ |
||||||
|
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ |
||||||
|
#define CFG_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ |
||||||
|
#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ |
||||||
|
#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ |
||||||
|
#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ |
||||||
|
#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ |
||||||
|
#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ |
||||||
|
#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ |
||||||
|
|
||||||
|
#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ |
||||||
|
#define CFG_PLD_RESET (0x80000000 >> 12) /* GPIO12 */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Internal Definitions |
||||||
|
* |
||||||
|
* Boot Flags |
||||||
|
*/ |
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Default speed selection (cpu_plb_opb_ebc) in mhz. |
||||||
|
* This value will be set if iic boot eprom is disabled. |
||||||
|
*/ |
||||||
|
#if 0 |
||||||
|
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
||||||
|
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 |
||||||
|
#endif |
||||||
|
#if 0 |
||||||
|
#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
||||||
|
#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 |
||||||
|
#endif |
||||||
|
#if 1 |
||||||
|
#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
||||||
|
#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 |
||||||
|
#endif |
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue