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sunxi: clock: Fix OHCI clock gating for H3/H5

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Clock gating bits on H43/H5 were wrong, fix them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
lime2-spi
Chen-Yu Tsai 7 years ago committed by Jagan Teki
parent 5c5fe883e0
commit fef73766d9
1 changed files with 4 additions and 7 deletions
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  1. 11
      arch/arm/include/asm/arch-sunxi/clock_sun6i.h

11
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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@ -350,13 +350,10 @@ struct sunxi_ccm_reg {
#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
#ifdef CONFIG_MACH_SUNXI_H3_H5 #ifdef CONFIG_MACH_SUNXI_H3_H5
/* #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
* These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
* them 0 - 2 like they were called on older SoCs. #define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
*/ #define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
#else #else
#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)

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