u-boot

Author	SHA1	Message	Date
Yuri Tikhonov	928d1d77f8	Fix CPU POST test failure The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered by it. The gcc-4.2 with its more aggressive optimization exposes this fact. This patch just saves the CR value before running the test code, so allowing it to do anything it wants with CR. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Acked-by: Yuri Tikhonov <yur@emcraft.com> --	17 years ago
Stefan Roese	3db93b8bed	ppc4xx: Enable CPU POST test for 4xx with dcache enabled Now with caches enabled (i- and d-cache) on 44x, we need a chance to disable the cache for the CPU POST tests, since these tests consist of self modifying code. This is done via the new change_tlb() function. Signed-off-by: Stefan Roese <sr@denx.de>	17 years ago
Sergei Poselenov	b44896215a	Merged POST framework with the current TOT. Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>	18 years ago
Igor Lisitsin	a11e06965e	Extend POST support for PPC440 Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --	18 years ago
Wolfgang Denk	ad5bb451ad	Restructure POST directory to support of other CPUs, boards, etc.	18 years ago