Instead of hardcoding the mx6 silicon revision, read it in run-time.
Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.
Tested on a mx6qsabrelite, where it shows:
CPU: Freescale i.MX6Q rev1.0 at 792 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
After booting mx6qsabrelite from POR the following is reported:
CPU: Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: unknown reset
This is because both the POR and WDOG bits are set after reset.
Fix this by also checking both bits in the POR case.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
In order to support the coming MX6 platform and to reducde
the duplicated code, we had better move some common files
or functions to the imx-common folder for sharing.
This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature
added but just fix the checkpatch errors in the old file and remove
the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Fix checkpatch warning and errors in several i.MX related files.
While at it also address a checkpatch warning at arch/arm/cpu/armv7/mx5/soc.c
regarding the usage of extern in a C file.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
factor out boot cause function to common code to avoid
the duplicate code in each board support package
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Add initial support for Freescale MX53 processor,
- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro
Signed-off-by: Jason Liu <r64343@freescale.com>
The patch is to support getting FEC MAC address from fuse bank.
Signed-off-by: Jason Liu <r64343@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9
Cortex A8 and A9 both belong to the armv7 architecture, hence the name change.
The two architectures are similar enough that substantial code can be shared.
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Fix MX51 CPU detect message.
Original string was:
CPU: Freescale i.MX51 family 3.0V at 800 MHz
which can be misinterpreted as 3.0 Volts instead of the silicon revision.
,change it to:
CPU: Freescale i.MX51 family rev3.0 at 800 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fix MX51 CPU detect message.
Original string was:
CPU: Freescale i.MX51 family 3.0V at 800 MHz
which can be misinterpreted as 3.0 Volts instead of the silicon revision.
,change it to:
CPU: Freescale i.MX51 family rev3.0 at 800 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The patch removes warnings at compile time and provides
some cleanup code:
- Removed comment on NAND (not yet supported) from lowlevel_init.S
- Removed NFMS bit definition from imx-regs.h
The bit is only related to MX.25/35 and can lead to confusion
- Moved is_soc_rev() to soc specific code (removed from mx51evk.c)
Signed-off-by: Stefano Babic <sbabic@denx.de>
The patch add initial support for the Freescale i.MX51 processor
(family arm cortex_a8).
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
Fabio Estevam
Jason Liu
Fabio Estevam
Liu Hui-R64343
Steve Sakoman
Fabio Estevam
Peter Tyser
Stefano Babic