This patch adds a board command to configure the I2C bootstrap EEPROM
values. Right now 533 and 667MHz are supported for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 533 nor ;to configure the board for 533MHz NOR booting
=> bootstrap 667 nand ;to configure the board for 667MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds NAND booting support for the AMCC Acadia eval board.
Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.
I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
This patch undoes the patch by Jeff Mann with commit-id ada4697d. As
suggested by AMCC it is not recommended to dynamically change the EBC
speed after bootup. So we undo this change to be on the safe side.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch updates the "normal" Bamboo NOR booting port, so
that it is compatible with the coming soon NAND booting
Bamboo port.
It also enables the 2nd NAND flash on the Bamboo.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch updates the Acadia (405EZ) support for the new 1.1 board
revision. It also adds support for NAND FLASH via the 4xx NDFC.
Please note that the jumper J7 must be in position 2-3 for this
NAND support. Position 1-2 is for NAND booting only. NAND booting
support will follow later.
Signed-off-by: Stefan Roese <sr@denx.de>
Because the Sequoia board does not boot with an EBC faster than 66MHz,
the clock divider are changed after the initial boot process.
This allows for maximum clocking speeds to be achieved on newer boards.
Sequoia boards with 666.66 MHz processors require that the EBC divider
be set to 3 in order to start the initial boot process at a slower EBC
speed. After the initial boot process, the divider can be set back to 2,
which will cause the boards to run at 83.333MHz. This is backward
compatible with boards with 533.33 MHz processors, as these boards will
already be set with an EBC divider of 2.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
for the 4k NAND boot image so define bus_frequency to 133MHz here
which is save for the refresh counter setup.
Signed-off-by: Stefan Roese <sr@denx.de>
With this new base address of the Xilinx SystemACE controller
the Linux driver will be easier to adapt, since it can now be
mapped via the "normal" ioremap() call.
Signed-off-by: Stefan Roese <sr@denx.de>
The board specific "bootstrap" command is now fixed and can
be used for the AMCC Katmai board to configure different
CPU/PLB/OPB frequencies.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for the new AMCC Acadia eval board.
Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.
Signed-off-by: Stefan Roese <sr@denx.de>
Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).
Signed-off-by: Stefan Roese <sr@denx.de>
The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.
This patch also enables the cache in FLASH for the startup
phase of U-Boot (while running from FLASH). After relocating to
SDRAM the cache is disabled again. This will speed up the boot
process, especially the SDRAM setup, since there are some loops
for memory testing (auto calibration).
Signed-off-by: Stefan Roese <sr@denx.de>
The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.
Signed-off-by: Stefan Roese <sr@denx.de>
Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).
Signed-off-by: Stefan Roese <sr@denx.de>
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.
For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.
Please note, that still some problems are left with some memory
configurations. See the driver for more details.
Signed-off-by: Stefan Roese <sr@denx.de>
Now the AMCC eval boards Yosemite (440EP) and Yellowstone (440GR)
share one config file and all board specific files. This way we
don't have to maintain two different sets of files for nearly
identical boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Now the board revision and the current PCI bus speed are printed after
the board message.
Also the EBC initialising is now done via defines in the board config
file.
Signed-off-by: Stefan Roese <sr@denx.de>
Now the board revision and the current PCI bus speed are printed after
the board message.
Also the EBC initialising is now done via defines in the board config
file.
Signed-off-by: Stefan Roese <sr@denx.de>
This code will optimize the DDR2 controller setup on a board specific
basis.
Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
Signed-off-by: Stefan Roese <sr@denx.de>
Igor Lisitsin
Stefan Roese
Jeffrey Mann
Wolfgang Denk
John Otken john@softadvances.com
Wolfgang Denk
Marian Balakowicz
Wolfgang Denk