During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.
Avoid updating these register.They will be programmed during NAND RAMBOOT.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.
Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.
Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add NAND support (including spl) on IFC, such as is found on the p1010.
Note that using hardware ECC on IFC with small-page NAND (which is what
comes on the p1010rdb reference board) means there will be insufficient
OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should
work, as it does not use OOB for anything but ECC.
When hardware ECC is not enabled in CSOR, software ECC is now used.
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
[scottwood@freescale.com: ECC rework and misc fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Removed clearing of L2 cache as SRAM as it is not necessary without ECC.
This also speeds up the booting process.
Signed-off-by: Fabian Cenedese <cenedese@indel.ch>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM
and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more
appropriate CONFIG_SYS prefix as well as be consistent with 83xx.
Signed-off-by: Matthew McClintock <msm@freescale.com>
cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
When boot from NAND, the NAND flash must be connected to br/or0.
Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to
it.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
When boot from NAND, the NAND flash must be connected to br/or0.
Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to
it.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Prabhakar Kushwaha
Poonam Aggrwal
Dipen Dudhat
Fabian Cenedese
Matthew McClintock
Becky Bruce
Stefan Roese
Peter Tyser
Mingkai Hu