The DDR mapping function really is just a generic virtual -> physical
mapping function. Generalize it so it can support any virtual starting
offset and IO maps just the same.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)
We don't need to provide Linux copatibility any more.
This commit deletes include/linux/config.h
and fixes source files not to include this.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
e6500 implements MMUv2 and supports power-of-2 page sizes rather than
power-of-4. Add support for such pages.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Instead of just shooting down the entry that covers CCSR, clear out
every TLB entry that isn't the one that we're executing out of.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Some of the MAS register macros do not protect the parameter with
parentheses, which could cause wrong values if the parameter includes
operators.
Also fix the definition of TSIZE_TO_BYTES() so that it actually uses
the parameter. This hasn't caused any problems to date because the
parameter was always been 'tsize'.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is useful when we just want to wipe out the TLBs. There's currently
a function that resets the ddr tlbs to a different value; it is changed to
utilize this function. The new function can be used in conjunction with
setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address
range as needed.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This dumps out the contents of TLB1 on 85xx-based systems.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Extract the operation to read a tlb into a function - we will need
this later to print out the tlbs, and there's no point in duplicating
the code. Create a TSIZE_TO_BYTES macro to deal with the conversion
from the MAS field to an actual size instead of duplicating this in code.
There are a few misc other minor cleanups.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.
Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.
Signed-off-by: Stefan Roese <sr@denx.de>
This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way. If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).
Currently we are limited to power of two sized DDR since we only use a
single bat. If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code. For example the SPD
DDR code today hard codes which TLB entries it uses. We can now make
that pick entries that are free.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_
defines were only enabled for the 83xx platform, but they are also
needed on MPC512x system. Enabling these for E300 systems seems thus
more appropriate.
Signed-off-by: Wolfgang Denk <wd@denx.de>
On 85xx platforms we shouldn't be using any LAWAR_* defines
but using the LAW_* ones provided by fsl-law.h. Rename any such
uses and limit the LAWAR_ to the 83xx platform as the only user so
we will get compile errors in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We can pack the initial tlb_table in MAS register format and use
write_tlb to set things up. This savings can be helpful for NAND
style first stage boot loaders.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Factor out the code we use to actually write a tlb entry.
set_tlb is a logical view of the TLB while write_tlb is a low level
matching the MAS registers.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Allow us to search the TLB array based on an address. This is useful
if we want to change an entry but dont know where it happens to be
located.
For example, the boot page mapping we use on MP or the flash TLB that
we change the WIMGE settings for after we've relocated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_
defines were only enabled for the 83xx platform, but they are also
needed on MPC512x system. Enabling these for E300 systems seems thus
more appropriate.
Signed-off-by: Wolfgang Denk <wd@denx.de>
On 85xx platforms we shouldn't be using any LAWAR_* defines
but using the LAW_* ones provided by fsl-law.h. Rename any such
uses and limit the LAWAR_ to the 83xx platform as the only user so
we will get compile errors in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We can pack the initial tlb_table in MAS register format and use
write_tlb to set things up. This savings can be helpful for NAND
style first stage boot loaders.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Factor out the code we use to actually write a tlb entry.
set_tlb is a logical view of the TLB while write_tlb is a low level
matching the MAS registers.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Allow us to search the TLB array based on an address. This is useful
if we want to change an entry but dont know where it happens to be
located.
For example, the boot page mapping we use on MP or the flash TLB that
we change the WIMGE settings for after we've relocated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The BAT fields are architected; there's no need for these to be in
cpu-specific files. Drop the duplication and move these to
include/asm-ppc/mmu.h. Also, remove the BL_xxx defines that were only
used by the alaska board, and switch to using the BATU_BL_xxx defines
used by all the other boards. The BL_ defines previously in use
had to be shifted into the proper position for use, which was inefficient.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
This function prints the values of all the BAT register
pairs - I needed this for debug earlier this week; adding it to
lib_ppc so others can use it (and add it to reginfo commands
if so desired).
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Currently, this code only deals with BATs 0-3, which makes
it useless on systems that support BATs 4-7. Add the
support for these registers.
Signed-off-by: Becky Bruce <Becky.bruce@freescale.com>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).
Signed-off-by: Stefan Roese <sr@denx.de>
Add a set of functions to manipulate TLB entries:
* set_tlb() - write a tlb entry
* invalidate_tlb() - invalidate a tlb array
* disable_tlb() - disable a variable size tlb entry
* init_tlbs() - setup initial tlbs based on static table
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry. Actually use the bit masks for these items
since they are only a single bit.
Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Grab the FSL Book-E MAS register macros from Linux. Also added
defines for page sizes up to 4TB and removed SHAREN since it doesnt
really exist.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We already had defines for LAWAR_TRGT_IF_* that we should use
rather than creating new ones. Also, added some missing defines for
PCIE targets.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The new function remove_tlb() can be used to remove the TLB's used to
map a specific memory region. This is especially useful for the DDR(2)
setup routines which configure the SDRAM area temporarily as a cached
area (for speedup on auto-calibration and ECC generation) and later
need this area uncached for normal usage.
Signed-off-by: Stefan Roese <sr@denx.de>
The other pagesz constants use one letter to specify order of
magnitude. Also change the one reference to it in mpc8548cds/init.S
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch adds support for the DDR2 controller used on the
440SP and 440SPe. It is tested on the Katmai (440SPe) eval
board and works fine with the following DIMM modules:
- Corsair CM2X512-5400C4 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM)
This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Completion of the 8540ADS/8560ADS updates:
Fix some PCI and Rapid I/O memory maps,
Initialize both TSEC 1 and 2,
Initialize SDRAM
Update MAINTAINER for 85xx boards and README.mpc85xxads
- Added Motorola CPU 8540/8560 support (cpu/85xx)
- Added Motorola MPC8540ADS board support (board/mpc8540ads)
- Added Motorola MPC8560ADS board support (board/mpc8560ads)
* Minor code cleanup
Alexander Graf
Masahiro Yamada
Scott Wood
Timur Tabi
Becky Bruce
Stefan Roese
Peter Tyser
Kumar Gala
Wolfgang Denk
Becky Bruce
Andy Fleming
Zang Roy-r61911
Jon Loeliger
Marian Balakowicz
wdenk