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133 Commits (b62fa913d47e1dab7cbb055dae627c434ea57255)

Author SHA1 Message Date
stroese afcc4a7404 Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.
22 years ago
wdenk ac6dbb85b7 Make compile clean, fix the usual small problems.
22 years ago
stroese 2a46cabd77 esd PCI405 updated.
22 years ago
stroese d69b100e70 esd PCI405 updated.
22 years ago
stroese 6f4474e87b CPCI4052 update (support for revision 3).
22 years ago
stroese ad10dd9aaf Add "pcidelay" environment variable (in ms, enabled via CONFIG_PCI_BOOTDELAY).
22 years ago
wdenk 37bd321e99 Initial revision
22 years ago
wdenk fe8c2806cd Initial revision
22 years ago
wdenk c609719b8d Initial revision
22 years ago
wdenk 458ded34b6 Initial revision
23 years ago
wdenk ab255f26f9 Initial revision
23 years ago
wdenk 153d511e36 Initial revision
23 years ago
wdenk 16f217049a Initial revision
23 years ago
wdenk affae2bff8 Initial revision
23 years ago
wdenk 2f54faae47 Initial revision
23 years ago
wdenk 935ecca1c3 Initial revision
23 years ago
wdenk efee170991 Initial revision
23 years ago
wdenk befe61a190 Initial revision
23 years ago
wdenk 3cae4c9f61 Initial revision
23 years ago
wdenk c7b3f07f4b Initial revision
23 years ago
wdenk 0312e6a7f3 Initial revision
23 years ago
wdenk e85390dc1d Initial revision
23 years ago
wdenk 67fc21f34e Initial revision
23 years ago
wdenk b92ab0d727 Initial revision
23 years ago
wdenk 12e4407c6a Initial revision
23 years ago
wdenk 89ab65e00c Initial revision
24 years ago
wdenk 349e1442f3 Initial revision
24 years ago
wdenk 2dab301caa Initial revision
24 years ago
wdenk a475b5e2a0 Initial revision
24 years ago