2 Commits (ba8c9ea38a5e5f31edc3ef7e3490f0e2143a8360)

Author	SHA1	Message	Date
Prabhakar Kushwaha	6b50f62cc4	board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config ... The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>	11 years ago
Shaohui Xie	83d925668f	powerpc/B4860: enable PBL tool for B4860 ... Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>	11 years ago
Shaohui Xie	c79fd50382	T4240/ramboot: enable PBL tool for T4240 ... Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>	12 years ago