When the timestamp is incremented via interrupt and the interrupt
period is greater than 1 msec, successive calls to get_timer() can
produce inaccurate timing since the interrupts are asynchronous
to the timing loop. For example, with an interrupt period of 10 msec
two successive calls to get_timer() could indicate an elapsed time
of 10 msec after only several hundred usecs -- depending on when
the next interrupt actually occurs. This behavior can cause
reliability issues with components such as CFI and NAND.
This can be remedied by calling reset_timer() prior to establishing
the base timestamp with get_timer(0), provided reset_timer()
resets the hardware timer (rather than simply resetting only the
timestamp). This has the effect of synchronizing the interrupts
(and the advance of the timestamp) with the timing loop.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
This patch adds bootargs passing to nios2 linux.
The args passing is enabled with,
r4 : 'NIOS' magic
r5 : pointer to initrd start
r6 : pointer to initrd end
r7 : pointer to command line
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
CONFIG_SYS_HZ was being calculated (incorrectly) in nios2 configuration
headers. Updated comments to accurately describe timebase macros.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
The outx/writex macros were using writex(addr, val) rather than
the standard writex(val, addr), resulting in incompatibilty with
architecture independent components. This change set uses standard
parameter order.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Copy from linux header. This is needed for generic bitops.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
The standard Altera UART & JTAG UART as well as the OpenCores
YANU driver are now in individual files in drivers/serial
rather than a single file uner cpu/nios2.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
As this seems unclear, document how the flow of setting up
the MAC address is correct.
Signed-off-by: Heiko Schocher <hs@denx.de>
Text changed slightly, adding input from Mike Frysinger.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Only fill the device enetaddr with the contents of the eeprom,
do not program it in MAC address registers
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
The ramdisk sections in doc/uImage.FIT/multi.its lack
load address and entry point properties. Using examples
from this file will result in unbootable image, u-boot
will issue the following error messages:
Can't get ramdisk subimage load address!
Ramdisk image is corrupt or invalid
This patch adds missing properties to ramdisk sections.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way. If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).
Currently we are limited to power of two sized DDR since we only use a
single bat. If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use the same code between primary and secondary cores to init the
L1 cache. We were not enabling cache parity on the secondary cores.
Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks. Than enables the cache and
makes sure its enabled before continuing.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch fixes a problem introduced with patch eb5eb2b0
[ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C
base address to the "i2c" pointer inside of the controller loop.
Otherwise controller 0 is initialized multiple times instead of
initializing each I2C controller sequentially.
Tested on Katmai.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Booting a "Multi-File Image" including a linux kernel, ramdisk and
fdt, generated with
mkimage -A ppc \
-O linux \
-T multi \
-C gzip \
-a 00000000 \
-e 00000000 \
-n "kernel-2.6+initrd+dtb" \
-d "vmlinux.bin.gz:ramdisk_image.gz:board.dtb" \
multi.bin
actually fails, because ramdisk start and end addresses
didn;t get initialized. This patch fixes this issue.
Tested on the KUP4K board.
Signed-off-by: Heiko Schocher <hs@denx.de>
The code to parse alen appeared 6 times in the function.
Factored this out in a small helper function
Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
The ml300 board has a number of issues, but nobody cares about this
long-orphaned board any more. Remove it.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Michal Simek <monstr@monstr.eu>
The restructuring of the mkimage command in commit 89a4d6b1 ("tools:
mkimage: split code into core, default and FIT image specific")
introduced a bug that caused mkimage to segfault when run without
"-n name" option. Initialize the imagename entry to prevent that.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch adds status polling method to offer an alternative to
data toggle method for amd flash chips.
This patch is needed for nios2 cfi flash interface, where the bus
controller performs 4 bytes read cycles for a single byte read
instruction. The data toggle method can not detect chip busy
status correctly. So we have to poll DQ7, which will be inverted
when the chip is busy.
This feature is enabled with the config def,
CONFIG_SYS_CFI_FLASH_STATUS_POLL
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000.
Signed-off-by: Renato Andreola <renato.andreola@imagos.it>
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
The ATMEL flash does not have buffer write feature. Assgined
buffer_size = 1, so that when there is a write to the flash
will not use buffer write function.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
The CF will call cache functions in lib_m68/cache.c and the
cache settings are defined in platform configuration file.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add
CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update
DRAM control and SRAM control register setting. Update cache
setting where size does not write to proper region.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Fix proper portsize: The register for portsize is either 00b, 01b,
or 1xb. The value that previous assigned is 32d.
Fix DRAM bring up: insert asm("nop") for every DRAM register setup
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Fix incorrect default environment for flash erase or protect
range. Change offset from 0 to 0xff80nnnn. Remove default
ethernet setup and MAC address.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Newer ColdFire processors family boot from address 0 instead of
0xFFnn_nnnn. When the boot flash base chip select is set at new
location instead of 0, an un-predictable error will occur if
there is an vector being trigger and refer it to an invalid
address or the vector table handler is not existed at address
0.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Scott McNutt
Thomas Chou
Wolfgang Denk
Heiko Schocher
Felix Radensky
Heiko Schocher
Timur Tabi
Kumar Gala
Stefan Roese
Frans Meulenbroeks
Renato Andreola
TsiChung Liew