This patch removes the architecture specific implementation of
version_string where possible. Some architectures use a special place
and therefore we provide U_BOOT_VERSION_STRING definition and a common
weak symbol version_string.
Signed-off-by: Andreas Biemann <andreas.devel@googlemail.com>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Peter Pan <pppeterpppan@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
-msingle-pic-base is a new gcc option for ppc and
it reduces the size of my u-boot with 6-8 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.
-msingle-pic-base will be in gcc 4.6, however
backported patches are available at
http://bugs.gentoo.org/show_bug.cgi?id=347281
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Currently, _end is used for end of BSS section. We want _end to mean
end of u-boot image, so we rename _end to __bss_end__ first.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Use common ppc4xx linker script for xilinx ppc440 and ppc405 related boards.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
When the cache is enabled in SDRAM we need to flush not only the global
data area but also the bd_info struct in relocate_code. This patch now
flushed the complete dcache (all dcache lines) via flush_dcache() instead
of adding a flush_dcache_range() call for bd_info since this is faster.
Signed-off-by: Stefan Roese <sr@denx.de>
The fixup procedure just stored a constant value in the
fixup table rather than just adjusting the table.
Although that doesn't seem to do any harm, it prevents
relocation more that once.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not
being able to use "sizeof(struct global_data)" in assembler files.
Recent experience has shown that manual synchronization is not
reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into
GENERATED_GBL_DATA_SIZE which gets automatically generated by the
asm-offsets tool. In the result, all definitions of this value can be
deleted from the board config files. We have to make sure that all
files that reference such data include the new <asm-offsets.h> file.
No other changes have been done yet, but it is obvious that similar
changes / simplifications can be done for other, related macro
definitions as well.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be
some end address; to make the meaning more clear we rename it into
CONFIG_SYS_INIT_RAM_SIZE
No other code changes are performed in this patch, only minor editing
of white space (due to the changed length) and the comments was done,
where noticed.
Note that the code for the PATI and cmi_mpc5xx board configurations
looks seriously broken. Last known maintainers on Cc:
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Denis Peter <d.peter@mpl.ch>
Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
The fixup routine must not fixup NULL pointers.
Problem can be seen by
char *testfun(void) __attribute__((weak));
char *(*myfun)(void) = testfun;
Then add
printf("myfun:%p, &myfun:%p\n", myfun, &myfun);
before relocation and after relocation.
myfun should be NULL in both cases but it is not.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
APM821XX is a new line of SoCs which are derivatives of
PPC44X family of processors. This patch adds support of CPU, cache,
tlb, 32k ocm, bootstraps, PLB and AHB bus.
Signed-off-by: Tirumala R Marri <tmarri@apm.com>
Signed-off-by: Stefan Roese <sr@denx.de>
By default the trace broadcast is enabled on 44x systems.
To reduce power consumption when instruction tracing is
not needed, disable trace broadcast.
Check External Debug Mode (EDM) bit to detect if it should be
disabled or not.
Resetting system via a debugger will set the DBCR0[EDM] bit.
Resetting via u-boot or OS will not.
Signed-off-by: Victor Gallardo <vgallardo@apm.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch moves some ppc4xx related headers from the common include
directory (include/) to the powerpc specific one
(arch/powerpc/include/asm/). This way to common include directory is not
so cluttered with files.
Signed-off-by: Stefan Roese <sr@denx.de>
We need to invalidate the data cache after it has been used as init-ram.
This problem was detected on the lwmon5 update.
Signed-off-by: Stefan Roese <sr@denx.de>
Background Info:
Some PPC440/460 boards have caches enabled in the Boot/FLASH TLB (via
init.S) to speed up the boot process. In relocate_code (start.S) the
cache inhibit attribute for this TLB is set to disable cache. This is
needed for the CFI FLASH driver.
This patch now cleans this code up:
- CONFIG_SYS_TLB_FOR_BOOT_FLASH is defined to 0 (default TLB) if not
defined in the top of this file. This way, we can remove an ugly
#ifdef in this code.
- Replace complex "#if defined(CONFIG_440EP) || defined(CONFIG_GR)..."
statement with "#if defined(CONFIG_440)".
- Remove unnecessary cache invalidate calls resulting in faster bootup.
Signed-off-by: Stefan Roese <sr@denx.de>
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
The 440SPe Rev. A is quite old and newer 440SPe boards don't need support
for this CPU revision. Since removing support for this older version
simplifies the creation for newer U-Boot ports, this patch now enables
440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By
defining this in the board config header, Rev. A will still be supported.
Otherwise (default for newer board ports), Rev. A will not be supported.
Signed-off-by: Stefan Roese <sr@denx.de>
r14 is not supposed to be clobbered by functions. Switch
to r12 and call GET_GOT when needed. This will allow u-boot
to loose the -ffixed-r14 gcc option.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Using the GOT in IRQ handlers requires r14 to be -ffixed-r14.
Avoid this by relocatate transfer_to_handler too.
This will allow to free up r14 later on.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
NULL is an absolute value and should not be relocated.
After this correction code like:
void weak_fun(void) __attribute__((weak));
printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
It was brought to our attention that U-Boot contains code derived from the
IBM OpenBIOS source code originally provided with some of the older PowerPC
4xx development boards. As a result, the original license of this code has
been carried in the various files for a number of years in the U-Boot project.
IBM is dual-licensing the IBM code contributions already present in U-Boot
under either the terms of the GNU General Public License version 2, or the
original code license already present.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Patch d873133f [ppc4xx: Add Sequoia RAM-booting target] broke "normal"
booting on some 44x platforms. This breakage is only noticed in some
cases while powercycling. As it seems, the code in question in start.S
didn't invalidate TLB #0. This makes sense since this TLB is used for
the bootrom mapping. With the patch mentioned above even TLB #0 got
invalidated resulting in an error later on.
This patch now fixes this issue by only invalidating TLB #0 in the RAM-
booting case.
Tested succesfully on Sequoia and Canyonlands.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <Eibach@gdsys.de>
This patch makes pll_write on PPC405EP boards
global and callable from C code.
pll_write can be used to dynamically modify the PLB:PCI divider
as it is required for 33/66 MHz pci adapters based on the 405EP.
board_early_init_f() is a good place to do that (check M66EN signal
and call pll_write() when it is required).
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds another build target for the AMCC Sequoia PPC440EPx
eval board. This RAM-booting version is targeted for boards without
NOR FLASH (NAND booting) which need a possibility to initially
program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000)
configured to setup the SDRAM, this debugger can load this RAM-
booting image to the target address in SDRAM (in this case 0x1000000)
and start it there. Then U-Boot's standard NAND commands can be
used to program the NAND FLASH (e.g. "nand write ...").
Here the commands to load and start this image from the BDI2000:
440EPX>reset halt
440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin
440EPX>go 0x1000000
Please note that this image automatically scans for an already
initialized SDRAM TLB (detected by EPN=0). This TLB will not be
cleared. This TLB doesn't need to be TLB #0, this RAM-booting
version will detect it and preserve it. So booting via BDI2000
will work and booting with a complete different TLB init via
U-Boot works as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.
Adjusted internal SRAM initialization to match updated user
manual recommendation.
OCM & ISRAM are now mapped as follows:
physical virtual size
ISRAM 0x4_0000_0000 0xE300_0000 256k
OCM 0x4_0004_0000 0xE304_0000 64k
A single TLB was used for this mapping.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.
Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This is needed on Canyonlands which still has an exception pending
while running relocate_code(). This leads to a failure after trap_init()
is moved to the top of board_init_r().
Signed-off-by: Stefan Roese <sr@denx.de>
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.
Any custom xilinx ppc405 board can be added very easily with no code
duplicity.
This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h
This patch is prepared to work with the latest version of EDK (10.1)
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
Historically the 405 U-Boot port had a dram_init() call in early init
stage. This function was still called from start.S and most of the time
coded in assembler. This is not needed anymore (since a long time) and
boards should implement the common initdram() function in C instead.
This patch now removed the dram_init() call from start.S and removes the
empty implementations that are scattered through most of the 405 board
ports. Some older board ports really implement this dram_init() though.
These are:
csb272
csb472
ERIC
EXBITGEN
W7OLMC
W7OLMG
I changed those boards to call this assembler dram_init() function now
from their board specific initdram() instead. This *should* work, but please
test again on those platforms. And it is perhaps a good idea that those
boards use some common 405 SDRAM initialization code from cpu/ppc4xx at
some time. So further patches welcome here.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch consolidates the 405 and 440 parts of the NAND booting code
selected via CONFIG_NAND_SPL. Now common code is used to initialize the
SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc.
Only *after* running from this location, nand_boot() is called.
Please note that the initsdram() call is now moved from nand_boot.c
to start.S. I experienced problems with some boards like Kilauea
(405EX), which don't have internal SRAM (OCM) and relocation needs to
be done to SDRAM before the NAND controller can get accessed. When
initdram() is called later on in nand_boot(), this can lead to problems
with variables in the bss sections like nand_ecc_pos[].
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
This patch (Part 1 of 2):
* Rolls up a suite of changes to enable correct primordial stack and
global data handling when the data cache is used for such a purpose
for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).
* Related to the first, unifies DDR2 SDRAM and ECC initialization by
eliminating redundant ECC initialization implementations and moving
redundant SDRAM initialization out of board code into shared 4xx
code.
* Enables MCSR visibility on the 405EX(r).
* Enables the use of the data cache for initial RAM on
both AMCC's Kilauea and Makalu and removes a redundant
CFG_POST_MEMORY flag from each board's CONFIG_POST value.
- Removed, per Stefan Roese's request, defunct memory.c file for
Makalu and rolled sdram_init from it into makalu.c.
With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Since the current dflush() implementation is know to have some problems
(as seem on lwmon5 ECC init) this patch removes it completely and replaces
it by using clean_dcache_range().
Tested on Katmai with ECC DIMM.
Signed-off-by: Stefan Roese <sr@denx.de>
460EX doesn't support a fixed bootstrap option to boot from 512 byte page
NAND devices. The only bootstrap option for NAND booting is option F for
2k page devices. So to boot from a 512 bype page device, the I2C bootstrap
EEPROM needs to be programmed accordingly.
This patch adds basic NAND booting support for the AMCC Canyonlands aval
board and also adds support to the "bootstrap" command, to enable NAND
booting I2C setting.
Tested with 512 byte page NAND device (32MByte) on Canyonlands.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for locking the init-ram/stack in d-cache,
so that other regions may use d-cache as well
Note, that this current implementation locks exactly 4k of d-cache,
so please make sure that you don't define a bigger init-ram area. Take
a look at the lwmon5 440EPx implementation as a reference.
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx clear_bss() fails if BSS segment size is not
divisible by 4 without remainder. This patch provides
fix for this problem.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Andreas Bießmann
Wolfgang Denk
Joakim Tjernlund
Po-Yu Chuang
Ricardo Ribalda Delgado
Stefan Roese
Peter Tyser
Tirumala Marri
Victor Gallardo
Josh Boyer
Matthias Fuchs
Dave Mitchell
Ricardo Ribalda Delgado
Jean-Christophe PLAGNIOL-VILLARD
Feng Kan
Grant Erickson
Rafal Jaworowski
Larry Johnson
Anatolij Gustschin