upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Trent Piepho f62fb99941 Fix all linker script to handle all rodata sections ... A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>		16 years ago
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Makefile	FSL DDR: Convert MPC8540ADS to new DDR code.	17 years ago
config.mk	…
ddr.c	fsl-ddr: use the 1T timing as default configuration	16 years ago
law.c	85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boards	16 years ago
mpc8540ads.c	mpc8xxx: LCRR[CLKDIV] is sometimes five bits	16 years ago
tlb.c	85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards	16 years ago
u-boot.lds	Fix all linker script to handle all rodata sections	16 years ago