upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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614 lines
15 KiB
614 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PXA LCD Controller
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*
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* (C) Copyright 2001-2002
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* Wolfgang Denk, DENX Software Engineering -- wd@denx.de
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*/
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/************************************************************************/
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/* ** HEADER FILES */
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/************************************************************************/
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#include <common.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/io.h>
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#include <lcd.h>
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#include <linux/types.h>
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#include <stdarg.h>
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#include <stdio_dev.h>
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/* #define DEBUG */
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#ifdef CONFIG_LCD
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/*----------------------------------------------------------------------*/
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/*
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* Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
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* your display.
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*/
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#ifdef CONFIG_PXA_VGA
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/* LCD outputs connected to a video DAC */
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# define LCD_BPP LCD_COLOR8
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x003008f8
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# define REG_LCCR3 0x0300FF01
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/* 640x480x16 @ 61 Hz */
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vidinfo_t panel_info = {
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.vl_col = 640,
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.vl_row = 480,
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.vl_width = 640,
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.vl_height = 480,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_oep = CONFIG_SYS_HIGH,
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.vl_hsp = CONFIG_SYS_HIGH,
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.vl_vsp = CONFIG_SYS_HIGH,
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.vl_dp = CONFIG_SYS_HIGH,
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.vl_bpix = LCD_BPP,
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.vl_lbw = 0,
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.vl_splt = 0,
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.vl_clor = 0,
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.vl_tft = 1,
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.vl_hpw = 40,
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.vl_blw = 56,
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.vl_elw = 56,
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.vl_vpw = 20,
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.vl_bfw = 8,
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.vl_efw = 8,
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};
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#endif /* CONFIG_PXA_VIDEO */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_SHARP_LM8V31
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# define LCD_BPP LCD_COLOR8
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# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x0030087C
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# define REG_LCCR3 0x0340FF08
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vidinfo_t panel_info = {
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.vl_col = 640,
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.vl_row = 480,
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.vl_width = 157,
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.vl_height = 118,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_oep = CONFIG_SYS_HIGH,
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.vl_hsp = CONFIG_SYS_HIGH,
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.vl_vsp = CONFIG_SYS_HIGH,
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.vl_dp = CONFIG_SYS_HIGH,
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.vl_bpix = LCD_BPP,
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.vl_lbw = 0,
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.vl_splt = 1,
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.vl_clor = 1,
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.vl_tft = 0,
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.vl_hpw = 1,
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.vl_blw = 3,
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.vl_elw = 3,
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.vl_vpw = 1,
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.vl_bfw = 0,
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.vl_efw = 0,
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};
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#endif /* CONFIG_SHARP_LM8V31 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_VOIPAC_LCD
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# define LCD_BPP LCD_COLOR8
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# define LCD_INVERT_COLORS
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x043008f8
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# define REG_LCCR3 0x0340FF08
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vidinfo_t panel_info = {
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.vl_col = 640,
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.vl_row = 480,
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.vl_width = 157,
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.vl_height = 118,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_oep = CONFIG_SYS_HIGH,
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.vl_hsp = CONFIG_SYS_HIGH,
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.vl_vsp = CONFIG_SYS_HIGH,
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.vl_dp = CONFIG_SYS_HIGH,
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.vl_bpix = LCD_BPP,
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.vl_lbw = 0,
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.vl_splt = 1,
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.vl_clor = 1,
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.vl_tft = 1,
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.vl_hpw = 32,
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.vl_blw = 144,
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.vl_elw = 32,
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.vl_vpw = 2,
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.vl_bfw = 13,
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.vl_efw = 30,
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};
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#endif /* CONFIG_VOIPAC_LCD */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_HITACHI_SX14
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/* Hitachi SX14Q004-ZZA color STN LCD */
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#define LCD_BPP LCD_COLOR8
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/* you have to set lccr0 and lccr3 (including pcd) */
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#define REG_LCCR0 0x00301079
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#define REG_LCCR3 0x0340FF20
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vidinfo_t panel_info = {
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.vl_col = 320,
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.vl_row = 240,
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.vl_width = 167,
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.vl_height = 109,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_oep = CONFIG_SYS_HIGH,
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.vl_hsp = CONFIG_SYS_HIGH,
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.vl_vsp = CONFIG_SYS_HIGH,
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.vl_dp = CONFIG_SYS_HIGH,
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.vl_bpix = LCD_BPP,
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.vl_lbw = 1,
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.vl_splt = 0,
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.vl_clor = 1,
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.vl_tft = 0,
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.vl_hpw = 1,
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.vl_blw = 1,
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.vl_elw = 1,
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.vl_vpw = 7,
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.vl_bfw = 0,
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.vl_efw = 0,
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};
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#endif /* CONFIG_HITACHI_SX14 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_LMS283GF05
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# define LCD_BPP LCD_COLOR8
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/*# define LCD_INVERT_COLORS*/
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x043008f8
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# define REG_LCCR3 0x03b00009
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vidinfo_t panel_info = {
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.vl_col = 240,
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.vl_row = 320,
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.vl_rot = 3,
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.vl_width = 240,
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.vl_height = 320,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_oep = CONFIG_SYS_LOW,
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.vl_hsp = CONFIG_SYS_LOW,
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.vl_vsp = CONFIG_SYS_LOW,
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.vl_dp = CONFIG_SYS_HIGH,
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.vl_bpix = LCD_BPP,
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.vl_lbw = 0,
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.vl_splt = 1,
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.vl_clor = 1,
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.vl_tft = 1,
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.vl_hpw = 4,
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.vl_blw = 4,
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.vl_elw = 8,
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.vl_vpw = 4,
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.vl_bfw = 4,
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.vl_efw = 8,
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};
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#endif /* CONFIG_LMS283GF05 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_ACX517AKN
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# define LCD_BPP LCD_COLOR8
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x003008f9
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# define REG_LCCR3 0x03700006
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vidinfo_t panel_info = {
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.vl_col = 320,
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.vl_row = 320,
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.vl_width = 320,
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.vl_height = 320,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_oep = CONFIG_SYS_LOW,
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.vl_hsp = CONFIG_SYS_LOW,
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.vl_vsp = CONFIG_SYS_LOW,
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.vl_dp = CONFIG_SYS_HIGH,
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.vl_bpix = LCD_BPP,
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.vl_lbw = 0,
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.vl_splt = 1,
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.vl_clor = 1,
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.vl_tft = 1,
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.vl_hpw = 0x04,
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.vl_blw = 0x1c,
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.vl_elw = 0x08,
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.vl_vpw = 0x01,
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.vl_bfw = 0x07,
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.vl_efw = 0x08,
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};
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#endif /* CONFIG_ACX517AKN */
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#ifdef CONFIG_ACX544AKN
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# define LCD_BPP LCD_COLOR16
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x003008f9
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# define REG_LCCR3 0x04700007 /* 16bpp */
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vidinfo_t panel_info = {
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.vl_col = 320,
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.vl_row = 320,
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.vl_width = 320,
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.vl_height = 320,
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.vl_clkp = CONFIG_SYS_LOW,
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.vl_oep = CONFIG_SYS_LOW,
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.vl_hsp = CONFIG_SYS_LOW,
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.vl_vsp = CONFIG_SYS_LOW,
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.vl_dp = CONFIG_SYS_LOW,
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.vl_bpix = LCD_BPP,
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.vl_lbw = 0,
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.vl_splt = 0,
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.vl_clor = 1,
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.vl_tft = 1,
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.vl_hpw = 0x05,
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.vl_blw = 0x13,
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.vl_elw = 0x08,
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.vl_vpw = 0x02,
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.vl_bfw = 0x07,
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.vl_efw = 0x05,
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};
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#endif /* CONFIG_ACX544AKN */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_LQ038J7DH53
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# define LCD_BPP LCD_COLOR8
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x003008f9
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# define REG_LCCR3 0x03700004
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vidinfo_t panel_info = {
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.vl_col = 320,
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.vl_row = 480,
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.vl_width = 320,
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.vl_height = 480,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_oep = CONFIG_SYS_LOW,
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.vl_hsp = CONFIG_SYS_LOW,
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.vl_vsp = CONFIG_SYS_LOW,
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.vl_dp = CONFIG_SYS_HIGH,
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.vl_bpix = LCD_BPP,
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.vl_lbw = 0,
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.vl_splt = 1,
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.vl_clor = 1,
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.vl_tft = 1,
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.vl_hpw = 0x04,
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.vl_blw = 0x20,
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.vl_elw = 0x01,
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.vl_vpw = 0x01,
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.vl_bfw = 0x04,
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.vl_efw = 0x01,
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};
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#endif /* CONFIG_ACX517AKN */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_LITTLETON_LCD
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# define LCD_BPP LCD_COLOR8
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x003008f8
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# define REG_LCCR3 0x0300FF04
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vidinfo_t panel_info = {
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.vl_col = 480,
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.vl_row = 640,
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.vl_width = 480,
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.vl_height = 640,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_oep = CONFIG_SYS_HIGH,
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.vl_hsp = CONFIG_SYS_HIGH,
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.vl_vsp = CONFIG_SYS_HIGH,
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.vl_dp = CONFIG_SYS_HIGH,
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.vl_bpix = LCD_BPP,
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.vl_lbw = 0,
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.vl_splt = 0,
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.vl_clor = 0,
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.vl_tft = 1,
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.vl_hpw = 9,
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.vl_blw = 8,
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.vl_elw = 24,
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.vl_vpw = 2,
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.vl_bfw = 2,
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.vl_efw = 4,
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};
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#endif /* CONFIG_LITTLETON_LCD */
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/*----------------------------------------------------------------------*/
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static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
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static void pxafb_setup_gpio (vidinfo_t *vid);
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static void pxafb_enable_controller (vidinfo_t *vid);
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static int pxafb_init (vidinfo_t *vid);
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/************************************************************************/
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/* --------------- PXA chipset specific functions ------------------- */
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/************************************************************************/
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ushort *configuration_get_cmap(void)
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{
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struct pxafb_info *fbi = &panel_info.pxa;
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return (ushort *)fbi->palette;
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}
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void lcd_ctrl_init (void *lcdbase)
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{
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pxafb_init_mem(lcdbase, &panel_info);
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pxafb_init(&panel_info);
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pxafb_setup_gpio(&panel_info);
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pxafb_enable_controller(&panel_info);
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}
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/*----------------------------------------------------------------------*/
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#if LCD_BPP == LCD_COLOR8
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void
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lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
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{
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struct pxafb_info *fbi = &panel_info.pxa;
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unsigned short *palette = (unsigned short *)fbi->palette;
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u_int val;
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if (regno < fbi->palette_size) {
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val = ((red << 8) & 0xf800);
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val |= ((green << 4) & 0x07e0);
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val |= (blue & 0x001f);
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#ifdef LCD_INVERT_COLORS
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palette[regno] = ~val;
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#else
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palette[regno] = val;
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#endif
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}
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debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
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regno, &palette[regno],
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red, green, blue,
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palette[regno]);
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}
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#endif /* LCD_COLOR8 */
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/*----------------------------------------------------------------------*/
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__weak void lcd_enable(void)
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{
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}
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/************************************************************************/
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/* ** PXA255 specific routines */
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/************************************************************************/
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/*
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* Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
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* descriptors and palette areas.
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*/
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ulong calc_fbsize (void)
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{
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ulong size;
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int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
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size = line_length * panel_info.vl_row;
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size += PAGE_SIZE;
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return size;
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}
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static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
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{
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u_long palette_mem_size;
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struct pxafb_info *fbi = &vid->pxa;
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int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
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fbi->screen = (u_long)lcdbase;
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fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
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palette_mem_size = fbi->palette_size * sizeof(u16);
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debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
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/* locate palette and descs at end of page following fb */
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fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
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return 0;
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}
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#ifdef CONFIG_CPU_MONAHANS
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static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
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#else
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static void pxafb_setup_gpio (vidinfo_t *vid)
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{
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u_long lccr0;
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/*
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* setup is based on type of panel supported
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*/
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lccr0 = vid->pxa.reg_lccr0;
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/* 4 bit interface */
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if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
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{
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debug("Setting GPIO for 4 bit data\n");
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/* bits 58-61 */
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writel(readl(GPDR1) | (0xf << 26), GPDR1);
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writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
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GAFR1_U);
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/* bits 74-77 */
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writel(readl(GPDR2) | (0xf << 10), GPDR2);
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writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
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GAFR2_L);
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}
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/* 8 bit interface */
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else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
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(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
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{
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debug("Setting GPIO for 8 bit data\n");
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/* bits 58-65 */
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writel(readl(GPDR1) | (0x3f << 26), GPDR1);
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writel(readl(GPDR2) | (0x3), GPDR2);
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writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
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GAFR1_U);
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writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
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/* bits 74-77 */
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writel(readl(GPDR2) | (0xf << 10), GPDR2);
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writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
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GAFR2_L);
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}
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/* 16 bit interface */
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else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
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{
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debug("Setting GPIO for 16 bit data\n");
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/* bits 58-77 */
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writel(readl(GPDR1) | (0x3f << 26), GPDR1);
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writel(readl(GPDR2) | 0x00003fff, GPDR2);
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writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
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GAFR1_U);
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writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
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}
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else
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{
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printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
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}
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}
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#endif
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static void pxafb_enable_controller (vidinfo_t *vid)
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{
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debug("Enabling LCD controller\n");
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/* Sequence from 11.7.10 */
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writel(vid->pxa.reg_lccr3, LCCR3);
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writel(vid->pxa.reg_lccr2, LCCR2);
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writel(vid->pxa.reg_lccr1, LCCR1);
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writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
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writel(vid->pxa.fdadr0, FDADR0);
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writel(vid->pxa.fdadr1, FDADR1);
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writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
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#ifdef CONFIG_CPU_MONAHANS
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writel(readl(CKENA) | CKENA_1_LCD, CKENA);
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#else
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writel(readl(CKEN) | CKEN16_LCD, CKEN);
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#endif
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debug("FDADR0 = 0x%08x\n", readl(FDADR0));
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debug("FDADR1 = 0x%08x\n", readl(FDADR1));
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debug("LCCR0 = 0x%08x\n", readl(LCCR0));
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debug("LCCR1 = 0x%08x\n", readl(LCCR1));
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debug("LCCR2 = 0x%08x\n", readl(LCCR2));
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debug("LCCR3 = 0x%08x\n", readl(LCCR3));
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}
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static int pxafb_init (vidinfo_t *vid)
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{
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struct pxafb_info *fbi = &vid->pxa;
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debug("Configuring PXA LCD\n");
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fbi->reg_lccr0 = REG_LCCR0;
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fbi->reg_lccr3 = REG_LCCR3;
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debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
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vid->vl_col, vid->vl_hpw,
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vid->vl_blw, vid->vl_elw);
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debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
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vid->vl_row, vid->vl_vpw,
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vid->vl_bfw, vid->vl_efw);
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fbi->reg_lccr1 =
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LCCR1_DisWdth(vid->vl_col) +
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LCCR1_HorSnchWdth(vid->vl_hpw) +
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LCCR1_BegLnDel(vid->vl_blw) +
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LCCR1_EndLnDel(vid->vl_elw);
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fbi->reg_lccr2 =
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LCCR2_DisHght(vid->vl_row) +
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LCCR2_VrtSnchWdth(vid->vl_vpw) +
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LCCR2_BegFrmDel(vid->vl_bfw) +
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LCCR2_EndFrmDel(vid->vl_efw);
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fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
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fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
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| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
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/* setup dma descriptors */
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fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
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fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
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fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
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#define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
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(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
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(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
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/* populate descriptors */
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fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
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fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
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fbi->dmadesc_fblow->fidr = 0;
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fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
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fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
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fbi->dmadesc_fbhigh->fsadr = fbi->screen;
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fbi->dmadesc_fbhigh->fidr = 0;
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fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
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fbi->dmadesc_palette->fsadr = fbi->palette;
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fbi->dmadesc_palette->fidr = 0;
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fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
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if( NBITS(vid->vl_bpix) < 12)
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{
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/* assume any mode with <12 bpp is palette driven */
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fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
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fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
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/* flips back and forth between pal and fbhigh */
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fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
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}
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else
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{
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/* palette shouldn't be loaded in true-color mode */
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fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
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fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
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}
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debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
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debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
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debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
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debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
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debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
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debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
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debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
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debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
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debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
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debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
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debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
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debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
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return 0;
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}
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/************************************************************************/
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/************************************************************************/
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#endif /* CONFIG_LCD */
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