upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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817 lines
21 KiB
817 lines
21 KiB
/*
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* (C) Copyright 2000
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* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
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*
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* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_HARD_I2C)
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#include <asm/cpm_8260.h>
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#include <i2c.h>
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/* define to enable debug messages */
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#undef DEBUG_I2C
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_I2C_MULTI_BUS)
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static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
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#endif /* CONFIG_I2C_MULTI_BUS */
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/* uSec to wait between polls of the i2c */
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#define DELAY_US 100
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/* uSec to wait for the CPM to start processing the buffer */
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#define START_DELAY_US 1000
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/*
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* tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
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* timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
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*/
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#define TOUT_LOOP 5
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/*-----------------------------------------------------------------------
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* Set default values
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*/
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#ifndef CONFIG_SYS_I2C_SPEED
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#define CONFIG_SYS_I2C_SPEED 50000
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#endif
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#ifndef CONFIG_SYS_I2C_SLAVE
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#define CONFIG_SYS_I2C_SLAVE 0xFE
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#endif
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/*-----------------------------------------------------------------------
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*/
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typedef void (*i2c_ecb_t)(int, int, void *); /* error callback function */
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/* This structure keeps track of the bd and buffer space usage. */
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typedef struct i2c_state {
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int rx_idx; /* index to next free Rx BD */
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int tx_idx; /* index to next free Tx BD */
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void *rxbd; /* pointer to next free Rx BD */
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void *txbd; /* pointer to next free Tx BD */
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int tx_space; /* number of Tx bytes left */
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unsigned char *tx_buf; /* pointer to free Tx area */
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i2c_ecb_t err_cb; /* error callback function */
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void *cb_data; /* private data to be passed */
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} i2c_state_t;
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/* flags for i2c_send() and i2c_receive() */
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#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
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#define I2CF_START_COND 0x02 /* tx: generate start condition */
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#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
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/* return codes */
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#define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
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#define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
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#define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
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#define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/receive */
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#define I2CERR_IO_ERROR 5 /* had an error during comms */
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/* error callback flags */
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#define I2CECB_RX_ERR 0x10 /* this is a receive error */
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#define I2CECB_RX_OV 0x02 /* receive overrun error */
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#define I2CECB_RX_MASK 0x0f /* mask for error bits */
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#define I2CECB_TX_ERR 0x20 /* this is a transmit error */
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#define I2CECB_TX_CL 0x01 /* transmit collision error */
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#define I2CECB_TX_UN 0x02 /* transmit underflow error */
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#define I2CECB_TX_NAK 0x04 /* transmit no ack error */
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#define I2CECB_TX_MASK 0x0f /* mask for error bits */
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#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
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#define ERROR_I2C_NONE 0
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#define ERROR_I2C_LENGTH 1
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#define I2C_WRITE_BIT 0x00
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#define I2C_READ_BIT 0x01
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#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
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#define NUM_RX_BDS 4
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#define NUM_TX_BDS 4
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#define MAX_TX_SPACE 256
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typedef struct I2C_BD
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{
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unsigned short status;
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unsigned short length;
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unsigned char *addr;
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} I2C_BD;
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#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
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#define BD_I2C_TX_CL 0x0001 /* collision error */
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#define BD_I2C_TX_UN 0x0002 /* underflow error */
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#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
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#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
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#define BD_I2C_RX_ERR BD_SC_OV
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#ifdef DEBUG_I2C
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#define PRINTD(x) printf x
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#else
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#define PRINTD(x)
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#endif
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/*
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* Returns the best value of I2BRG to meet desired clock speed of I2C with
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* input parameters (clock speed, filter, and predivider value).
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* It returns computer speed value and the difference between it and desired
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* speed.
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*/
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static inline int
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i2c_roundrate(int hz, int speed, int filter, int modval,
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int *brgval, int *totspeed)
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{
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int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
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PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
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hz, speed, filter, modval));
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div = moddiv * speed;
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brgdiv = (hz + div - 1) / div;
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PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
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*brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
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if ((*brgval < 0) || (*brgval > 255)) {
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PRINTD(("\t\trejected brgval=%d\n", *brgval));
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return -1;
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}
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brgdiv = 2 * (*brgval + 3 + (2 * filter));
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div = moddiv * brgdiv ;
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*totspeed = hz / div;
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PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
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return 0;
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}
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/*
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* Sets the I2C clock predivider and divider to meet required clock speed.
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*/
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static int i2c_setrate(int hz, int speed)
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{
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
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volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
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int brgval,
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modval, /* 0-3 */
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bestspeed_diff = speed,
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bestspeed_brgval=0,
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bestspeed_modval=0,
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bestspeed_filter=0,
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totspeed,
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filter = 0; /* Use this fixed value */
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for (modval = 0; modval < 4; modval++)
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{
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if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
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{
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int diff = speed - totspeed ;
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if ((diff >= 0) && (diff < bestspeed_diff))
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{
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bestspeed_diff = diff ;
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bestspeed_modval = modval;
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bestspeed_brgval = brgval;
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bestspeed_filter = filter;
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}
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}
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}
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PRINTD(("[I2C] Best is:\n"));
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PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
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hz, speed,
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bestspeed_filter, bestspeed_modval, bestspeed_brgval,
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bestspeed_diff));
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i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
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i2c->i2c_i2brg = bestspeed_brgval & 0xff;
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PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
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return 1 ;
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}
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void i2c_init(int speed, int slaveadd)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
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volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
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volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
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volatile iic_t *iip;
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ulong rbase, tbase;
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volatile I2C_BD *rxbd, *txbd;
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uint dpaddr;
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/* call board specific i2c bus reset routine before accessing the */
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/* environment, which might be in a chip on that bus. For details */
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/* about this problem see doc/I2C_Edge_Conditions. */
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i2c_init_board();
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#endif
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dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
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if (dpaddr == 0) {
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/* need to allocate dual port ram */
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dpaddr = m8260_cpm_dpalloc(64 +
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(NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
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MAX_TX_SPACE, 64);
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*((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr;
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}
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/*
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* initialise data in dual port ram:
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*
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* dpaddr -> parameter ram (64 bytes)
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* rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
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* tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
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* tx buffer (MAX_TX_SPACE bytes)
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*/
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iip = (iic_t *)&immap->im_dprambase[dpaddr];
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memset((void*)iip, 0, sizeof(iic_t));
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rbase = dpaddr + 64;
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tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
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/* Disable interrupts */
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i2c->i2c_i2mod = 0x00;
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i2c->i2c_i2cmr = 0x00;
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i2c->i2c_i2cer = 0xff;
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i2c->i2c_i2add = slaveadd;
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/*
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* Set the I2C BRG Clock division factor from desired i2c rate
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* and current CPU rate (we assume sccr dfbgr field is 0;
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* divide BRGCLK by 1)
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*/
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PRINTD(("[I2C] Setting rate...\n"));
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i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ;
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/* Set I2C controller in master mode */
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i2c->i2c_i2com = 0x01;
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/* Initialize Tx/Rx parameters */
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iip->iic_rbase = rbase;
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iip->iic_tbase = tbase;
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rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]);
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txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]);
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PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
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PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
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PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
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PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
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/* Set big endian byte order */
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iip->iic_tfcr = 0x10;
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iip->iic_rfcr = 0x10;
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/* Set maximum receive size. */
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iip->iic_mrblr = I2C_RXTX_LEN;
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
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CPM_CR_I2C_SBLOCK,
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0x00,
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CPM_CR_INIT_TRX) | CPM_CR_FLG;
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do {
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__asm__ __volatile__ ("eieio");
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} while (cp->cp_cpcr & CPM_CR_FLG);
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/* Clear events and interrupts */
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i2c->i2c_i2cer = 0xff;
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i2c->i2c_i2cmr = 0x00;
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}
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static
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void i2c_newio(i2c_state_t *state)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
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volatile iic_t *iip;
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uint dpaddr;
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PRINTD(("[I2C] i2c_newio\n"));
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dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
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iip = (iic_t *)&immap->im_dprambase[dpaddr];
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state->rx_idx = 0;
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state->tx_idx = 0;
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state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase];
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state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase];
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state->tx_space = MAX_TX_SPACE;
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state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
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state->err_cb = NULL;
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state->cb_data = NULL;
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PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
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PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
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PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
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/* clear the buffer memory */
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memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
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}
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static
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int i2c_send(i2c_state_t *state,
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unsigned char address,
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unsigned char secondary_address,
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unsigned int flags,
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unsigned short size,
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unsigned char *dataout)
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{
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volatile I2C_BD *txbd;
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int i,j;
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PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
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address, secondary_address, flags, size));
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/* trying to send message larger than BD */
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if (size > I2C_RXTX_LEN)
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return I2CERR_MSG_TOO_LONG;
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/* no more free bds */
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if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
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return I2CERR_NO_BUFFERS;
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txbd = (I2C_BD *)state->txbd;
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txbd->addr = state->tx_buf;
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PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
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if (flags & I2CF_START_COND)
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{
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PRINTD(("[I2C] Formatting addresses...\n"));
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if (flags & I2CF_ENABLE_SECONDARY)
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{
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txbd->length = size + 2; /* Length of message plus dest addresses */
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txbd->addr[0] = address << 1;
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txbd->addr[1] = secondary_address;
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i = 2;
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}
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else
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{
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txbd->length = size + 1; /* Length of message plus dest address */
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txbd->addr[0] = address << 1; /* Write destination address to BD */
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i = 1;
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}
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}
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else
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{
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txbd->length = size; /* Length of message */
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i = 0;
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}
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/* set up txbd */
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txbd->status = BD_SC_READY;
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if (flags & I2CF_START_COND)
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txbd->status |= BD_I2C_TX_START;
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if (flags & I2CF_STOP_COND)
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txbd->status |= BD_SC_LAST | BD_SC_WRAP;
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/* Copy data to send into buffer */
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PRINTD(("[I2C] copy data...\n"));
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for(j = 0; j < size; i++, j++)
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txbd->addr[i] = dataout[j];
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PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
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txbd->length,
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txbd->status,
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txbd->addr[0],
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txbd->addr[1]));
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/* advance state */
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state->tx_buf += txbd->length;
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state->tx_space -= txbd->length;
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state->tx_idx++;
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state->txbd = (void*)(txbd + 1);
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return 0;
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}
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static
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int i2c_receive(i2c_state_t *state,
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unsigned char address,
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unsigned char secondary_address,
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unsigned int flags,
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unsigned short size_to_expect,
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unsigned char *datain)
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{
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volatile I2C_BD *rxbd, *txbd;
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PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
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/* Expected to receive too much */
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if (size_to_expect > I2C_RXTX_LEN)
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return I2CERR_MSG_TOO_LONG;
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/* no more free bds */
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if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
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|| state->tx_space < 2)
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return I2CERR_NO_BUFFERS;
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rxbd = (I2C_BD *)state->rxbd;
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txbd = (I2C_BD *)state->txbd;
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PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
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PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
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txbd->addr = state->tx_buf;
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/* set up TXBD for destination address */
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if (flags & I2CF_ENABLE_SECONDARY)
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{
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txbd->length = 2;
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txbd->addr[0] = address << 1; /* Write data */
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txbd->addr[1] = secondary_address; /* Internal address */
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txbd->status = BD_SC_READY;
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}
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else
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{
|
|
txbd->length = 1 + size_to_expect;
|
|
txbd->addr[0] = (address << 1) | 0x01;
|
|
txbd->status = BD_SC_READY;
|
|
memset(&txbd->addr[1], 0, txbd->length);
|
|
}
|
|
|
|
/* set up rxbd for reception */
|
|
rxbd->status = BD_SC_EMPTY;
|
|
rxbd->length = size_to_expect;
|
|
rxbd->addr = datain;
|
|
|
|
txbd->status |= BD_I2C_TX_START;
|
|
if (flags & I2CF_STOP_COND)
|
|
{
|
|
txbd->status |= BD_SC_LAST | BD_SC_WRAP;
|
|
rxbd->status |= BD_SC_WRAP;
|
|
}
|
|
|
|
PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
|
|
txbd->length,
|
|
txbd->status,
|
|
txbd->addr[0],
|
|
txbd->addr[1]));
|
|
PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
|
|
rxbd->length,
|
|
rxbd->status,
|
|
rxbd->addr[0],
|
|
rxbd->addr[1]));
|
|
|
|
/* advance state */
|
|
state->tx_buf += txbd->length;
|
|
state->tx_space -= txbd->length;
|
|
state->tx_idx++;
|
|
state->txbd = (void*)(txbd + 1);
|
|
state->rx_idx++;
|
|
state->rxbd = (void*)(rxbd + 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static
|
|
int i2c_doio(i2c_state_t *state)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
|
|
volatile iic_t *iip;
|
|
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
|
|
volatile I2C_BD *txbd, *rxbd;
|
|
int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
|
|
uint dpaddr;
|
|
|
|
PRINTD(("[I2C] i2c_doio\n"));
|
|
|
|
if (state->tx_idx <= 0 && state->rx_idx <= 0) {
|
|
PRINTD(("[I2C] No I/O is queued\n"));
|
|
return I2CERR_QUEUE_EMPTY;
|
|
}
|
|
|
|
dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
|
|
iip = (iic_t *)&immap->im_dprambase[dpaddr];
|
|
iip->iic_rbptr = iip->iic_rbase;
|
|
iip->iic_tbptr = iip->iic_tbase;
|
|
|
|
/* Enable I2C */
|
|
PRINTD(("[I2C] Enabling I2C...\n"));
|
|
i2c->i2c_i2mod |= 0x01;
|
|
|
|
/* Begin transmission */
|
|
i2c->i2c_i2com |= 0x80;
|
|
|
|
/* Loop until transmit & receive completed */
|
|
|
|
if ((n = state->tx_idx) > 0) {
|
|
|
|
txbd = ((I2C_BD*)state->txbd) - n;
|
|
for (i = 0; i < n; i++) {
|
|
txtimeo += TOUT_LOOP * txbd->length;
|
|
txbd++;
|
|
}
|
|
|
|
txbd--; /* wait until last in list is done */
|
|
|
|
PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
|
|
|
|
udelay(START_DELAY_US); /* give it time to start */
|
|
while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
|
|
udelay(DELAY_US);
|
|
if (ctrlc())
|
|
return (-1);
|
|
__asm__ __volatile__ ("eieio");
|
|
}
|
|
}
|
|
|
|
if (txcnt < txtimeo && (n = state->rx_idx) > 0) {
|
|
|
|
rxbd = ((I2C_BD*)state->rxbd) - n;
|
|
for (i = 0; i < n; i++) {
|
|
rxtimeo += TOUT_LOOP * rxbd->length;
|
|
rxbd++;
|
|
}
|
|
|
|
rxbd--; /* wait until last in list is done */
|
|
|
|
PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
|
|
|
|
udelay(START_DELAY_US); /* give it time to start */
|
|
while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
|
|
udelay(DELAY_US);
|
|
if (ctrlc())
|
|
return (-1);
|
|
__asm__ __volatile__ ("eieio");
|
|
}
|
|
}
|
|
|
|
/* Turn off I2C */
|
|
i2c->i2c_i2mod &= ~0x01;
|
|
|
|
if ((n = state->tx_idx) > 0) {
|
|
for (i = 0; i < n; i++) {
|
|
txbd = ((I2C_BD*)state->txbd) - (n - i);
|
|
if ((b = txbd->status & BD_I2C_TX_ERR) != 0) {
|
|
if (state->err_cb != NULL)
|
|
(*state->err_cb)(I2CECB_TX_ERR|b, i,
|
|
state->cb_data);
|
|
if (rc == 0)
|
|
rc = I2CERR_IO_ERROR;
|
|
}
|
|
}
|
|
}
|
|
|
|
if ((n = state->rx_idx) > 0) {
|
|
for (i = 0; i < n; i++) {
|
|
rxbd = ((I2C_BD*)state->rxbd) - (n - i);
|
|
if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) {
|
|
if (state->err_cb != NULL)
|
|
(*state->err_cb)(I2CECB_RX_ERR|b, i,
|
|
state->cb_data);
|
|
if (rc == 0)
|
|
rc = I2CERR_IO_ERROR;
|
|
}
|
|
}
|
|
}
|
|
|
|
if ((txtimeo > 0 && txcnt >= txtimeo) || \
|
|
(rxtimeo > 0 && rxcnt >= rxtimeo)) {
|
|
if (state->err_cb != NULL)
|
|
(*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data);
|
|
if (rc == 0)
|
|
rc = I2CERR_TIMEOUT;
|
|
}
|
|
|
|
return (rc);
|
|
}
|
|
|
|
static void
|
|
i2c_probe_callback(int flags, int xnum, void *data)
|
|
{
|
|
/*
|
|
* the only acceptable errors are a transmit NAK or a receive
|
|
* overrun - tx NAK means the device does not exist, rx OV
|
|
* means the device must have responded to the slave address
|
|
* even though the transfer failed
|
|
*/
|
|
if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK))
|
|
*(int *)data |= 1;
|
|
if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV))
|
|
*(int *)data |= 2;
|
|
}
|
|
|
|
int
|
|
i2c_probe(uchar chip)
|
|
{
|
|
i2c_state_t state;
|
|
int rc, err_flag;
|
|
uchar buf[1];
|
|
|
|
i2c_newio(&state);
|
|
|
|
state.err_cb = i2c_probe_callback;
|
|
state.cb_data = (void *) &err_flag;
|
|
err_flag = 0;
|
|
|
|
rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
|
|
|
|
if (rc != 0)
|
|
return (rc); /* probe failed */
|
|
|
|
rc = i2c_doio(&state);
|
|
|
|
if (rc == 0)
|
|
return (0); /* device exists - read succeeded */
|
|
|
|
if (rc == I2CERR_TIMEOUT)
|
|
return (-1); /* device does not exist - timeout */
|
|
|
|
if (rc != I2CERR_IO_ERROR || err_flag == 0)
|
|
return (rc); /* probe failed */
|
|
|
|
if (err_flag & 1)
|
|
return (-1); /* device does not exist - had transmit NAK */
|
|
|
|
return (0); /* device exists - had receive overrun */
|
|
}
|
|
|
|
|
|
int
|
|
i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|
{
|
|
i2c_state_t state;
|
|
uchar xaddr[4];
|
|
int rc;
|
|
|
|
xaddr[0] = (addr >> 24) & 0xFF;
|
|
xaddr[1] = (addr >> 16) & 0xFF;
|
|
xaddr[2] = (addr >> 8) & 0xFF;
|
|
xaddr[3] = addr & 0xFF;
|
|
|
|
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
|
/*
|
|
* EEPROM chips that implement "address overflow" are ones
|
|
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
|
|
* and the extra bits end up in the "chip address" bit slots.
|
|
* This makes a 24WC08 (1Kbyte) chip look like four 256 byte
|
|
* chips.
|
|
*
|
|
* Note that we consider the length of the address field to still
|
|
* be one byte because the extra address bits are hidden in the
|
|
* chip address.
|
|
*/
|
|
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
|
#endif
|
|
|
|
i2c_newio(&state);
|
|
|
|
rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
|
|
if (rc != 0) {
|
|
printf("i2c_read: i2c_send failed (%d)\n", rc);
|
|
return 1;
|
|
}
|
|
|
|
rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
|
|
if (rc != 0) {
|
|
printf("i2c_read: i2c_receive failed (%d)\n", rc);
|
|
return 1;
|
|
}
|
|
|
|
rc = i2c_doio(&state);
|
|
if (rc != 0) {
|
|
printf("i2c_read: i2c_doio failed (%d)\n", rc);
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|
{
|
|
i2c_state_t state;
|
|
uchar xaddr[4];
|
|
int rc;
|
|
|
|
xaddr[0] = (addr >> 24) & 0xFF;
|
|
xaddr[1] = (addr >> 16) & 0xFF;
|
|
xaddr[2] = (addr >> 8) & 0xFF;
|
|
xaddr[3] = addr & 0xFF;
|
|
|
|
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
|
/*
|
|
* EEPROM chips that implement "address overflow" are ones
|
|
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
|
|
* and the extra bits end up in the "chip address" bit slots.
|
|
* This makes a 24WC08 (1Kbyte) chip look like four 256 byte
|
|
* chips.
|
|
*
|
|
* Note that we consider the length of the address field to still
|
|
* be one byte because the extra address bits are hidden in the
|
|
* chip address.
|
|
*/
|
|
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
|
#endif
|
|
|
|
i2c_newio(&state);
|
|
|
|
rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
|
|
if (rc != 0) {
|
|
printf("i2c_write: first i2c_send failed (%d)\n", rc);
|
|
return 1;
|
|
}
|
|
|
|
rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
|
|
if (rc != 0) {
|
|
printf("i2c_write: second i2c_send failed (%d)\n", rc);
|
|
return 1;
|
|
}
|
|
|
|
rc = i2c_doio(&state);
|
|
if (rc != 0) {
|
|
printf("i2c_write: i2c_doio failed (%d)\n", rc);
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uchar
|
|
i2c_reg_read(uchar chip, uchar reg)
|
|
{
|
|
uchar buf;
|
|
|
|
i2c_read(chip, reg, 1, &buf, 1);
|
|
|
|
return (buf);
|
|
}
|
|
|
|
void
|
|
i2c_reg_write(uchar chip, uchar reg, uchar val)
|
|
{
|
|
i2c_write(chip, reg, 1, &val, 1);
|
|
}
|
|
|
|
#if defined(CONFIG_I2C_MULTI_BUS)
|
|
/*
|
|
* Functions for multiple I2C bus handling
|
|
*/
|
|
unsigned int i2c_get_bus_num(void)
|
|
{
|
|
return i2c_bus_num;
|
|
}
|
|
|
|
int i2c_set_bus_num(unsigned int bus)
|
|
{
|
|
#if defined(CONFIG_I2C_MUX)
|
|
if (bus < CONFIG_SYS_MAX_I2C_BUS) {
|
|
i2c_bus_num = bus;
|
|
} else {
|
|
int ret;
|
|
|
|
ret = i2x_mux_select_mux(bus);
|
|
if (ret == 0)
|
|
i2c_bus_num = bus;
|
|
else
|
|
return ret;
|
|
}
|
|
#else
|
|
if (bus >= CONFIG_SYS_MAX_I2C_BUS)
|
|
return -1;
|
|
i2c_bus_num = bus;
|
|
#endif
|
|
return 0;
|
|
}
|
|
/* TODO: add 100/400k switching */
|
|
unsigned int i2c_get_bus_speed(void)
|
|
{
|
|
return CONFIG_SYS_I2C_SPEED;
|
|
}
|
|
|
|
int i2c_set_bus_speed(unsigned int speed)
|
|
{
|
|
if (speed != CONFIG_SYS_I2C_SPEED)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_I2C_MULTI_BUS */
|
|
#endif /* CONFIG_HARD_I2C */
|
|
|