upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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100 lines
3.0 KiB
100 lines
3.0 KiB
/*
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* Configuration settings for the Espresso7420 board.
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* Copyright (C) 2016 Samsung Electronics
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* Thomas Abraham <thomas.ab@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_EXYNOS7420_COMMON_H
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#define __CONFIG_EXYNOS7420_COMMON_H
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/* High Level Configuration Options */
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#define CONFIG_SAMSUNG /* in a SAMSUNG core */
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#define CONFIG_EXYNOS7420 /* Exynos7 Family */
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#define CONFIG_S5P
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <linux/sizes.h>
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#define CONFIG_ARCH_CPU_INIT
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/* Size of malloc() pool before and after relocation */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* select serial console configuration */
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/* Timer input clock frequency */
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#define COUNTER_FREQUENCY 24000000
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/* Device Tree */
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#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
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/* IRAM Layout */
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#define CONFIG_IRAM_BASE 0x02100000
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#define CONFIG_IRAM_SIZE 0x58000
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#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
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#define CPU_RELEASE_ADDR secondary_boot_addr
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/* select serial console configuration */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
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/* Configuration of ENV Blocks */
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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#ifndef MEM_LAYOUT_ENV_SETTINGS
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"kernel_addr_r=0x42000000\0" \
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"fdt_addr_r=0x43000000\0" \
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"ramdisk_addr_r=0x43300000\0" \
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"scriptaddr=0x50000000\0" \
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"pxefile_addr_r=0x51000000\0"
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#endif
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#ifndef EXYNOS_DEVICE_SETTINGS
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#define EXYNOS_DEVICE_SETTINGS \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0"
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#endif
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#ifndef EXYNOS_FDTFILE_SETTING
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#define EXYNOS_FDTFILE_SETTING
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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EXYNOS_DEVICE_SETTINGS \
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EXYNOS_FDTFILE_SETTING \
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MEM_LAYOUT_ENV_SETTINGS
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#endif /* __CONFIG_EXYNOS7420_COMMON_H */
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