upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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73 lines
1.6 KiB
73 lines
1.6 KiB
/*
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* Wait for bit with timeout and ctrlc
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __WAIT_BIT_H
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#define __WAIT_BIT_H
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#include <common.h>
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#include <console.h>
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#include <watchdog.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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/**
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* wait_for_bit() waits for bit set/cleared in register
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*
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* Function polls register waiting for specific bit(s) change
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* (either 0->1 or 1->0). It can fail under two conditions:
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* - Timeout
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* - User interaction (CTRL-C)
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* Function succeeds only if all bits of masked register are set/cleared
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* (depending on set option).
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*
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* @param prefix Prefix added to timeout messagge (message visible only
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* with debug enabled)
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* @param reg Register that will be read (using readl())
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* @param mask Bit(s) of register that must be active
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* @param set Selects wait condition (bit set or clear)
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* @param timeout_ms Timeout (in miliseconds)
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* @param breakable Enables CTRL-C interruption
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* @return 0 on success, -ETIMEDOUT or -EINTR on failure
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*/
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static inline int wait_for_bit(const char *prefix, const u32 *reg,
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const u32 mask, const bool set,
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const unsigned int timeout_ms,
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const bool breakable)
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{
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u32 val;
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unsigned long start = get_timer(0);
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while (1) {
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val = readl(reg);
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if (!set)
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val = ~val;
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if ((val & mask) == mask)
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return 0;
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if (get_timer(start) > timeout_ms)
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break;
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if (breakable && ctrlc()) {
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puts("Abort\n");
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return -EINTR;
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}
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udelay(1);
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WATCHDOG_RESET();
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}
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debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg, mask,
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set);
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return -ETIMEDOUT;
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}
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#endif
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