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@ -92,7 +92,7 @@ static inline void early_mmu_setup(void) |
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static void fix_pcie_mmu_map(void) |
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{ |
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#ifdef CONFIG_LS2080A |
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#ifdef CONFIG_ARCH_LS2080A |
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unsigned int i; |
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u32 svr, ver; |
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
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@ -523,7 +523,7 @@ int timer_init(void) |
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#ifdef CONFIG_FSL_LSCH3 |
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u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; |
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#endif |
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#ifdef CONFIG_LS2080A |
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#ifdef CONFIG_ARCH_LS2080A |
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u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; |
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u32 svr_dev_id; |
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#endif |
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@ -541,7 +541,7 @@ int timer_init(void) |
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out_le32(cltbenr, 0xf); |
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#endif |
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#ifdef CONFIG_LS2080A |
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#ifdef CONFIG_ARCH_LS2080A |
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/*
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* In certain Layerscape SoCs, the clock for each core's |
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* has an enable bit in the PMU Physical Core Time Base Enable |
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