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ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case

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The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).

Signed-off-by: Stefan Roese <sr@denx.de>
master
Stefan Roese 15 years ago
parent 952e7760bf
commit 95b602bab5
26 changed files with 341 additions and 357 deletions
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  1. 24
      board/amcc/ebony/ebony.c
  2. 24
      board/amcc/ocotea/ocotea.c
  3. 32
      board/amcc/yosemite/yosemite.c
  4. 18
      board/cray/L1/L1.c
  5. 8
      board/csb272/csb272.c
  6. 18
      board/csb272/init.S
  7. 8
      board/csb472/csb472.c
  8. 18
      board/csb472/init.S
  9. 14
      board/eric/init.S
  10. 8
      board/exbitgen/exbitgen.c
  11. 14
      board/exbitgen/init.S
  12. 14
      board/g2000/g2000.c
  13. 36
      board/jse/sdram.c
  14. 38
      board/mpl/mip405/mip405.c
  15. 36
      board/mpl/pip405/pip405.c
  16. 40
      board/netstal/common/fixed_sdram.c
  17. 24
      board/sandburst/common/sb_common.c
  18. 22
      board/sc3/sc3.c
  19. 10
      board/w7o/init.S
  20. 8
      board/w7o/w7o.c
  21. 42
      common/cmd_reginfo.c
  22. 26
      cpu/ppc4xx/40x_spd_sdram.c
  23. 44
      cpu/ppc4xx/44x_spd_ddr.c
  24. 60
      cpu/ppc4xx/sdram.c
  25. 86
      include/asm-ppc/ppc4xx-sdram.h
  26. 26
      nand_spl/board/amcc/bamboo/sdram.c

24
board/amcc/ebony/ebony.c
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@ -131,11 +131,11 @@ long int fixed_sdram(void)
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup some default * Setup some default
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup for board-specific specific mem * Setup for board-specific specific mem
@ -143,20 +143,20 @@ long int fixed_sdram(void)
/* /*
* Following for CAS Latency = 2.5 @ 133 MHz PLB * Following for CAS Latency = 2.5 @ 133 MHz PLB
*/ */
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */ /* RA=10 RD=3 */
mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay(400); /* Delay 200 usecs (min) */ udelay(400); /* Delay 200 usecs (min) */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete * Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) { for (;;) {
mfsdram(mem_mcsts, reg); mfsdram(SDRAM0_MCSTS, reg);
if (reg & 0x80000000) if (reg & 0x80000000)
break; break;
} }

24
board/amcc/ocotea/ocotea.c
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@ -241,11 +241,11 @@ long int fixed_sdram (void)
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup some default * Setup some default
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup for board-specific specific mem * Setup for board-specific specific mem
@ -253,20 +253,20 @@ long int fixed_sdram (void)
/* /*
* Following for CAS Latency = 2.5 @ 133 MHz PLB * Following for CAS Latency = 2.5 @ 133 MHz PLB
*/ */
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */ /* RA=10 RD=3 */
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */ udelay (400); /* Delay 200 usecs (min) */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete * Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) { for (;;) {
mfsdram (mem_mcsts, reg); mfsdram (SDRAM0_MCSTS, reg);
if (reg & 0x80000000) if (reg & 0x80000000)
break; break;
} }

32
board/amcc/yosemite/yosemite.c
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@ -237,7 +237,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
/* go through all possible SDRAM0_TR1[RDCT] values */ /* go through all possible SDRAM0_TR1[RDCT] values */
for (i=0; i<=0x1ff; i++) { for (i=0; i<=0x1ff; i++) {
/* set the current value for TR1 */ /* set the current value for TR1 */
mtsdram(mem_tr1, (0x80800800 | i)); mtsdram(SDRAM0_TR1, (0x80800800 | i));
/* write values */ /* write values */
for (j=0; j<NUM_TRIES; j++) { for (j=0; j<NUM_TRIES; j++) {
@ -289,15 +289,15 @@ phys_size_t initdram(int board)
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup some default * Setup some default
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_clktr, 0x40000000); /* ?? */ mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
mtsdram(mem_wddctr, 0x40000000); /* ?? */ mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger /*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */ then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */ mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup for board-specific specific mem * Setup for board-specific specific mem
@ -305,29 +305,29 @@ phys_size_t initdram(int board)
/* /*
* Following for CAS Latency = 2.5 @ 133 MHz PLB * Following for CAS Latency = 2.5 @ 133 MHz PLB
*/ */
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */ mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* ?? */ mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */ mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */ mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */ udelay(400); /* Delay 200 usecs (min) */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete * Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x80000000); /* Enable */ mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
for (;;) { for (;;) {
mfsdram(mem_mcsts, reg); mfsdram(SDRAM0_MCSTS, reg);
if (reg & 0x80000000) if (reg & 0x80000000)
break; break;
} }
sdram_tr1_set(0x00000000, &tr1_bank1); sdram_tr1_set(0x00000000, &tr1_bank1);
sdram_tr1_set(0x08000000, &tr1_bank2); sdram_tr1_set(0x08000000, &tr1_bank2);
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800)); mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */ return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
} }

18
board/cray/L1/L1.c
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@ -198,7 +198,7 @@ static void init_sdram (void)
unsigned long tmp; unsigned long tmp;
/* write SDRAM bank 0 register */ /* write SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, 0x00062001); mtdcr (SDRAM0_CFGDATA, 0x00062001);
/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
@ -212,25 +212,25 @@ static void init_sdram (void)
/* divisor = ((mfdcr(strap)>> 28) & 0x3); */ /* divisor = ((mfdcr(strap)>> 28) & 0x3); */
/* write SDRAM timing for 100MHz. */ /* write SDRAM timing for 100MHz. */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1); mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, 0x0086400D); mtdcr (SDRAM0_CFGDATA, 0x0086400D);
/* write SDRAM refresh interval register */ /* write SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr); mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, 0x05F00000); mtdcr (SDRAM0_CFGDATA, 0x05F00000);
udelay (200); udelay (200);
/* sdram controller.*/ /* sdram controller.*/
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x90800000); mtdcr (SDRAM0_CFGDATA, 0x90800000);
udelay (200); udelay (200);
/* initially, disable ECC on all banks */ /* initially, disable ECC on all banks */
udelay (200); udelay (200);
mtdcr (SDRAM0_CFGADDR, mem_ecccf); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff; tmp &= 0xff0fffff;
mtdcr (SDRAM0_CFGADDR, mem_ecccf); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
return; return;
@ -282,15 +282,15 @@ int testdram (void)
} }
printf ("Enable ECC.."); printf ("Enable ECC..");
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600); udelay (600);
for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
; ;
udelay (400); udelay (400);
mtdcr (SDRAM0_CFGADDR, mem_ecccf); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000; tmp |= 0x00800000;
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);

8
board/csb272/csb272.c
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@ -135,28 +135,28 @@ phys_size_t initdram (int board_type)
tot_size = 0; tot_size = 0;
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size; tot_size += bank_size;
} }
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size; tot_size += bank_size;
} }
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size; tot_size += bank_size;
} }
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);

18
board/csb272/init.S
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@ -175,26 +175,26 @@ sdram_init:
* Disable memory controller to allow * Disable memory controller to allow
* values to be changed. * values to be changed.
*/ */
WDCR_SDRAM(mem_mcopt1, 0x00000000) WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
/* /*
* Configure Memory Banks * Configure Memory Banks
*/ */
WDCR_SDRAM(mem_mb0cf, 0x00084001) WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
WDCR_SDRAM(mem_mb1cf, 0x00000000) WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
WDCR_SDRAM(mem_mb2cf, 0x00000000) WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
WDCR_SDRAM(mem_mb3cf, 0x00000000) WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
/* /*
* Set up SDTR1 (SDRAM Timing Register) * Set up SDTR1 (SDRAM Timing Register)
*/ */
WDCR_SDRAM(mem_sdtr1, 0x00854009) WDCR_SDRAM(SDRAM0_TR, 0x00854009)
/* /*
* Set RTR (Refresh Timing Register) * Set RTR (Refresh Timing Register)
*/ */
WDCR_SDRAM(mem_rtr, 0x10000000) WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
/* WDCR_SDRAM(mem_rtr, 0x05f00000) */ /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
/******************************************************************** /********************************************************************
* Delay to ensure 200usec have elapsed since reset. Assume worst * Delay to ensure 200usec have elapsed since reset. Assume worst
@ -210,7 +210,7 @@ sdram_init:
/******************************************************************** /********************************************************************
* Set memory controller options reg, MCOPT1. * Set memory controller options reg, MCOPT1.
*******************************************************************/ *******************************************************************/
WDCR_SDRAM(mem_mcopt1,0x80800000) WDCR_SDRAM(SDRAM0_CFG,0x80800000)
..sdri_done: ..sdri_done:
blr /* Return to calling function */ blr /* Return to calling function */

8
board/csb472/csb472.c
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@ -103,28 +103,28 @@ phys_size_t initdram (int board_type)
tot_size = 0; tot_size = 0;
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size; tot_size += bank_size;
} }
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size; tot_size += bank_size;
} }
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size; tot_size += bank_size;
} }
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);

18
board/csb472/init.S
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@ -171,26 +171,26 @@ sdram_init:
* Disable memory controller to allow * Disable memory controller to allow
* values to be changed. * values to be changed.
*/ */
WDCR_SDRAM(mem_mcopt1, 0x00000000) WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
/* /*
* Configure Memory Banks * Configure Memory Banks
*/ */
WDCR_SDRAM(mem_mb0cf, 0x00062001) WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
WDCR_SDRAM(mem_mb1cf, 0x00000000) WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
WDCR_SDRAM(mem_mb2cf, 0x00000000) WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
WDCR_SDRAM(mem_mb3cf, 0x00000000) WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
/* /*
* Set up SDTR1 (SDRAM Timing Register) * Set up SDTR1 (SDRAM Timing Register)
*/ */
WDCR_SDRAM(mem_sdtr1, 0x00854009) WDCR_SDRAM(SDRAM0_TR, 0x00854009)
/* /*
* Set RTR (Refresh Timing Register) * Set RTR (Refresh Timing Register)
*/ */
WDCR_SDRAM(mem_rtr, 0x10000000) WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
/* WDCR_SDRAM(mem_rtr, 0x05f00000) */ /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
/******************************************************************** /********************************************************************
* Delay to ensure 200usec have elapsed since reset. Assume worst * Delay to ensure 200usec have elapsed since reset. Assume worst
@ -206,7 +206,7 @@ sdram_init:
/******************************************************************** /********************************************************************
* Set memory controller options reg, MCOPT1. * Set memory controller options reg, MCOPT1.
*******************************************************************/ *******************************************************************/
WDCR_SDRAM(mem_mcopt1,0x80800000) WDCR_SDRAM(SDRAM0_CFG,0x80800000)
..sdri_done: ..sdri_done:
blr /* Return to calling function */ blr /* Return to calling function */

14
board/eric/init.S
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@ -228,7 +228,7 @@ sdram_init:
/* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */ /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
/*------------------------------------------------------------------- */ /*------------------------------------------------------------------- */
addi r4,0,mem_mb0cf addi r4,0,SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB0CF@h addis r4,0,MB0CF@h
ori r4,r4,MB0CF@l ori r4,r4,MB0CF@l
@ -238,7 +238,7 @@ sdram_init:
/* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */ /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
/*------------------------------------------------------------------- */ /*------------------------------------------------------------------- */
addi r4,0,mem_mb1cf addi r4,0,SDRAM0_B1CR
mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB1CF@h addis r4,0,MB1CF@h
ori r4,r4,MB1CF@l ori r4,r4,MB1CF@l
@ -248,7 +248,7 @@ sdram_init:
/* Set MB2CF for bank 2. off */ /* Set MB2CF for bank 2. off */
/*------------------------------------------------------------------- */ /*------------------------------------------------------------------- */
addi r4,0,mem_mb2cf addi r4,0,SDRAM0_B2CR
mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB2CF@h addis r4,0,MB2CF@h
ori r4,r4,MB2CF@l ori r4,r4,MB2CF@l
@ -258,7 +258,7 @@ sdram_init:
/* Set MB3CF for bank 3. off */ /* Set MB3CF for bank 3. off */
/*------------------------------------------------------------------- */ /*------------------------------------------------------------------- */
addi r4,0,mem_mb3cf addi r4,0,SDRAM0_B3CR
mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB3CF@h addis r4,0,MB3CF@h
ori r4,r4,MB3CF@l ori r4,r4,MB3CF@l
@ -305,14 +305,14 @@ sdram_init:
/*------------------------------------------------------------------- */ /*------------------------------------------------------------------- */
/* Set SDTR1 */ /* Set SDTR1 */
/*------------------------------------------------------------------- */ /*------------------------------------------------------------------- */
addi r4,0,mem_sdtr1 addi r4,0,SDRAM0_TR
mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r6 mtdcr SDRAM0_CFGDATA,r6
/*------------------------------------------------------------------- */ /*------------------------------------------------------------------- */
/* Set RTR */ /* Set RTR */
/*------------------------------------------------------------------- */ /*------------------------------------------------------------------- */
addi r4,0,mem_rtr addi r4,0,SDRAM0_RTR
mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r7 mtdcr SDRAM0_CFGDATA,r7
@ -332,7 +332,7 @@ sdram_init:
/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
/* read/prefetch. */ /* read/prefetch. */
/*------------------------------------------------------------------- */ /*------------------------------------------------------------------- */
addi r4,0,mem_mcopt1 addi r4,0,SDRAM0_CFG
mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x8080 /* set DC_EN=1 */ addis r4,0,0x8080 /* set DC_EN=1 */
ori r4,r4,0x0000 ori r4,r4,0x0000

8
board/exbitgen/exbitgen.c
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@ -94,28 +94,28 @@ phys_size_t initdram (int board_type)
tot_size = 0; tot_size = 0;
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size; tot_size += bank_size;
} }
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size; tot_size += bank_size;
} }
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size; tot_size += bank_size;
} }
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) { if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7); bank_size = 0x00400000 << ((tmp >> 17) & 0x7);

14
board/exbitgen/init.S
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@ -382,7 +382,7 @@ sdram_init:
/*----------------------------------------------------------- */ /*----------------------------------------------------------- */
/* Set SDTR1 */ /* Set SDTR1 */
/*----------------------------------------------------------- */ /*----------------------------------------------------------- */
addi r5,0,mem_sdtr1 addi r5,0,SDRAM0_TR
mtdcr SDRAM0_CFGADDR,r5 mtdcr SDRAM0_CFGADDR,r5
mtdcr SDRAM0_CFGDATA,r4 mtdcr SDRAM0_CFGDATA,r4
@ -413,7 +413,7 @@ sdram_init:
/* Set SDRAM bank 0 register and adjust r6 for next bank */ /* Set SDRAM bank 0 register and adjust r6 for next bank */
/*------------------------------------------------------ */ /*------------------------------------------------------ */
addi r7,0,mem_mb0cf addi r7,0,SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6 mtdcr SDRAM0_CFGDATA,r6
@ -424,7 +424,7 @@ sdram_init:
cmpi 0, r12, 2 cmpi 0, r12, 2
bne b1skip bne b1skip
addi r7,0,mem_mb1cf addi r7,0,SDRAM0_B1CR
mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6 mtdcr SDRAM0_CFGDATA,r6
@ -432,7 +432,7 @@ sdram_init:
/* Set SDRAM bank 2 register and adjust r6 for next bank */ /* Set SDRAM bank 2 register and adjust r6 for next bank */
/*------------------------------------------------------ */ /*------------------------------------------------------ */
b1skip: addi r7,0,mem_mb2cf b1skip: addi r7,0,SDRAM0_B2CR
mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6 mtdcr SDRAM0_CFGDATA,r6
@ -443,7 +443,7 @@ b1skip: addi r7,0,mem_mb2cf
cmpi 0, r12, 2 cmpi 0, r12, 2
bne b3skip bne b3skip
addi r7,0,mem_mb3cf addi r7,0,SDRAM0_B3CR
mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6 mtdcr SDRAM0_CFGDATA,r6
b3skip: b3skip:
@ -456,7 +456,7 @@ b3skip:
addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ addis r7, 0, 0x05F0 /* RTR value for 100Mhz */
bl rtr_2 bl rtr_2
rtr_1: addis r7, 0, 0x03F8 rtr_1: addis r7, 0, 0x03F8
rtr_2: addi r4,0,mem_rtr rtr_2: addi r4,0,SDRAM0_RTR
mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r7 mtdcr SDRAM0_CFGDATA,r7
@ -476,7 +476,7 @@ rtr_2: addi r4,0,mem_rtr
/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
/* read/prefetch. */ /* read/prefetch. */
/*----------------------------------------------------------- */ /*----------------------------------------------------------- */
addi r4,0,mem_mcopt1 addi r4,0,SDRAM0_CFG
mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x80C0 /* set DC_EN=1 */ addis r4,0,0x80C0 /* set DC_EN=1 */
ori r4,r4,0x0000 ori r4,r4,0x0000

14
board/g2000/g2000.c
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@ -116,16 +116,16 @@ long int init_sdram_static_settings(void)
{ {
#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) #define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */ /* disable memcontroller so updates work */
mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL ); mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL );
mtsdram0( mem_rtr , MEM_RTR_INIT_VAL ); mtsdram0( SDRAM0_RTR , MEM_RTR_INIT_VAL );
mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL ); mtsdram0( SDRAM0_PMIT , MEM_PMIT_INIT_VAL );
mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL ); mtsdram0( SDRAM0_B0CR , MEM_MB0CF_INIT_VAL );
mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL ); mtsdram0( SDRAM0_B1CR , MEM_MB1CF_INIT_VAL );
mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL ); mtsdram0( SDRAM0_TR , MEM_SDTR1_INIT_VAL );
/* SDRAM have a power on delay, 500 micro should do */ /* SDRAM have a power on delay, 500 micro should do */
udelay(500); udelay(500);
mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
} }

36
board/jse/sdram.c
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@ -35,59 +35,59 @@ phys_size_t initdram (int board_type)
/* Configure the SDRAMS */ /* Configure the SDRAMS */
/* disable memory controller */ /* disable memory controller */
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x00000000); mtdcr (SDRAM0_CFGDATA, 0x00000000);
udelay (500); udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
mtdcr (SDRAM0_CFGADDR, mem_besra); mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
mtdcr (SDRAM0_CFGDATA, 0xffffffff); mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
mtdcr (SDRAM0_CFGADDR, mem_besrb); mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
mtdcr (SDRAM0_CFGDATA, 0xffffffff); mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */ /* Clear SDRAM0_ECCCFG (disable ECC) */
mtdcr (SDRAM0_CFGADDR, mem_ecccf); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
mtdcr (SDRAM0_CFGDATA, 0x00000000); mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
mtdcr (SDRAM0_CFGADDR, mem_eccerr); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
mtdcr (SDRAM0_CFGDATA, 0xffffffff); mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1); mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, 0x010a4016); mtdcr (SDRAM0_CFGDATA, 0x010a4016);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, 0x00084001); mtdcr (SDRAM0_CFGDATA, 0x00084001);
/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
mtdcr (SDRAM0_CFGDATA, 0x04084001); mtdcr (SDRAM0_CFGDATA, 0x04084001);
/* Memory Bank 2 Config == BE=0 */ /* Memory Bank 2 Config == BE=0 */
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
mtdcr (SDRAM0_CFGDATA, 0x00000000); mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Memory Bank 3 Config == BE=0 */ /* Memory Bank 3 Config == BE=0 */
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
mtdcr (SDRAM0_CFGDATA, 0x00000000); mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* refresh timer = 0x400 */ /* refresh timer = 0x400 */
mtdcr (SDRAM0_CFGADDR, mem_rtr); mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, 0x04000000); mtdcr (SDRAM0_CFGDATA, 0x04000000);
/* Power management idle timer set to the default. */ /* Power management idle timer set to the default. */
mtdcr (SDRAM0_CFGADDR, mem_pmit); mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
mtdcr (SDRAM0_CFGDATA, 0x07c00000); mtdcr (SDRAM0_CFGDATA, 0x07c00000);
udelay (500); udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x80e00000); mtdcr (SDRAM0_CFGDATA, 0x80e00000);
return SDRAM_LEN; return SDRAM_LEN;
@ -108,7 +108,7 @@ int testdram (void)
#ifdef DEBUG #ifdef DEBUG
printf ("SDRAM Controller Registers --\n"); printf ("SDRAM Controller Registers --\n");
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
val = mfdcr (SDRAM0_CFGDATA); val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_CFG : 0x%08x\n", val); printf (" SDRAM0_CFG : 0x%08x\n", val);
@ -116,19 +116,19 @@ int testdram (void)
val = mfdcr (SDRAM0_CFGDATA); val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_STATUS: 0x%08x\n", val); printf (" SDRAM0_STATUS: 0x%08x\n", val);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
val = mfdcr (SDRAM0_CFGDATA); val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B0CR : 0x%08x\n", val); printf (" SDRAM0_B0CR : 0x%08x\n", val);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
val = mfdcr (SDRAM0_CFGDATA); val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B1CR : 0x%08x\n", val); printf (" SDRAM0_B1CR : 0x%08x\n", val);
mtdcr (SDRAM0_CFGADDR, mem_sdtr1); mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
val = mfdcr (SDRAM0_CFGDATA); val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_TR : 0x%08x\n", val); printf (" SDRAM0_TR : 0x%08x\n", val);
mtdcr (SDRAM0_CFGADDR, mem_rtr); mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
val = mfdcr (SDRAM0_CFGDATA); val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_RTR : 0x%08x\n", val); printf (" SDRAM0_RTR : 0x%08x\n", val);
#endif #endif

38
board/mpl/mip405/mip405.c
Unescape View File

@ -348,7 +348,7 @@ int init_sdram (void)
/* trc_clocks is sum of trp_clocks + tras_clocks */ /* trc_clocks is sum of trp_clocks + tras_clocks */
trc_clocks = trp_clocks + tras_clocks; trc_clocks = trp_clocks + tras_clocks;
/* get SDRAM timing register */ /* get SDRAM timing register */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1); mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */ /* insert CASL value */
sdram_tim |= ((unsigned long) (cal_val)) << 23; sdram_tim |= ((unsigned long) (cal_val)) << 23;
@ -369,7 +369,7 @@ int init_sdram (void)
/* insert SZ value; */ /* insert SZ value; */
tmp |= ((unsigned long) sdram_table[i].sz << 17); tmp |= ((unsigned long) sdram_table[i].sz << 17);
/* get SDRAM bank 0 register */ /* get SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_bank |= (baseaddr | tmp | 0x01); sdram_bank |= (baseaddr | tmp | 0x01);
@ -380,7 +380,7 @@ int init_sdram (void)
#endif #endif
/* write SDRAM timing register */ /* write SDRAM timing register */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1); mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, sdram_tim); mtdcr (SDRAM0_CFGDATA, sdram_tim);
#ifdef SDRAM_DEBUG #ifdef SDRAM_DEBUG
@ -390,22 +390,22 @@ int init_sdram (void)
#endif #endif
/* write SDRAM bank 0 register */ /* write SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, sdram_bank); mtdcr (SDRAM0_CFGDATA, sdram_bank);
if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
/* get SDRAM refresh interval register */ /* get SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr); mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x07F00000; tmp |= 0x07F00000;
} else { } else {
/* get SDRAM refresh interval register */ /* get SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr); mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x05F00000; tmp |= 0x05F00000;
} }
/* write SDRAM refresh interval register */ /* write SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr); mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
/* enable ECC if used */ /* enable ECC if used */
#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
@ -415,18 +415,18 @@ int init_sdram (void)
#ifdef SDRAM_DEBUG #ifdef SDRAM_DEBUG
serial_puts ("disable ECC.. "); serial_puts ("disable ECC.. ");
#endif #endif
mtdcr (SDRAM0_CFGADDR, mem_ecccf); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff; /* disable all banks */ tmp &= 0xff0fffff; /* disable all banks */
mtdcr (SDRAM0_CFGADDR, mem_ecccf); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
/* set up SDRAM Controller with ECC enabled */ /* set up SDRAM Controller with ECC enabled */
#ifdef SDRAM_DEBUG #ifdef SDRAM_DEBUG
serial_puts ("setup SDRAM Controller.. "); serial_puts ("setup SDRAM Controller.. ");
#endif #endif
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600); udelay (600);
#ifdef SDRAM_DEBUG #ifdef SDRAM_DEBUG
@ -447,7 +447,7 @@ int init_sdram (void)
serial_puts ("enable ECC\n"); serial_puts ("enable ECC\n");
#endif #endif
udelay (400); udelay (400);
mtdcr (SDRAM0_CFGADDR, mem_ecccf); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000; /* enable bank 0 */ tmp |= 0x00800000; /* enable bank 0 */
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
@ -456,9 +456,9 @@ int init_sdram (void)
#endif #endif
{ {
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400); udelay (400);
} }
@ -631,13 +631,13 @@ phys_size_t initdram (int board_type)
ds = 0; ds = 0;
/* since the DRAM controller is allready set up, calculate the size with the /* since the DRAM controller is allready set up, calculate the size with the
bank registers */ bank registers */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
bank_reg[0] = mfdcr (SDRAM0_CFGDATA); bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
bank_reg[1] = mfdcr (SDRAM0_CFGDATA); bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
bank_reg[2] = mfdcr (SDRAM0_CFGDATA); bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
bank_reg[3] = mfdcr (SDRAM0_CFGDATA); bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0; TotalSize = 0;
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
@ -648,7 +648,7 @@ phys_size_t initdram (int board_type)
} else } else
ds = 1; ds = 1;
} }
mtdcr (SDRAM0_CFGADDR, mem_ecccf); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);
if (!tmp) if (!tmp)

36
board/mpl/pip405/pip405.c
Unescape View File

@ -361,7 +361,7 @@ int board_early_init_f (void)
SDRAM_err ("unsupported SDRAM"); SDRAM_err ("unsupported SDRAM");
/* get SDRAM timing register */ /* get SDRAM timing register */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1); mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */ /* insert CASL value */
/* tmp |= ((unsigned long)cal_val) << 23; */ /* tmp |= ((unsigned long)cal_val) << 23; */
@ -385,7 +385,7 @@ int board_early_init_f (void)
#endif #endif
/* write SDRAM timing register */ /* write SDRAM timing register */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1); mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
baseaddr = CONFIG_SYS_SDRAM_BASE; baseaddr = CONFIG_SYS_SDRAM_BASE;
bank_size = (((unsigned long) density) << 22) / 2; bank_size = (((unsigned long) density) << 22) / 2;
@ -418,7 +418,7 @@ int board_early_init_f (void)
SDRAM_err ("unsupported SDRAM"); SDRAM_err ("unsupported SDRAM");
} /* endswitch */ } /* endswitch */
/* get SDRAM bank 0 register */ /* get SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01); bank |= (baseaddr | tmp | 0x01);
#ifdef SDRAM_DEBUG #ifdef SDRAM_DEBUG
@ -434,11 +434,11 @@ int board_early_init_f (void)
sdram_size += bank_size; sdram_size += bank_size;
/* write SDRAM bank 0 register */ /* write SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, bank); mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 1 register */ /* get SDRAM bank 1 register */
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_size = 0; sdram_size = 0;
@ -459,11 +459,11 @@ int board_early_init_f (void)
serial_puts ("\n"); serial_puts ("\n");
#endif #endif
/* write SDRAM bank 1 register */ /* write SDRAM bank 1 register */
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
mtdcr (SDRAM0_CFGDATA, bank); mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 2 register */ /* get SDRAM bank 2 register */
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01); bank |= (baseaddr | tmp | 0x01);
@ -482,11 +482,11 @@ int board_early_init_f (void)
sdram_size += bank_size; sdram_size += bank_size;
/* write SDRAM bank 2 register */ /* write SDRAM bank 2 register */
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
mtdcr (SDRAM0_CFGDATA, bank); mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 3 register */ /* get SDRAM bank 3 register */
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
#ifdef SDRAM_DEBUG #ifdef SDRAM_DEBUG
@ -509,12 +509,12 @@ int board_early_init_f (void)
#endif #endif
/* write SDRAM bank 3 register */ /* write SDRAM bank 3 register */
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
mtdcr (SDRAM0_CFGDATA, bank); mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM refresh interval register */ /* get SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr); mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
if (tmemclk < NSto10PS (16)) if (tmemclk < NSto10PS (16))
@ -523,13 +523,13 @@ int board_early_init_f (void)
tmp |= 0x03F80000; tmp |= 0x03F80000;
/* write SDRAM refresh interval register */ /* write SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr); mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp); mtdcr (SDRAM0_CFGDATA, tmp);
@ -619,13 +619,13 @@ phys_size_t initdram (int board_type)
/* since the DRAM controller is allready set up, /* since the DRAM controller is allready set up,
* calculate the size with the bank registers * calculate the size with the bank registers
*/ */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
bank_reg[0] = mfdcr (SDRAM0_CFGDATA); bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
bank_reg[1] = mfdcr (SDRAM0_CFGDATA); bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
bank_reg[2] = mfdcr (SDRAM0_CFGDATA); bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
bank_reg[3] = mfdcr (SDRAM0_CFGDATA); bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0; TotalSize = 0;
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {

40
board/netstal/common/fixed_sdram.c
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@ -29,17 +29,17 @@ void show_sdram_registers(void)
u32 value; u32 value;
printf("SDRAM Controller Registers --\n"); printf("SDRAM Controller Registers --\n");
mfsdram(mem_mcopt1, value); mfsdram(SDRAM0_CFG, value);
printf(" SDRAM0_CFG : 0x%08x\n", value); printf(" SDRAM0_CFG : 0x%08x\n", value);
mfsdram(mem_status, value); mfsdram(SDRAM0_STATUS, value);
printf(" SDRAM0_STATUS: 0x%08x\n", value); printf(" SDRAM0_STATUS: 0x%08x\n", value);
mfsdram(mem_mb0cf, value); mfsdram(SDRAM0_B0CR, value);
printf(" SDRAM0_B0CR : 0x%08x\n", value); printf(" SDRAM0_B0CR : 0x%08x\n", value);
mfsdram(mem_mb1cf, value); mfsdram(SDRAM0_B1CR, value);
printf(" SDRAM0_B1CR : 0x%08x\n", value); printf(" SDRAM0_B1CR : 0x%08x\n", value);
mfsdram(mem_sdtr1, value); mfsdram(SDRAM0_TR, value);
printf(" SDRAM0_TR : 0x%08x\n", value); printf(" SDRAM0_TR : 0x%08x\n", value);
mfsdram(mem_rtr, value); mfsdram(SDRAM0_RTR, value);
printf(" SDRAM0_RTR : 0x%08x\n", value); printf(" SDRAM0_RTR : 0x%08x\n", value);
} }
#endif #endif
@ -50,53 +50,53 @@ long int init_ppc405_sdram(unsigned int dram_size)
printf(__FUNCTION__); printf(__FUNCTION__);
#endif #endif
/* disable memory controller */ /* disable memory controller */
mtsdram(mem_mcopt1, 0x00000000); mtsdram(SDRAM0_CFG, 0x00000000);
udelay (500); udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
mtsdram(mem_besra, 0xffffffff); mtsdram(SDRAM0_BESR0, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
mtsdram(mem_besrb, 0xffffffff); mtsdram(SDRAM0_BESR1, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */ /* Clear SDRAM0_ECCCFG (disable ECC) */
mtsdram(mem_ecccf, 0x00000000); mtsdram(SDRAM0_ECCCFG, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
mtsdram(mem_eccerr, 0xffffffff); mtsdram(SDRAM0_ECCESR, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
*/ */
mtsdram(mem_sdtr1, 0x008a4015); mtsdram(SDRAM0_TR, 0x008a4015);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
* and refresh timer * and refresh timer
*/ */
switch (dram_size >> 20) { switch (dram_size >> 20) {
case 32: case 32:
mtsdram(mem_mb0cf, 0x00062001); mtsdram(SDRAM0_B0CR, 0x00062001);
mtsdram(mem_rtr, 0x07F00000); mtsdram(SDRAM0_RTR, 0x07F00000);
break; break;
case 64: case 64:
mtsdram(mem_mb0cf, 0x00084001); mtsdram(SDRAM0_B0CR, 0x00084001);
mtsdram(mem_rtr, 0x04100000); mtsdram(SDRAM0_RTR, 0x04100000);
break; break;
case 128: case 128:
mtsdram(mem_mb0cf, 0x000A4001); mtsdram(SDRAM0_B0CR, 0x000A4001);
mtsdram(mem_rtr, 0x04100000); mtsdram(SDRAM0_RTR, 0x04100000);
break; break;
default: default:
printf("Invalid memory size of %d MB given\n", dram_size >> 20); printf("Invalid memory size of %d MB given\n", dram_size >> 20);
} }
/* Power management idle timer set to the default. */ /* Power management idle timer set to the default. */
mtsdram(mem_pmit, 0x07c00000); mtsdram(SDRAM0_PMIT, 0x07c00000);
udelay (500); udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */ /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
mtsdram(mem_mcopt1, 0x90800000); mtsdram(SDRAM0_CFG, 0x90800000);
#ifdef DEBUG #ifdef DEBUG
printf("%s: done\n", __FUNCTION__); printf("%s: done\n", __FUNCTION__);

24
board/sandburst/common/sb_common.c
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@ -266,11 +266,11 @@ long int fixed_sdram (void)
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup some default * Setup some default
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup for board-specific specific mem * Setup for board-specific specific mem
@ -278,20 +278,20 @@ long int fixed_sdram (void)
/* /*
* Following for CAS Latency = 2.5 @ 133 MHz PLB * Following for CAS Latency = 2.5 @ 133 MHz PLB
*/ */
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */ /* RA=10 RD=3 */
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */ udelay (400); /* Delay 200 usecs (min) */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete * Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) { for (;;) {
mfsdram (mem_mcsts, reg); mfsdram (SDRAM0_MCSTS, reg);
if (reg & 0x80000000) if (reg & 0x80000000)
break; break;
} }

22
board/sc3/sc3.c
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@ -577,7 +577,7 @@ static int printSDRAMConfig(char reg, unsigned long cr)
} }
#ifdef SC3_DEBUGOUT #ifdef SC3_DEBUGOUT
static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf}; static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR};
#endif #endif
phys_size_t initdram (int board_type) phys_size_t initdram (int board_type)
@ -591,7 +591,7 @@ phys_size_t initdram (int board_type)
puts("\nSDRAM configuration:\n"); puts("\nSDRAM configuration:\n");
mtdcr (SDRAM0_CFGADDR, mem_mcopt1); mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
ul1 = mfdcr(SDRAM0_CFGDATA); ul1 = mfdcr(SDRAM0_CFGDATA);
if (!(ul1 & 0x80000000)) { if (!(ul1 & 0x80000000)) {
@ -604,7 +604,7 @@ phys_size_t initdram (int board_type)
mems += printSDRAMConfig (i, ul1); mems += printSDRAMConfig (i, ul1);
} }
mtdcr (SDRAM0_CFGADDR, mem_sdtr1); mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
ul1 = mfdcr(SDRAM0_CFGDATA); ul1 = mfdcr(SDRAM0_CFGDATA);
printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1); printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
@ -614,14 +614,14 @@ phys_size_t initdram (int board_type)
printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4); printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1)); printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
puts ("Misc:\n"); puts ("Misc:\n");
mtdcr (SDRAM0_CFGADDR, mem_rtr); mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
ul1 = mfdcr(SDRAM0_CFGDATA); ul1 = mfdcr(SDRAM0_CFGDATA);
printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7); printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
mtdcr(SDRAM0_CFGADDR,mem_pmit); mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT);
ul2=mfdcr(SDRAM0_CFGDATA); ul2=mfdcr(SDRAM0_CFGDATA);
mtdcr(SDRAM0_CFGADDR,mem_mcopt1); mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG);
ul1=mfdcr(SDRAM0_CFGDATA); ul1=mfdcr(SDRAM0_CFGDATA);
if (ul1 & 0x20000000) if (ul1 & 0x20000000)
@ -658,7 +658,7 @@ phys_size_t initdram (int board_type)
else else
puts(" -Memory lines only at write cycles active outputs\n"); puts(" -Memory lines only at write cycles active outputs\n");
mtdcr (SDRAM0_CFGADDR, mem_status); mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS);
ul1 = mfdcr (SDRAM0_CFGDATA); ul1 = mfdcr (SDRAM0_CFGDATA);
if (ul1 & 0x80000000) if (ul1 & 0x80000000)
puts(" -SDRAM Controller ready\n"); puts(" -SDRAM Controller ready\n");
@ -670,19 +670,19 @@ phys_size_t initdram (int board_type)
return (mems * 1024 * 1024); return (mems * 1024 * 1024);
#else #else
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
ul1 = mfdcr (SDRAM0_CFGDATA); ul1 = mfdcr (SDRAM0_CFGDATA);
mems = printSDRAMConfig (0, ul1); mems = printSDRAMConfig (0, ul1);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
ul1 = mfdcr (SDRAM0_CFGDATA); ul1 = mfdcr (SDRAM0_CFGDATA);
mems += printSDRAMConfig (1, ul1); mems += printSDRAMConfig (1, ul1);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
ul1 = mfdcr(SDRAM0_CFGDATA); ul1 = mfdcr(SDRAM0_CFGDATA);
mems += printSDRAMConfig (2, ul1); mems += printSDRAMConfig (2, ul1);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
ul1 = mfdcr(SDRAM0_CFGDATA); ul1 = mfdcr(SDRAM0_CFGDATA);
mems += printSDRAMConfig (3, ul1); mems += printSDRAMConfig (3, ul1);

10
board/w7o/init.S
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@ -182,7 +182,7 @@ sdram_init:
* Disable memory controller to allow * Disable memory controller to allow
* values to be changed. * values to be changed.
*/ */
addi r3, 0, mem_mcopt1 addi r3, 0, SDRAM0_CFG
mtdcr SDRAM0_CFGADDR, r3 mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x0 addis r4, 0, 0x0
ori r4, r4, 0x0 ori r4, r4, 0x0
@ -192,7 +192,7 @@ sdram_init:
* Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
* All other banks are disabled. * All other banks are disabled.
*/ */
addi r3, 0, mem_mb0cf addi r3, 0, SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR, r3 mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
@ -222,7 +222,7 @@ sdram_init:
/* /*
* Set up SDTR1 * Set up SDTR1
*/ */
addi r3, 0, mem_sdtr1 addi r3, 0, SDRAM0_TR
mtdcr SDRAM0_CFGADDR, r3 mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
ori r4, r4, 0x400D ori r4, r4, 0x400D
@ -231,7 +231,7 @@ sdram_init:
/* /*
* Set RTR * Set RTR
*/ */
addi r3, 0, mem_rtr addi r3, 0, SDRAM0_RTR
mtdcr SDRAM0_CFGADDR, r3 mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
mtdcr SDRAM0_CFGDATA, r4 mtdcr SDRAM0_CFGDATA, r4
@ -250,7 +250,7 @@ sdram_init:
/******************************************************************** /********************************************************************
* Set memory controller options reg, MCOPT1. * Set memory controller options reg, MCOPT1.
*******************************************************************/ *******************************************************************/
addi r3, 0, mem_mcopt1 addi r3, 0, SDRAM0_CFG
mtdcr SDRAM0_CFGADDR, r3 mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */

8
board/w7o/w7o.c
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@ -170,16 +170,16 @@ unsigned long get_dram_size (void)
int size = 0; int size = 0;
/* Get bank Size registers */ /* Get bank Size registers */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); /* get bank 0 config reg */ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */
regs[0] = mfdcr (SDRAM0_CFGDATA); regs[0] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); /* get bank 1 config reg */ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */
regs[1] = mfdcr (SDRAM0_CFGDATA); regs[1] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); /* get bank 2 config reg */ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */
regs[2] = mfdcr (SDRAM0_CFGDATA); regs[2] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); /* get bank 3 config reg */ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */
regs[3] = mfdcr (SDRAM0_CFGDATA); regs[3] = mfdcr (SDRAM0_CFGDATA);
/* compute the size, add each bank if enabled */ /* compute the size, add each bank if enabled */

42
common/cmd_reginfo.c
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@ -108,24 +108,24 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
puts ("\nMemory (SDRAM) Configuration\n" puts ("\nMemory (SDRAM) Configuration\n"
"besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
mtdcr(SDRAM0_CFGADDR,mem_besra); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_besrsa); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_besrb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_besrsb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_bear); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_BEAR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
puts ("\n" puts ("\n"
"mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb2cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_B2CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb3cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_B3CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_ecccf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCCFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_eccerr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCESR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
printf ("\n\n" printf ("\n\n"
"DMA Channels\n" "DMA Channels\n"
@ -195,12 +195,12 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
puts ("\nMemory (SDRAM) Configuration\n" puts ("\nMemory (SDRAM) Configuration\n"
"mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
printf ("\n\n" printf ("\n\n"
"DMA Channels\n" "DMA Channels\n"

26
cpu/ppc4xx/40x_spd_sdram.c
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@ -424,30 +424,30 @@ long int spd_sdram(int(read_spd)(uint addr))
#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) #define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */ /* disable memcontroller so updates work */
mtsdram0( mem_mcopt1, 0 ); mtsdram0( SDRAM0_CFG, 0 );
#ifndef CONFIG_405EP /* not on PPC405EP */ #ifndef CONFIG_405EP /* not on PPC405EP */
mtsdram0( mem_besra , sdram0_besr0 ); mtsdram0( SDRAM0_BESR0 , sdram0_besr0 );
mtsdram0( mem_besrb , sdram0_besr1 ); mtsdram0( SDRAM0_BESR1 , sdram0_besr1 );
mtsdram0( mem_ecccf , sdram0_ecccfg ); mtsdram0( SDRAM0_ECCCFG , sdram0_ecccfg );
mtsdram0( mem_eccerr, sdram0_eccesr ); mtsdram0( SDRAM0_ECCESR, sdram0_eccesr );
#endif #endif
mtsdram0( mem_rtr , sdram0_rtr ); mtsdram0( SDRAM0_RTR , sdram0_rtr );
mtsdram0( mem_pmit , sdram0_pmit ); mtsdram0( SDRAM0_PMIT , sdram0_pmit );
mtsdram0( mem_mb0cf , sdram0_b0cr ); mtsdram0( SDRAM0_B0CR , sdram0_b0cr );
mtsdram0( mem_mb1cf , sdram0_b1cr ); mtsdram0( SDRAM0_B1CR , sdram0_b1cr );
#ifndef CONFIG_405EP /* not on PPC405EP */ #ifndef CONFIG_405EP /* not on PPC405EP */
mtsdram0( mem_mb2cf , sdram0_b2cr ); mtsdram0( SDRAM0_B2CR , sdram0_b2cr );
mtsdram0( mem_mb3cf , sdram0_b3cr ); mtsdram0( SDRAM0_B3CR , sdram0_b3cr );
#endif #endif
mtsdram0( mem_sdtr1 , sdram0_tr ); mtsdram0( SDRAM0_TR , sdram0_tr );
/* SDRAM have a power on delay, 500 micro should do */ /* SDRAM have a power on delay, 500 micro should do */
udelay(500); udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
if (ecc_on) if (ecc_on)
sdram0_cfg |= SDRAM0_CFG_MEMCHK; sdram0_cfg |= SDRAM0_CFG_MEMCHK;
mtsdram0(mem_mcopt1, sdram0_cfg); mtsdram0(SDRAM0_CFG, sdram0_cfg);
return (total_size); return (total_size);
} }

44
cpu/ppc4xx/44x_spd_ddr.c
Unescape View File

@ -230,7 +230,7 @@ long int spd_sdram(void) {
/* /*
* program SDRAM Clock Timing Register (SDRAM0_CLKTR) * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
*/ */
mtsdram(mem_clktr, 0x40000000); mtsdram(SDRAM0_CLKTR, 0x40000000);
/* /*
* delay to ensure 200 usec has elapsed * delay to ensure 200 usec has elapsed
@ -240,14 +240,14 @@ long int spd_sdram(void) {
/* /*
* enable the memory controller * enable the memory controller
*/ */
mfsdram(mem_cfg0, cfg0); mfsdram(SDRAM0_CFG0, cfg0);
mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN); mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
/* /*
* wait for SDRAM_CFG0_DC_EN to complete * wait for SDRAM_CFG0_DC_EN to complete
*/ */
while (1) { while (1) {
mfsdram(mem_mcsts, mcsts); mfsdram(SDRAM0_MCSTS, mcsts);
if ((mcsts & SDRAM_MCSTS_MRSC) != 0) if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
break; break;
} }
@ -386,7 +386,7 @@ static void program_cfg0(unsigned long *dimm_populated,
/* /*
* get Memory Controller Options 0 data * get Memory Controller Options 0 data
*/ */
mfsdram(mem_cfg0, cfg0); mfsdram(SDRAM0_CFG0, cfg0);
/* /*
* clear bits * clear bits
@ -457,7 +457,7 @@ static void program_cfg0(unsigned long *dimm_populated,
* Note: DCEN must be enabled after all DDR SDRAM controller * Note: DCEN must be enabled after all DDR SDRAM controller
* configuration registers get initialized. * configuration registers get initialized.
*/ */
mtsdram(mem_cfg0, cfg0); mtsdram(SDRAM0_CFG0, cfg0);
} }
static void program_cfg1(unsigned long *dimm_populated, static void program_cfg1(unsigned long *dimm_populated,
@ -465,7 +465,7 @@ static void program_cfg1(unsigned long *dimm_populated,
unsigned long num_dimm_banks) unsigned long num_dimm_banks)
{ {
unsigned long cfg1; unsigned long cfg1;
mfsdram(mem_cfg1, cfg1); mfsdram(SDRAM0_CFG1, cfg1);
/* /*
* Self-refresh exit, disable PM * Self-refresh exit, disable PM
@ -475,7 +475,7 @@ static void program_cfg1(unsigned long *dimm_populated,
/* /*
* program Memory Controller Options 1 * program Memory Controller Options 1
*/ */
mtsdram(mem_cfg1, cfg1); mtsdram(SDRAM0_CFG1, cfg1);
} }
static void program_rtr(unsigned long *dimm_populated, static void program_rtr(unsigned long *dimm_populated,
@ -535,7 +535,7 @@ static void program_rtr(unsigned long *dimm_populated,
/* /*
* program Refresh Timer Register (SDRAM0_RTR) * program Refresh Timer Register (SDRAM0_RTR)
*/ */
mtsdram(mem_rtr, sdram_rtr); mtsdram(SDRAM0_RTR, sdram_rtr);
} }
static void program_tr0(unsigned long *dimm_populated, static void program_tr0(unsigned long *dimm_populated,
@ -576,7 +576,7 @@ static void program_tr0(unsigned long *dimm_populated,
/* /*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/ */
mfsdram(mem_tr0, tr0); mfsdram(SDRAM0_TR0, tr0);
tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK | tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK | SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK | SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
@ -821,7 +821,7 @@ static void program_tr0(unsigned long *dimm_populated,
} }
debug("tr0: %x\n", tr0); debug("tr0: %x\n", tr0);
mtsdram(mem_tr0, tr0); mtsdram(SDRAM0_TR0, tr0);
} }
static int short_mem_test(void) static int short_mem_test(void)
@ -848,7 +848,7 @@ static int short_mem_test(void)
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2)); mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
/* Bank is enabled */ /* Bank is enabled */
membase = (unsigned long*) membase = (unsigned long*)
@ -918,11 +918,11 @@ static void program_tr1(void)
/* /*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/ */
mfsdram(mem_tr1, tr1); mfsdram(SDRAM0_TR1, tr1);
tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK | tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK); SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
mfsdram(mem_tr0, tr0); mfsdram(SDRAM0_TR0, tr0);
if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) && if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
(sys_info.freqPLB > 100000000)) { (sys_info.freqPLB > 100000000)) {
tr1 |= SDRAM_TR1_RDSS_TR2; tr1 |= SDRAM_TR1_RDSS_TR2;
@ -937,14 +937,14 @@ static void program_tr1(void)
/* /*
* save CFG0 ECC setting to a temporary variable and turn ECC off * save CFG0 ECC setting to a temporary variable and turn ECC off
*/ */
mfsdram(mem_cfg0, cfg0); mfsdram(SDRAM0_CFG0, cfg0);
ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK; ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
/* /*
* get the delay line calibration register value * get the delay line calibration register value
*/ */
mfsdram(mem_dlycal, dlycal); mfsdram(SDRAM0_DLYCAL, dlycal);
dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
max_pass_length = 0; max_pass_length = 0;
@ -964,7 +964,7 @@ static void program_tr1(void)
/* /*
* Set the timing reg for the test. * Set the timing reg for the test.
*/ */
mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
if (short_mem_test()) { if (short_mem_test()) {
if (fail_found == TRUE) { if (fail_found == TRUE) {
@ -1018,7 +1018,7 @@ static void program_tr1(void)
/* /*
* restore the orignal ECC setting * restore the orignal ECC setting
*/ */
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
/* /*
* set the SDRAM TR1 RDCD value * set the SDRAM TR1 RDCD value
@ -1056,7 +1056,7 @@ static void program_tr1(void)
/* /*
* program SDRAM Timing Register 1 TR1 * program SDRAM Timing Register 1 TR1
*/ */
mtsdram(mem_tr1, tr1); mtsdram(SDRAM0_TR1, tr1);
} }
static unsigned long program_bxcr(unsigned long *dimm_populated, static unsigned long program_bxcr(unsigned long *dimm_populated,
@ -1086,7 +1086,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
* Set the BxCR regs. First, wipe out the bank config registers. * Set the BxCR regs. First, wipe out the bank config registers.
*/ */
for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2)); mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
mtdcr(SDRAM0_CFGDATA, 0x00000000); mtdcr(SDRAM0_CFGDATA, 0x00000000);
bank_parms[bx_cr_num].bank_size_bytes = 0; bank_parms[bx_cr_num].bank_size_bytes = 0;
} }
@ -1232,7 +1232,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
/* Set the SDRAM0_BxCR regs thanks to sort tables */ /* Set the SDRAM0_BxCR regs thanks to sort tables */
for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |

60
cpu/ppc4xx/sdram.c
Unescape View File

@ -188,14 +188,14 @@ phys_size_t initdram(int board_type)
/* /*
* Disable memory controller. * Disable memory controller.
*/ */
mtsdram(mem_mcopt1, 0x00000000); mtsdram(SDRAM0_CFG, 0x00000000);
/* /*
* Set MB0CF for bank 0. * Set MB0CF for bank 0.
*/ */
mtsdram(mem_mb0cf, mb0cf[i].reg); mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
mtsdram(mem_sdtr1, sdtr1); mtsdram(SDRAM0_TR, sdtr1);
mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64)); mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200); udelay(200);
@ -204,7 +204,7 @@ phys_size_t initdram(int board_type)
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch. * read/prefetch.
*/ */
mtsdram(mem_mcopt1, 0x80800000); mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000); udelay(10000);
@ -216,9 +216,9 @@ phys_size_t initdram(int board_type)
* defined (assumes same type as bank 0) * defined (assumes same type as bank 0)
*/ */
#ifdef CONFIG_SDRAM_BANK1 #ifdef CONFIG_SDRAM_BANK1
mtsdram(mem_mcopt1, 0x00000000); mtsdram(SDRAM0_CFG, 0x00000000);
mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg); mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
mtsdram(mem_mcopt1, 0x80800000); mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000); udelay(10000);
/* /*
@ -228,8 +228,8 @@ phys_size_t initdram(int board_type)
*/ */
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) != if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
mb0cf[i].size) { mb0cf[i].size) {
mtsdram(mem_mb1cf, 0); mtsdram(SDRAM0_B1CR, 0);
mtsdram(mem_mcopt1, 0); mtsdram(SDRAM0_CFG, 0);
} else { } else {
/* /*
* We have two identical banks, so the size * We have two identical banks, so the size
@ -315,7 +315,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
/* go through all possible SDRAM0_TR1[RDCT] values */ /* go through all possible SDRAM0_TR1[RDCT] values */
for (i=0; i<=0x1ff; i++) { for (i=0; i<=0x1ff; i++) {
/* set the current value for TR1 */ /* set the current value for TR1 */
mtsdram(mem_tr1, (0x80800800 | i)); mtsdram(SDRAM0_TR1, (0x80800800 | i));
/* write values */ /* write values */
for (j=0; j<NUM_TRIES; j++) { for (j=0; j<NUM_TRIES; j++) {
@ -383,31 +383,31 @@ phys_size_t initdram(int board_type)
/* /*
* Disable memory controller. * Disable memory controller.
*/ */
mtsdram(mem_cfg0, 0x00000000); mtsdram(SDRAM0_CFG0, 0x00000000);
/* /*
* Setup some default * Setup some default
*/ */
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_wddctr, CONFIG_SYS_SDRAM0_WDDCTR); mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/* /*
* Following for CAS Latency = 2.5 @ 133 MHz PLB * Following for CAS Latency = 2.5 @ 133 MHz PLB
*/ */
mtsdram(mem_b0cr, mb0cf[i].reg); mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0); mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(mem_rtr, CONFIG_SYS_SDRAM0_RTR); mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
udelay(400); /* Delay 200 usecs (min) */ udelay(400); /* Delay 200 usecs (min) */
/* /*
* Enable the controller, then wait for DCEN to complete * Enable the controller, then wait for DCEN to complete
*/ */
mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000); udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
@ -416,7 +416,7 @@ phys_size_t initdram(int board_type)
* Optimize TR1 to current hardware environment * Optimize TR1 to current hardware environment
*/ */
sdram_tr1_set(0x00000000, &tr1_bank1); sdram_tr1_set(0x00000000, &tr1_bank1);
mtsdram(mem_tr1, (tr1_bank1 | 0x80800800)); mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800));
/* /*
@ -424,9 +424,9 @@ phys_size_t initdram(int board_type)
* defined (assumes same type as bank 0) * defined (assumes same type as bank 0)
*/ */
#ifdef CONFIG_SDRAM_BANK1 #ifdef CONFIG_SDRAM_BANK1
mtsdram(mem_cfg0, 0); mtsdram(SDRAM0_CFG0, 0);
mtsdram(mem_b1cr, mb0cf[i].size | mb0cf[i].reg); mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000); udelay(10000);
/* /*
@ -436,9 +436,9 @@ phys_size_t initdram(int board_type)
*/ */
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
!= mb0cf[i].size) { != mb0cf[i].size) {
mtsdram(mem_cfg0, 0); mtsdram(SDRAM0_CFG0, 0);
mtsdram(mem_b1cr, 0); mtsdram(SDRAM0_B1CR, 0);
mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000); udelay(10000);
} else { } else {
/* /*

86
include/asm-ppc/ppc4xx-sdram.h
Unescape View File

@ -30,32 +30,27 @@
* SDRAM Controller * SDRAM Controller
*/ */
/*
* XXX - ToDo: Revisit file to change all these lower case defines into
* upper case. Also needs to be done in the controller setup code too
* of course. sr, 2008-06-02
*/
#ifndef CONFIG_405EP #ifndef CONFIG_405EP
#define mem_besra 0x00 /* bus error syndrome reg a */ #define SDRAM0_BESR0 0x00 /* bus error syndrome reg a */
#define mem_besrsa 0x04 /* bus error syndrome reg set a */ #define SDRAM0_BESRS0 0x04 /* bus error syndrome reg set a */
#define mem_besrb 0x08 /* bus error syndrome reg b */ #define SDRAM0_BESR1 0x08 /* bus error syndrome reg b */
#define mem_besrsb 0x0c /* bus error syndrome reg set b */ #define SDRAM0_BESRS1 0x0c /* bus error syndrome reg set b */
#define mem_bear 0x10 /* bus error address reg */ #define SDRAM0_BEAR 0x10 /* bus error address reg */
#endif #endif
#define mem_mcopt1 0x20 /* memory controller options 1 */ #define SDRAM0_CFG 0x20 /* memory controller options 1 */
#define mem_status 0x24 /* memory status */ #define SDRAM0_STATUS 0x24 /* memory status */
#define mem_rtr 0x30 /* refresh timer reg */ #define SDRAM0_RTR 0x30 /* refresh timer reg */
#define mem_pmit 0x34 /* power management idle timer */ #define SDRAM0_PMIT 0x34 /* power management idle timer */
#define mem_mb0cf 0x40 /* memory bank 0 configuration */ #define SDRAM0_B0CR 0x40 /* memory bank 0 configuration */
#define mem_mb1cf 0x44 /* memory bank 1 configuration */ #define SDRAM0_B1CR 0x44 /* memory bank 1 configuration */
#ifndef CONFIG_405EP #ifndef CONFIG_405EP
#define mem_mb2cf 0x48 /* memory bank 2 configuration */ #define SDRAM0_B2CR 0x48 /* memory bank 2 configuration */
#define mem_mb3cf 0x4c /* memory bank 3 configuration */ #define SDRAM0_B3CR 0x4c /* memory bank 3 configuration */
#endif #endif
#define mem_sdtr1 0x80 /* timing reg 1 */ #define SDRAM0_TR 0x80 /* timing reg 1 */
#ifndef CONFIG_405EP #ifndef CONFIG_405EP
#define mem_ecccf 0x94 /* ECC configuration */ #define SDRAM0_ECCCFG 0x94 /* ECC configuration */
#define mem_eccerr 0x98 /* ECC error status */ #define SDRAM0_ECCESR 0x98 /* ECC error status */
#endif #endif
#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */ #endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
@ -68,36 +63,25 @@
#define SDRAM_CFG0 0x20 /* memory controller options 0 */ #define SDRAM_CFG0 0x20 /* memory controller options 0 */
#define SDRAM_CFG1 0x21 /* memory controller options 1 */ #define SDRAM_CFG1 0x21 /* memory controller options 1 */
/* #define SDRAM0_BEAR 0x0010 /* bus error address reg */
* XXX - ToDo: Revisit file to change all these lower case defines into #define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
* upper case. Also needs to be done in the controller setup code too #define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
* of course. sr, 2008-06-02 #define SDRAM0_CFG1 0x0021 /* ddr sdram options 1 */
*/ #define SDRAM0_DEVOPT 0x0022 /* ddr sdram device options */
#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ #define SDRAM0_MCSTS 0x0024 /* memory controller status */
#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ #define SDRAM0_RTR 0x0030 /* refresh timer register */
#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ #define SDRAM0_PMIT 0x0034 /* power management idle timer */
#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ #define SDRAM0_UABBA 0x0038 /* plb UABus base address */
#define mem_bear 0x0010 /* bus error address reg */ #define SDRAM0_B0CR 0x0040 /* ddr sdram bank 0 configuration */
#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ #define SDRAM0_B1CR 0x0044 /* ddr sdram bank 1 configuration */
#define mem_mirq_set 0x0012 /* bus master interrupt (set) */ #define SDRAM0_B2CR 0x0048 /* ddr sdram bank 2 configuration */
#define mem_slio 0x0018 /* ddr sdram slave interface options */ #define SDRAM0_B3CR 0x004c /* ddr sdram bank 3 configuration */
#define mem_cfg0 0x0020 /* ddr sdram options 0 */ #define SDRAM0_TR0 0x0080 /* sdram timing register 0 */
#define mem_cfg1 0x0021 /* ddr sdram options 1 */ #define SDRAM0_TR1 0x0081 /* sdram timing register 1 */
#define mem_devopt 0x0022 /* ddr sdram device options */ #define SDRAM0_CLKTR 0x0082 /* ddr clock timing register */
#define mem_mcsts 0x0024 /* memory controller status */ #define SDRAM0_WDDCTR 0x0083 /* write data/dm/dqs clock timing reg */
#define mem_rtr 0x0030 /* refresh timer register */ #define SDRAM0_DLYCAL 0x0084 /* delay line calibration register */
#define mem_pmit 0x0034 /* power management idle timer */ #define SDRAM0_ECCESR 0x0098 /* ECC error status */
#define mem_uabba 0x0038 /* plb UABus base address */
#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
#define mem_tr0 0x0080 /* sdram timing register 0 */
#define mem_tr1 0x0081 /* sdram timing register 1 */
#define mem_clktr 0x0082 /* ddr clock timing register */
#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
#define mem_dlycal 0x0084 /* delay line calibration register */
#define mem_eccesr 0x0098 /* ECC error status */
/* /*
* Memory Controller Options 0 * Memory Controller Options 0

26
nand_spl/board/amcc/bamboo/sdram.c
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@ -31,7 +31,7 @@ static void wait_init_complete(void)
u32 val; u32 val;
do { do {
mfsdram(mem_mcsts, val); mfsdram(SDRAM0_MCSTS, val);
} while (!(val & 0x80000000)); } while (!(val & 0x80000000));
} }
@ -62,30 +62,30 @@ phys_size_t initdram(int board_type)
/* /*
* Disable memory controller. * Disable memory controller.
*/ */
mtsdram(mem_cfg0, 0x00000000); mtsdram(SDRAM0_CFG0, 0x00000000);
/* /*
* Setup some default * Setup some default
*/ */
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/* /*
* Following for CAS Latency = 2.5 @ 133 MHz PLB * Following for CAS Latency = 2.5 @ 133 MHz PLB
*/ */
mtsdram(mem_b0cr, 0x00082001); mtsdram(SDRAM0_B0CR, 0x00082001);
mtsdram(mem_tr0, 0x41094012); mtsdram(SDRAM0_TR0, 0x41094012);
mtsdram(mem_tr1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(mem_rtr, 0x04100000); /* Interval 7.8ľs @ 133MHz PLB */ mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8ｵs @ 133MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
/* /*
* Enable the controller, then wait for DCEN to complete * Enable the controller, then wait for DCEN to complete
*/ */
mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/ mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
wait_init_complete(); wait_init_complete();
return CONFIG_SYS_MBYTES_SDRAM << 20; return CONFIG_SYS_MBYTES_SDRAM << 20;

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