@ -60,7 +60,7 @@
# define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
# define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
# define CONFIG_SYS_LDSCRIPT "arch / powerpc / cpu / mpc85xx / u-boot-nand.lds"
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define CONFIG_SYS_FSL_PBL_RCW board / freescale / t102xrdb / t1024_nand_rcw.cfg
# elif defined(CONFIG_TARGET_T1023RDB)
# define CONFIG_SYS_FSL_PBL_RCW board / freescale / t102xrdb / t1023_nand_rcw.cfg
@ -79,7 +79,7 @@
# ifndef CONFIG_SPL_BUILD
# define CONFIG_SYS_MPC85XX_NO_RESETVEC
# endif
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define CONFIG_SYS_FSL_PBL_RCW board / freescale / t102xrdb / t1024_spi_rcw.cfg
# elif defined(CONFIG_TARGET_T1023RDB)
# define CONFIG_SYS_FSL_PBL_RCW board / freescale / t102xrdb / t1023_spi_rcw.cfg
@ -98,7 +98,7 @@
# ifndef CONFIG_SPL_BUILD
# define CONFIG_SYS_MPC85XX_NO_RESETVEC
# endif
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define CONFIG_SYS_FSL_PBL_RCW board / freescale / t102xrdb / t1024_sd_rcw.cfg
# elif defined(CONFIG_TARGET_T1023RDB)
# define CONFIG_SYS_FSL_PBL_RCW board / freescale / t102xrdb / t1023_sd_rcw.cfg
@ -175,7 +175,7 @@
# define CONFIG_ENV_SPI_MODE 0
# define CONFIG_ENV_SIZE 0x2000 /* 8KB */
# define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define CONFIG_ENV_SECT_SIZE 0x10000
# elif defined(CONFIG_TARGET_T1023RDB)
# define CONFIG_ENV_SECT_SIZE 0x40000
@ -190,7 +190,7 @@
# define CONFIG_SYS_EXTRA_ENV_RELOC
# define CONFIG_ENV_IS_IN_NAND
# define CONFIG_ENV_SIZE 0x2000
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
# elif defined(CONFIG_TARGET_T1023RDB)
# define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
@ -271,7 +271,7 @@ unsigned long get_board_ddr_clk(void);
# define CONFIG_DIMM_SLOTS_PER_CTLR 1
# define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
# define CONFIG_FSL_DDR_INTERACTIVE
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define CONFIG_DDR_SPD
# define CONFIG_SYS_FSL_DDR3
# define CONFIG_SYS_SPD_BUS_NUM 0
@ -301,7 +301,7 @@ unsigned long get_board_ddr_clk(void);
# define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
# elif defined(CONFIG_TARGET_T1023RDB)
# define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
@ -330,7 +330,7 @@ unsigned long get_board_ddr_clk(void);
# define CONFIG_SYS_FLASH_EMPTY_INFO
# define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
# ifdef CONFIG_T1024RDB
# ifdef CONFIG_TARGET_T 1024RDB
/* CPLD on IFC */
# define CONFIG_SYS_CPLD_BASE 0xffdf0000
# define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
@ -369,7 +369,7 @@ unsigned long get_board_ddr_clk(void);
| CSPR_V )
# define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
@ -706,7 +706,7 @@ unsigned long get_board_ddr_clk(void);
# define CONFIG_SYS_DPAA_FMAN
# ifdef CONFIG_T1024RDB
# ifdef CONFIG_TARGET_T 1024RDB
# define CONFIG_QE
# define CONFIG_U_QE
# endif
@ -730,7 +730,7 @@ unsigned long get_board_ddr_clk(void);
# define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
# elif defined(CONFIG_NAND)
# define CONFIG_SYS_QE_FMAN_FW_IN_NAND
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
# define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
# elif defined(CONFIG_TARGET_T1023RDB)
@ -761,7 +761,7 @@ unsigned long get_board_ddr_clk(void);
# define CONFIG_PHYLIB_10G
# define CONFIG_PHY_REALTEK
# define CONFIG_PHY_AQUANTIA
# if defined(CONFIG_T1024RDB)
# if defined(CONFIG_TARGET_T 1024RDB)
# define RGMII_PHY1_ADDR 0x2
# define RGMII_PHY2_ADDR 0x6
# define SGMII_AQR_PHY_ADDR 0x2