Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>master
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/*
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* (C) Copyright 2017 |
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* Vikas Manocha, <vikas.manocha@st.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/fmc.h> |
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#include <asm/arch/stm32.h> |
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static inline u32 _ns2clk(u32 ns, u32 freq) |
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{ |
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u32 tmp = freq/1000000; |
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return (tmp * ns) / 1000; |
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} |
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#define NS2CLK(ns) (_ns2clk(ns, freq)) |
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/*
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* Following are timings for IS42S16400J, from corresponding datasheet |
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*/ |
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#define SDRAM_CAS 3 /* 3 cycles */ |
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#define SDRAM_NB 1 /* Number of banks */ |
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#define SDRAM_MWID 1 /* 16 bit memory */ |
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#define SDRAM_NR 0x1 /* 12-bit row */ |
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#define SDRAM_NC 0x0 /* 8-bit col */ |
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#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ |
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#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ |
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#define SDRAM_TRRD NS2CLK(12) |
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#define SDRAM_TRCD NS2CLK(18) |
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#define SDRAM_TRP NS2CLK(18) |
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#define SDRAM_TRAS NS2CLK(42) |
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#define SDRAM_TRC NS2CLK(60) |
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#define SDRAM_TRFC NS2CLK(60) |
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#define SDRAM_TCDL (1 - 1) |
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#define SDRAM_TRDL NS2CLK(12) |
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#define SDRAM_TBDL (1 - 1) |
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#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) |
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#define SDRAM_TCCD (1 - 1) |
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#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ |
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#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ |
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/* Last data in to row precharge, need also comply ineq on page 1648 */ |
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#define SDRAM_TWR max(\ |
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(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
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(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
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) |
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#define SDRAM_MODE_BL_SHIFT 0 |
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#define SDRAM_MODE_CAS_SHIFT 4 |
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#define SDRAM_MODE_BL 0 |
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#define SDRAM_MODE_CAS SDRAM_CAS |
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int stm32_sdram_init(void) |
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{ |
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u32 freq; |
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/*
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* Get frequency for NS2CLK calculation. |
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*/ |
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freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; |
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writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
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| SDRAM_CAS << FMC_SDCR_CAS_SHIFT |
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| SDRAM_NB << FMC_SDCR_NB_SHIFT |
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| SDRAM_MWID << FMC_SDCR_MWID_SHIFT |
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| SDRAM_NR << FMC_SDCR_NR_SHIFT |
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| SDRAM_NC << FMC_SDCR_NC_SHIFT |
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| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT |
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| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, |
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&STM32_SDRAM_FMC->sdcr1); |
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writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT |
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| SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
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| SDRAM_TWR << FMC_SDTR_TWR_SHIFT |
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| SDRAM_TRC << FMC_SDTR_TRC_SHIFT |
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| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT |
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| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT |
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| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, |
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&STM32_SDRAM_FMC->sdtr1); |
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writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, |
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&STM32_SDRAM_FMC->sdcmr); |
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udelay(200); /* 200 us delay, page 10, "Power-Up" */ |
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FMC_BUSY_WAIT(); |
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writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, |
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&STM32_SDRAM_FMC->sdcmr); |
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udelay(100); |
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FMC_BUSY_WAIT(); |
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writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH |
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| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); |
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udelay(100); |
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FMC_BUSY_WAIT(); |
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writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
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| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) |
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<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, |
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&STM32_SDRAM_FMC->sdcmr); |
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udelay(100); |
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FMC_BUSY_WAIT(); |
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writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, |
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&STM32_SDRAM_FMC->sdcmr); |
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FMC_BUSY_WAIT(); |
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/* Refresh timer */ |
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writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); |
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return 0; |
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} |
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