Fixup an easy conflict over adding the clk_get prototype and USB_OTG defines for am33xx having moved. Conflicts: arch/arm/include/asm/arch-am33xx/hardware.h Signed-off-by: Tom Rini <trini@ti.com>master
Tom Rini
11 years ago
commit
e20cc2ca15
@ -1,26 +0,0 @@ |
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/* |
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* armboot - Startup Code for OMP2420/ARM1136 CPU-core |
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* |
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* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
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* |
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+
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*/ |
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#include <asm/arch/omap2420.h> |
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.globl reset_cpu
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reset_cpu: |
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ldr r1, rstctl /* get addr for global reset reg */ |
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mov r3, #0x2 /* full reset pll+mpu */ |
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str r3, [r1] /* force reset */ |
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mov r0, r0 |
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_loop_forever: |
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b _loop_forever |
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rstctl: |
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.word PM_RSTCTRL_WKUP
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@ -1,136 +0,0 @@ |
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/*
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* (C) Copyright 2004 |
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* Texas Instruments |
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* Richard Woodruff <r-woodruff2@ti.com> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* Alex Zuepke <azu@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/bits.h> |
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#include <asm/arch/omap2420.h> |
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#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) |
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#define TIMER_LOAD_VAL 0 |
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/* macro to read the 32 bit timer */ |
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#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+TCRR) \ |
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/ (TIMER_CLOCK / CONFIG_SYS_HZ) |
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DECLARE_GLOBAL_DATA_PTR; |
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int timer_init (void) |
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{ |
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int32_t val; |
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/* Start the counter ticking up */ |
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*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ |
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val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ |
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*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ |
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/* reset time */ |
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gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */ |
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gd->arch.tbl = 0; /* start "advancing" time stamp */ |
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return(0); |
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} |
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/*
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* timer without interrupts |
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*/ |
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ulong get_timer (ulong base) |
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{ |
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return get_timer_masked () - base; |
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} |
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/* delay x useconds AND preserve advance timestamp value */ |
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void __udelay (unsigned long usec) |
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{ |
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ulong tmo, tmp; |
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if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ |
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tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ |
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tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ |
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tmo /= 1000; /* finish normalize. */ |
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} else { /* else small number, don't kill it prior to HZ multiply */ |
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tmo = usec * CONFIG_SYS_HZ; |
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tmo /= (1000*1000); |
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} |
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tmp = get_timer (0); /* get current timestamp */ |
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if ((tmo + tmp + 1) < tmp) { /* if setting this forward will roll */ |
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/* time stamp, then reset time */ |
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gd->arch.lastinc = READ_TIMER; /* capture incrementer value */ |
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gd->arch.tbl = 0; /* start time stamp */ |
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} else { |
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tmo += tmp; /* else, set advancing stamp wake up time */ |
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} |
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while (get_timer_masked () < tmo)/* loop till event */ |
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/*NOP*/; |
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} |
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ulong get_timer_masked (void) |
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{ |
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ulong now = READ_TIMER; /* current tick value */ |
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if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ |
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/* move stamp fordward with absoulte diff ticks */ |
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gd->arch.tbl += (now - gd->arch.lastinc); |
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} else { |
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/* we have rollover of incrementer */ |
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gd->arch.tbl += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ)) |
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- gd->arch.lastinc) + now; |
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} |
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gd->arch.lastinc = now; |
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return gd->arch.tbl; |
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} |
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|
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/* waits specified delay value and resets timestamp */ |
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void udelay_masked (unsigned long usec) |
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{ |
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ulong tmo; |
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ulong endtime; |
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signed long diff; |
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if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ |
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tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ |
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tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ |
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tmo /= 1000; /* finish normalize. */ |
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} else { /* else small number, don't kill it prior to HZ multiply */ |
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tmo = usec * CONFIG_SYS_HZ; |
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tmo /= (1000*1000); |
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} |
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endtime = get_timer_masked () + tmo; |
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do { |
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ulong now = get_timer_masked (); |
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diff = endtime - now; |
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} while (diff >= 0); |
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} |
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/*
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* This function is derived from PowerPC code (read timebase as long long). |
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* On ARM it just returns the timer value. |
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*/ |
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unsigned long long get_ticks(void) |
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{ |
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return get_timer(0); |
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} |
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/*
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* This function is derived from PowerPC code (timebase clock frequency). |
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* On ARM it returns the number of timer ticks per second. |
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*/ |
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ulong get_tbclk (void) |
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{ |
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ulong tbclk; |
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tbclk = CONFIG_SYS_HZ; |
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return tbclk; |
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} |
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@ -0,0 +1,171 @@ |
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/*
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* clock.c |
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* |
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* Clock initialization for AM33XX boards. |
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* Derived from OMAP4 boards |
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* |
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/io.h> |
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static void setup_post_dividers(const struct dpll_regs *dpll_regs, |
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const struct dpll_params *params) |
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{ |
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/* Setup post-dividers */ |
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if (params->m2 >= 0) |
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writel(params->m2, dpll_regs->cm_div_m2_dpll); |
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if (params->m3 >= 0) |
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writel(params->m3, dpll_regs->cm_div_m3_dpll); |
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if (params->m4 >= 0) |
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writel(params->m4, dpll_regs->cm_div_m4_dpll); |
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if (params->m5 >= 0) |
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writel(params->m5, dpll_regs->cm_div_m5_dpll); |
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if (params->m6 >= 0) |
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writel(params->m6, dpll_regs->cm_div_m6_dpll); |
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} |
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static inline void do_lock_dpll(const struct dpll_regs *dpll_regs) |
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{ |
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clrsetbits_le32(dpll_regs->cm_clkmode_dpll, |
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CM_CLKMODE_DPLL_DPLL_EN_MASK, |
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DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); |
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} |
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static inline void wait_for_lock(const struct dpll_regs *dpll_regs) |
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{ |
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if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, |
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(void *)dpll_regs->cm_idlest_dpll, LDELAY)) { |
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printf("DPLL locking failed for 0x%x\n", |
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dpll_regs->cm_clkmode_dpll); |
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hang(); |
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} |
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} |
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static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs) |
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{ |
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clrsetbits_le32(dpll_regs->cm_clkmode_dpll, |
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CM_CLKMODE_DPLL_DPLL_EN_MASK, |
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DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT); |
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} |
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static inline void wait_for_bypass(const struct dpll_regs *dpll_regs) |
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{ |
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if (!wait_on_value(ST_DPLL_CLK_MASK, 0, |
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(void *)dpll_regs->cm_idlest_dpll, LDELAY)) { |
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printf("Bypassing DPLL failed 0x%x\n", |
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dpll_regs->cm_clkmode_dpll); |
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} |
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} |
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static void bypass_dpll(const struct dpll_regs *dpll_regs) |
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{ |
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do_bypass_dpll(dpll_regs); |
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wait_for_bypass(dpll_regs); |
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} |
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void do_setup_dpll(const struct dpll_regs *dpll_regs, |
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const struct dpll_params *params) |
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{ |
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u32 temp; |
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if (!params) |
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return; |
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temp = readl(dpll_regs->cm_clksel_dpll); |
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bypass_dpll(dpll_regs); |
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/* Set M & N */ |
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temp &= ~CM_CLKSEL_DPLL_M_MASK; |
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temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; |
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temp &= ~CM_CLKSEL_DPLL_N_MASK; |
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temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; |
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writel(temp, dpll_regs->cm_clksel_dpll); |
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setup_post_dividers(dpll_regs, params); |
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/* Wait till the DPLL locks */ |
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do_lock_dpll(dpll_regs); |
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wait_for_lock(dpll_regs); |
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} |
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static void setup_dplls(void) |
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{ |
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const struct dpll_params *params; |
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do_setup_dpll(&dpll_core_regs, &dpll_core); |
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu); |
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do_setup_dpll(&dpll_per_regs, &dpll_per); |
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writel(0x300, &cmwkup->clkdcoldodpllper); |
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params = get_dpll_ddr_params(); |
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do_setup_dpll(&dpll_ddr_regs, params); |
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} |
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static inline void wait_for_clk_enable(u32 *clkctrl_addr) |
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{ |
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u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; |
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u32 bound = LDELAY; |
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while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || |
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(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { |
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clkctrl = readl(clkctrl_addr); |
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idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> |
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MODULE_CLKCTRL_IDLEST_SHIFT; |
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if (--bound == 0) { |
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printf("Clock enable failed for 0x%p idlest 0x%x\n", |
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clkctrl_addr, clkctrl); |
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return; |
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} |
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} |
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} |
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static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, |
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u32 wait_for_enable) |
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{ |
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clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, |
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enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); |
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debug("Enable clock module - %p\n", clkctrl_addr); |
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if (wait_for_enable) |
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wait_for_clk_enable(clkctrl_addr); |
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} |
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static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) |
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{ |
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clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, |
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enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); |
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debug("Enable clock domain - %p\n", clkctrl_reg); |
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} |
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void do_enable_clocks(u32 *const *clk_domains, |
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u32 *const *clk_modules_explicit_en, u8 wait_for_enable) |
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{ |
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u32 i, max = 100; |
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/* Put the clock domains in SW_WKUP mode */ |
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for (i = 0; (i < max) && clk_domains[i]; i++) { |
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enable_clock_domain(clk_domains[i], |
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CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
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} |
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/* Clock modules that need to be put in SW_EXPLICIT_EN mode */ |
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for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { |
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enable_clock_module(clk_modules_explicit_en[i], |
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, |
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wait_for_enable); |
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}; |
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} |
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void prcm_init() |
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{ |
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enable_basic_clocks(); |
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setup_dplls(); |
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} |
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@ -0,0 +1,110 @@ |
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/*
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* clock_am43xx.c |
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* |
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* clocks for AM43XX based boards |
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* Derived from AM33XX based boards |
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* |
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/io.h> |
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; |
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struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; |
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const struct dpll_regs dpll_mpu_regs = { |
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.cm_clkmode_dpll = CM_WKUP + 0x560, |
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.cm_idlest_dpll = CM_WKUP + 0x564, |
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.cm_clksel_dpll = CM_WKUP + 0x56c, |
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.cm_div_m2_dpll = CM_WKUP + 0x570, |
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}; |
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const struct dpll_regs dpll_core_regs = { |
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.cm_clkmode_dpll = CM_WKUP + 0x520, |
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.cm_idlest_dpll = CM_WKUP + 0x524, |
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.cm_clksel_dpll = CM_WKUP + 0x52C, |
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.cm_div_m4_dpll = CM_WKUP + 0x538, |
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.cm_div_m5_dpll = CM_WKUP + 0x53C, |
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.cm_div_m6_dpll = CM_WKUP + 0x540, |
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}; |
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const struct dpll_regs dpll_per_regs = { |
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.cm_clkmode_dpll = CM_WKUP + 0x5E0, |
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.cm_idlest_dpll = CM_WKUP + 0x5E4, |
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.cm_clksel_dpll = CM_WKUP + 0x5EC, |
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.cm_div_m2_dpll = CM_WKUP + 0x5F0, |
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}; |
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|
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const struct dpll_regs dpll_ddr_regs = { |
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.cm_clkmode_dpll = CM_WKUP + 0x5A0, |
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.cm_idlest_dpll = CM_WKUP + 0x5A4, |
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.cm_clksel_dpll = CM_WKUP + 0x5AC, |
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.cm_div_m2_dpll = CM_WKUP + 0x5B0, |
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}; |
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const struct dpll_params dpll_mpu = { |
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-1, -1, -1, -1, -1, -1, -1}; |
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const struct dpll_params dpll_core = { |
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-1, -1, -1, -1, -1, -1, -1}; |
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const struct dpll_params dpll_per = { |
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-1, -1, -1, -1, -1, -1, -1}; |
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|
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void setup_clocks_for_console(void) |
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{ |
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/* Do not add any spl_debug prints in this function */ |
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clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, |
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CD_CLKCTRL_CLKTRCTRL_SW_WKUP << |
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CD_CLKCTRL_CLKTRCTRL_SHIFT); |
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|
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/* Enable UART0 */ |
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clrsetbits_le32(&cmwkup->wkup_uart0ctrl, |
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MODULE_CLKCTRL_MODULEMODE_MASK, |
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << |
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MODULE_CLKCTRL_MODULEMODE_SHIFT); |
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} |
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|
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void enable_basic_clocks(void) |
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{ |
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u32 *const clk_domains[] = { |
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&cmper->l3clkstctrl, |
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&cmper->l3sclkstctrl, |
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&cmper->l4lsclkstctrl, |
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&cmwkup->wkclkstctrl, |
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&cmper->emifclkstctrl, |
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0 |
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}; |
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|
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u32 *const clk_modules_explicit_en[] = { |
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&cmper->l3clkctrl, |
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&cmper->l4lsclkctrl, |
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&cmper->l4fwclkctrl, |
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&cmwkup->wkl4wkclkctrl, |
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&cmper->l3instrclkctrl, |
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&cmper->l4hsclkctrl, |
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&cmwkup->wkgpio0clkctrl, |
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&cmwkup->wkctrlclkctrl, |
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&cmper->timer2clkctrl, |
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&cmper->gpmcclkctrl, |
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&cmper->elmclkctrl, |
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&cmper->mmc0clkctrl, |
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&cmper->mmc1clkctrl, |
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&cmwkup->wkup_i2c0ctrl, |
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&cmper->gpio1clkctrl, |
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&cmper->gpio2clkctrl, |
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&cmper->gpio3clkctrl, |
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&cmper->i2c1clkctrl, |
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&cmper->emiffwclkctrl, |
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&cmper->emifclkctrl, |
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&cmper->otfaemifclkctrl, |
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0 |
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}; |
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|
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do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); |
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} |
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@ -0,0 +1,445 @@ |
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/*
|
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* clock_ti816x.c |
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* |
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* Clocks for TI816X based boards |
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* |
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
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* Antoine Tenart, <atenart@adeneo-embedded.com> |
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* |
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* Based on TI-PSP-04.00.02.14 : |
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* |
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* Copyright (C) 2009, Texas Instruments, Incorporated |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/ddr_defs.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/io.h> |
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|
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#include <asm/emif.h> |
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|
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#define CM_PLL_BASE (CTRL_BASE + 0x0400) |
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|
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/* Main PLL */ |
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#define MAIN_N 64 |
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#define MAIN_P 0x1 |
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#define MAIN_INTFREQ1 0x8 |
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#define MAIN_FRACFREQ1 0x800000 |
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#define MAIN_MDIV1 0x2 |
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#define MAIN_INTFREQ2 0xE |
||||
#define MAIN_FRACFREQ2 0x0 |
||||
#define MAIN_MDIV2 0x1 |
||||
#define MAIN_INTFREQ3 0x8 |
||||
#define MAIN_FRACFREQ3 0xAAAAB0 |
||||
#define MAIN_MDIV3 0x3 |
||||
#define MAIN_INTFREQ4 0x9 |
||||
#define MAIN_FRACFREQ4 0x55554F |
||||
#define MAIN_MDIV4 0x3 |
||||
#define MAIN_INTFREQ5 0x9 |
||||
#define MAIN_FRACFREQ5 0x374BC6 |
||||
#define MAIN_MDIV5 0xC |
||||
#define MAIN_MDIV6 0x48 |
||||
#define MAIN_MDIV7 0x4 |
||||
|
||||
/* DDR PLL */ |
||||
#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */ |
||||
#define DDR_N 59 |
||||
#define DDR_P 0x1 |
||||
#define DDR_MDIV1 0x4 |
||||
#define DDR_INTFREQ2 0x8 |
||||
#define DDR_FRACFREQ2 0xD99999 |
||||
#define DDR_MDIV2 0x1E |
||||
#define DDR_INTFREQ3 0x8 |
||||
#define DDR_FRACFREQ3 0x0 |
||||
#define DDR_MDIV3 0x4 |
||||
#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ |
||||
#define DDR_FRACFREQ4 0x0 |
||||
#define DDR_MDIV4 0x4 |
||||
#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ |
||||
#define DDR_FRACFREQ5 0x0 |
||||
#define DDR_MDIV5 0x4 |
||||
#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */ |
||||
#define DDR_N 59 |
||||
#define DDR_P 0x1 |
||||
#define DDR_MDIV1 0x3 |
||||
#define DDR_INTFREQ2 0x8 |
||||
#define DDR_FRACFREQ2 0xD99999 |
||||
#define DDR_MDIV2 0x1E |
||||
#define DDR_INTFREQ3 0x8 |
||||
#define DDR_FRACFREQ3 0x0 |
||||
#define DDR_MDIV3 0x4 |
||||
#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ |
||||
#define DDR_FRACFREQ4 0x0 |
||||
#define DDR_MDIV4 0x4 |
||||
#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ |
||||
#define DDR_FRACFREQ5 0x0 |
||||
#define DDR_MDIV5 0x4 |
||||
#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */ |
||||
#define DDR_N 50 |
||||
#define DDR_P 0x1 |
||||
#define DDR_MDIV1 0x2 |
||||
#define DDR_INTFREQ2 0x9 |
||||
#define DDR_FRACFREQ2 0x0 |
||||
#define DDR_MDIV2 0x19 |
||||
#define DDR_INTFREQ3 0x13 |
||||
#define DDR_FRACFREQ3 0x800000 |
||||
#define DDR_MDIV3 0x2 |
||||
#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ |
||||
#define DDR_FRACFREQ4 0x0 |
||||
#define DDR_MDIV4 0x4 |
||||
#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ |
||||
#define DDR_FRACFREQ5 0x0 |
||||
#define DDR_MDIV5 0x4 |
||||
#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */ |
||||
#define DDR_N 59 |
||||
#define DDR_P 0x1 |
||||
#define DDR_MDIV1 0x2 |
||||
#define DDR_INTFREQ2 0x8 |
||||
#define DDR_FRACFREQ2 0xD99999 |
||||
#define DDR_MDIV2 0x1E |
||||
#define DDR_INTFREQ3 0x8 |
||||
#define DDR_FRACFREQ3 0x0 |
||||
#define DDR_MDIV3 0x4 |
||||
#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ |
||||
#define DDR_FRACFREQ4 0x0 |
||||
#define DDR_MDIV4 0x4 |
||||
#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ |
||||
#define DDR_FRACFREQ5 0x0 |
||||
#define DDR_MDIV5 0x4 |
||||
#endif |
||||
|
||||
#define CONTROL_STATUS (CTRL_BASE + 0x40) |
||||
#define DDR_RCD (CTRL_BASE + 0x070C) |
||||
#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) |
||||
#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) |
||||
#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) |
||||
|
||||
#define INTCPS_SYSCONFIG 0x48200010 |
||||
#define CM_SYSCLK10_CLKSEL 0x48180324 |
||||
|
||||
struct cm_pll { |
||||
unsigned int mainpll_ctrl; /* offset 0x400 */ |
||||
unsigned int mainpll_pwd; |
||||
unsigned int mainpll_freq1; |
||||
unsigned int mainpll_div1; |
||||
unsigned int mainpll_freq2; |
||||
unsigned int mainpll_div2; |
||||
unsigned int mainpll_freq3; |
||||
unsigned int mainpll_div3; |
||||
unsigned int mainpll_freq4; |
||||
unsigned int mainpll_div4; |
||||
unsigned int mainpll_freq5; |
||||
unsigned int mainpll_div5; |
||||
unsigned int resv0[1]; |
||||
unsigned int mainpll_div6; |
||||
unsigned int resv1[1]; |
||||
unsigned int mainpll_div7; |
||||
unsigned int ddrpll_ctrl; /* offset 0x440 */ |
||||
unsigned int ddrpll_pwd; |
||||
unsigned int resv2[1]; |
||||
unsigned int ddrpll_div1; |
||||
unsigned int ddrpll_freq2; |
||||
unsigned int ddrpll_div2; |
||||
unsigned int ddrpll_freq3; |
||||
unsigned int ddrpll_div3; |
||||
unsigned int ddrpll_freq4; |
||||
unsigned int ddrpll_div4; |
||||
unsigned int ddrpll_freq5; |
||||
unsigned int ddrpll_div5; |
||||
unsigned int videopll_ctrl; /* offset 0x470 */ |
||||
unsigned int videopll_pwd; |
||||
unsigned int videopll_freq1; |
||||
unsigned int videopll_div1; |
||||
unsigned int videopll_freq2; |
||||
unsigned int videopll_div2; |
||||
unsigned int videopll_freq3; |
||||
unsigned int videopll_div3; |
||||
unsigned int resv3[4]; |
||||
unsigned int audiopll_ctrl; /* offset 0x4A0 */ |
||||
unsigned int audiopll_pwd; |
||||
unsigned int resv4[2]; |
||||
unsigned int audiopll_freq2; |
||||
unsigned int audiopll_div2; |
||||
unsigned int audiopll_freq3; |
||||
unsigned int audiopll_div3; |
||||
unsigned int audiopll_freq4; |
||||
unsigned int audiopll_div4; |
||||
unsigned int audiopll_freq5; |
||||
unsigned int audiopll_div5; |
||||
}; |
||||
|
||||
const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; |
||||
const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; |
||||
const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; |
||||
const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; |
||||
|
||||
void enable_dmm_clocks(void) |
||||
{ |
||||
writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); |
||||
writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); |
||||
writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); |
||||
|
||||
/* Wait for clocks to be active */ |
||||
while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) |
||||
; |
||||
/* Wait for emif0 to be fully functional, including OCP */ |
||||
while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) |
||||
; |
||||
/* Wait for emif1 to be fully functional, including OCP */ |
||||
while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) |
||||
; |
||||
|
||||
writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); |
||||
/* Wait for dmm to be fully functional, including OCP */ |
||||
while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) |
||||
; |
||||
|
||||
/* Enable Tiled Access */ |
||||
writel(0x80000000, DMM_PAT_BASE_ADDR); |
||||
} |
||||
|
||||
/* assume delay is aprox at least 1us */ |
||||
static void ddr_delay(int d) |
||||
{ |
||||
int i; |
||||
|
||||
/*
|
||||
* read a control register. |
||||
* this is a bit more delay and cannot be optimized by the compiler |
||||
* assuming one read takes 200 cycles and A8 is runing 1 GHz |
||||
* somewhat conservative setting |
||||
*/ |
||||
for (i = 0; i < 50*d; i++) |
||||
readl(CONTROL_STATUS); |
||||
} |
||||
|
||||
static void main_pll_init_ti816x(void) |
||||
{ |
||||
u32 main_pll_ctrl = 0; |
||||
|
||||
/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ |
||||
main_pll_ctrl = readl(&cmpll->mainpll_ctrl); |
||||
main_pll_ctrl &= 0xFFFFFFFB; |
||||
main_pll_ctrl |= BIT(2); |
||||
writel(main_pll_ctrl, &cmpll->mainpll_ctrl); |
||||
|
||||
/* Enable PLL by setting BIT3 in its ctrl reg */ |
||||
main_pll_ctrl = readl(&cmpll->mainpll_ctrl); |
||||
main_pll_ctrl &= 0xFFFFFFF7; |
||||
main_pll_ctrl |= BIT(3); |
||||
writel(main_pll_ctrl, &cmpll->mainpll_ctrl); |
||||
|
||||
/* Write the values of N,P in the CTRL reg */ |
||||
main_pll_ctrl = readl(&cmpll->mainpll_ctrl); |
||||
main_pll_ctrl &= 0xFF; |
||||
main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); |
||||
writel(main_pll_ctrl, &cmpll->mainpll_ctrl); |
||||
|
||||
/* Power up clock1-7 */ |
||||
writel(0x0, &cmpll->mainpll_pwd); |
||||
|
||||
/* Program the freq and divider values for clock1-7 */ |
||||
writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), |
||||
&cmpll->mainpll_freq1); |
||||
writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); |
||||
|
||||
writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), |
||||
&cmpll->mainpll_freq2); |
||||
writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); |
||||
|
||||
writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), |
||||
&cmpll->mainpll_freq3); |
||||
writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); |
||||
|
||||
writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), |
||||
&cmpll->mainpll_freq4); |
||||
writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); |
||||
|
||||
writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), |
||||
&cmpll->mainpll_freq5); |
||||
writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); |
||||
|
||||
writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); |
||||
|
||||
writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); |
||||
|
||||
/* Wait for PLL to lock */ |
||||
while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) |
||||
; |
||||
|
||||
/* Put the PLL in normal mode, disable bypass */ |
||||
main_pll_ctrl = readl(&cmpll->mainpll_ctrl); |
||||
main_pll_ctrl &= 0xFFFFFFFB; |
||||
writel(main_pll_ctrl, &cmpll->mainpll_ctrl); |
||||
} |
||||
|
||||
static void ddr_pll_bypass_ti816x(void) |
||||
{ |
||||
u32 ddr_pll_ctrl = 0; |
||||
|
||||
/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ |
||||
ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); |
||||
ddr_pll_ctrl &= 0xFFFFFFFB; |
||||
ddr_pll_ctrl |= BIT(2); |
||||
writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); |
||||
} |
||||
|
||||
static void ddr_pll_init_ti816x(void) |
||||
{ |
||||
u32 ddr_pll_ctrl = 0; |
||||
/* Enable PLL by setting BIT3 in its ctrl reg */ |
||||
ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); |
||||
ddr_pll_ctrl &= 0xFFFFFFF7; |
||||
ddr_pll_ctrl |= BIT(3); |
||||
writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); |
||||
|
||||
/* Write the values of N,P in the CTRL reg */ |
||||
ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); |
||||
ddr_pll_ctrl &= 0xFF; |
||||
ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); |
||||
writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); |
||||
|
||||
ddr_delay(10); |
||||
|
||||
/* Power up clock1-5 */ |
||||
writel(0x0, &cmpll->ddrpll_pwd); |
||||
|
||||
/* Program the freq and divider values for clock1-3 */ |
||||
writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); |
||||
ddr_delay(1); |
||||
writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); |
||||
writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), |
||||
&cmpll->ddrpll_freq2); |
||||
writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); |
||||
writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); |
||||
ddr_delay(1); |
||||
writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); |
||||
ddr_delay(1); |
||||
writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), |
||||
&cmpll->ddrpll_freq3); |
||||
ddr_delay(1); |
||||
writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), |
||||
&cmpll->ddrpll_freq3); |
||||
|
||||
ddr_delay(5); |
||||
|
||||
/* Wait for PLL to lock */ |
||||
while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) |
||||
; |
||||
|
||||
/* Power up RCD */ |
||||
writel(BIT(0), DDR_RCD); |
||||
} |
||||
|
||||
static void peripheral_enable(void) |
||||
{ |
||||
/* Wake-up the l3_slow clock */ |
||||
writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); |
||||
|
||||
/*
|
||||
* Note on Timers: |
||||
* There are 8 timers(0-7) out of which timer 0 is a secure timer. |
||||
* Timer 0 mux should not be changed |
||||
* |
||||
* To access the timer registers we need the to be |
||||
* enabled which is what we do in the first step |
||||
*/ |
||||
|
||||
/* Enable timer1 */ |
||||
writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); |
||||
/* Select timer1 clock to be CLKIN (27MHz) */ |
||||
writel(BIT(1), CM_TIMER1_CLKSEL); |
||||
|
||||
/* Wait for timer1 to be ON-ACTIVE */ |
||||
while (((readl(&cmalwon->l3slowclkstctrl) |
||||
& (0x80000<<1))>>20) != 1) |
||||
; |
||||
/* Wait for timer1 to be enabled */ |
||||
while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) |
||||
; |
||||
/* Active posted mode */ |
||||
writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); |
||||
while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) |
||||
; |
||||
/* Start timer1 */ |
||||
writel(BIT(0), (DM_TIMER1_BASE + 0x38)); |
||||
|
||||
/* eFuse */ |
||||
writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); |
||||
while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) |
||||
; |
||||
|
||||
/* Enable gpio0 */ |
||||
writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); |
||||
while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) |
||||
; |
||||
writel((BIT(8)), &cmalwon->gpio0clkctrl); |
||||
|
||||
/* Enable spi */ |
||||
writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); |
||||
while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) |
||||
; |
||||
|
||||
/* Enable i2c0 */ |
||||
writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); |
||||
while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) |
||||
; |
||||
|
||||
/* Enable ethernet0 */ |
||||
writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); |
||||
writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); |
||||
writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); |
||||
|
||||
/* Enable hsmmc */ |
||||
writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); |
||||
while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) |
||||
; |
||||
} |
||||
|
||||
void setup_clocks_for_console(void) |
||||
{ |
||||
/* Fix ROM code bug - from TI-PSP-04.00.02.14 */ |
||||
writel(0x0, CM_SYSCLK10_CLKSEL); |
||||
|
||||
ddr_pll_bypass_ti816x(); |
||||
|
||||
/* Enable uart0-2 */ |
||||
writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); |
||||
while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) |
||||
; |
||||
writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); |
||||
while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) |
||||
; |
||||
writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); |
||||
while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) |
||||
; |
||||
while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) |
||||
; |
||||
} |
||||
|
||||
void prcm_init(void) |
||||
{ |
||||
/* Enable the control */ |
||||
writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); |
||||
|
||||
main_pll_init_ti816x(); |
||||
ddr_pll_init_ti816x(); |
||||
|
||||
/*
|
||||
* With clk freqs setup to desired values, |
||||
* enable the required peripherals |
||||
*/ |
||||
peripheral_enable(); |
||||
} |
||||
@ -0,0 +1,142 @@ |
||||
/*
|
||||
* ti81xx.h |
||||
* |
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
||||
* Antoine Tenart, <atenart@adeneo-embedded.com> |
||||
* |
||||
* This file is released under the terms of GPL v2 and any later version. |
||||
* See the file COPYING in the root directory of the source tree for details. |
||||
*/ |
||||
|
||||
#ifndef _CLOCK_TI81XX_H_ |
||||
#define _CLOCK_TI81XX_H_ |
||||
|
||||
#define PRCM_MOD_EN 0x2 |
||||
|
||||
#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) |
||||
#define CM_ALWON_BASE (PRCM_BASE + 0x1400) |
||||
|
||||
struct cm_def { |
||||
unsigned int resv0[2]; |
||||
unsigned int l3fastclkstctrl; |
||||
unsigned int resv1[1]; |
||||
unsigned int pciclkstctrl; |
||||
unsigned int resv2[1]; |
||||
unsigned int ducaticlkstctrl; |
||||
unsigned int resv3[1]; |
||||
unsigned int emif0clkctrl; |
||||
unsigned int emif1clkctrl; |
||||
unsigned int dmmclkctrl; |
||||
unsigned int fwclkctrl; |
||||
unsigned int resv4[10]; |
||||
unsigned int usbclkctrl; |
||||
unsigned int resv5[1]; |
||||
unsigned int sataclkctrl; |
||||
unsigned int resv6[4]; |
||||
unsigned int ducaticlkctrl; |
||||
unsigned int pciclkctrl; |
||||
}; |
||||
|
||||
struct cm_alwon { |
||||
unsigned int l3slowclkstctrl; |
||||
unsigned int ethclkstctrl; |
||||
unsigned int l3medclkstctrl; |
||||
unsigned int mmu_clkstctrl; |
||||
unsigned int mmucfg_clkstctrl; |
||||
unsigned int ocmc0clkstctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int vcpclkstctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int ocmc1clkstctrl; |
||||
#endif |
||||
unsigned int mpuclkstctrl; |
||||
unsigned int sysclk4clkstctrl; |
||||
unsigned int sysclk5clkstctrl; |
||||
unsigned int sysclk6clkstctrl; |
||||
unsigned int rtcclkstctrl; |
||||
unsigned int l3fastclkstctrl; |
||||
unsigned int resv0[67]; |
||||
unsigned int mcasp0clkctrl; |
||||
unsigned int mcasp1clkctrl; |
||||
unsigned int mcasp2clkctrl; |
||||
unsigned int mcbspclkctrl; |
||||
unsigned int uart0clkctrl; |
||||
unsigned int uart1clkctrl; |
||||
unsigned int uart2clkctrl; |
||||
unsigned int gpio0clkctrl; |
||||
unsigned int gpio1clkctrl; |
||||
unsigned int i2c0clkctrl; |
||||
unsigned int i2c1clkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int mcasp345clkctrl; |
||||
unsigned int atlclkctrl; |
||||
unsigned int mlbclkctrl; |
||||
unsigned int pataclkctrl; |
||||
unsigned int resv1[1]; |
||||
unsigned int uart3clkctrl; |
||||
unsigned int uart4clkctrl; |
||||
unsigned int uart5clkctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int resv1[1]; |
||||
unsigned int timer1clkctrl; |
||||
unsigned int timer2clkctrl; |
||||
unsigned int timer3clkctrl; |
||||
unsigned int timer4clkctrl; |
||||
unsigned int timer5clkctrl; |
||||
unsigned int timer6clkctrl; |
||||
unsigned int timer7clkctrl; |
||||
#endif |
||||
unsigned int wdtimerclkctrl; |
||||
unsigned int spiclkctrl; |
||||
unsigned int mailboxclkctrl; |
||||
unsigned int spinboxclkctrl; |
||||
unsigned int mmudataclkctrl; |
||||
unsigned int resv2[2]; |
||||
unsigned int mmucfgclkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int resv3[2]; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int resv3[1]; |
||||
unsigned int sdioclkctrl; |
||||
#endif |
||||
unsigned int ocmc0clkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int vcpclkctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int ocmc1clkctrl; |
||||
#endif |
||||
unsigned int resv4[2]; |
||||
unsigned int controlclkctrl; |
||||
unsigned int resv5[2]; |
||||
unsigned int gpmcclkctrl; |
||||
unsigned int ethernet0clkctrl; |
||||
unsigned int ethernet1clkctrl; |
||||
unsigned int mpuclkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int debugssclkctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int resv6[1]; |
||||
#endif |
||||
unsigned int l3clkctrl; |
||||
unsigned int l4hsclkctrl; |
||||
unsigned int l4lsclkctrl; |
||||
unsigned int rtcclkctrl; |
||||
unsigned int tpccclkctrl; |
||||
unsigned int tptc0clkctrl; |
||||
unsigned int tptc1clkctrl; |
||||
unsigned int tptc2clkctrl; |
||||
unsigned int tptc3clkctrl; |
||||
#if defined(CONFIG_TI814X) |
||||
unsigned int resv6[4]; |
||||
unsigned int dcan01clkctrl; |
||||
unsigned int mmchs0clkctrl; |
||||
unsigned int mmchs1clkctrl; |
||||
unsigned int mmchs2clkctrl; |
||||
unsigned int custefuseclkctrl; |
||||
#elif defined(CONFIG_TI816X) |
||||
unsigned int sr0clkctrl; |
||||
unsigned int sr1clkctrl; |
||||
#endif |
||||
}; |
||||
|
||||
#endif /* _CLOCK_TI81XX_H_ */ |
||||
@ -0,0 +1,54 @@ |
||||
/*
|
||||
* hardware_am43xx.h |
||||
* |
||||
* AM43xx hardware specific header |
||||
* |
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __AM43XX_HARDWARE_AM43XX_H |
||||
#define __AM43XX_HARDWARE_AM43XX_H |
||||
|
||||
/* Module base addresses */ |
||||
|
||||
/* UART Base Address */ |
||||
#define UART0_BASE 0x44E09000 |
||||
|
||||
/* GPIO Base address */ |
||||
#define GPIO2_BASE 0x481AC000 |
||||
|
||||
/* Watchdog Timer */ |
||||
#define WDT_BASE 0x44E35000 |
||||
|
||||
/* Control Module Base Address */ |
||||
#define CTRL_BASE 0x44E10000 |
||||
#define CTRL_DEVICE_BASE 0x44E10600 |
||||
|
||||
/* PRCM Base Address */ |
||||
#define PRCM_BASE 0x44DF0000 |
||||
#define CM_WKUP 0x44DF2800 |
||||
#define CM_PER 0x44DF8800 |
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x4000) |
||||
#define PRM_RSTST (PRM_RSTCTRL + 4) |
||||
|
||||
/* VTP Base address */ |
||||
#define VTP0_CTRL_ADDR 0x44E10E0C |
||||
#define VTP1_CTRL_ADDR 0x48140E10 |
||||
|
||||
/* DDR Base address */ |
||||
#define DDR_PHY_CMD_ADDR 0x44E12000 |
||||
#define DDR_PHY_DATA_ADDR 0x44E120C8 |
||||
#define DDR_PHY_CMD_ADDR2 0x47C0C800 |
||||
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 |
||||
#define DDR_DATA_REGS_NR 2 |
||||
|
||||
/* CPSW Config space */ |
||||
#define CPSW_MDIO_BASE 0x4A101000 |
||||
|
||||
/* RTC base address */ |
||||
#define RTC_BASE 0x44E3E000 |
||||
|
||||
#endif /* __AM43XX_HARDWARE_AM43XX_H */ |
||||
@ -0,0 +1,61 @@ |
||||
/*
|
||||
* hardware_ti816x.h |
||||
* |
||||
* TI816x hardware specific header |
||||
* |
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
||||
* Antoine Tenart, <atenart@adeneo-embedded.com> |
||||
* Based on TI-PSP-04.00.02.14 |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef __AM33XX_HARDWARE_TI816X_H |
||||
#define __AM33XX_HARDWARE_TI816X_H |
||||
|
||||
/* UART */ |
||||
#define UART0_BASE 0x48020000 |
||||
#define UART1_BASE 0x48022000 |
||||
#define UART2_BASE 0x48024000 |
||||
|
||||
/* Watchdog Timer */ |
||||
#define WDT_BASE 0x480C2000 |
||||
|
||||
/* Control Module Base Address */ |
||||
#define CTRL_BASE 0x48140000 |
||||
|
||||
/* PRCM Base Address */ |
||||
#define PRCM_BASE 0x48180000 |
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) |
||||
#define PRM_RSTST (PRM_RSTCTRL + 8) |
||||
|
||||
/* VTP Base address */ |
||||
#define VTP0_CTRL_ADDR 0x48198358 |
||||
#define VTP1_CTRL_ADDR 0x4819A358 |
||||
|
||||
/* DDR Base address */ |
||||
#define DDR_PHY_CMD_ADDR 0x48198000 |
||||
#define DDR_PHY_DATA_ADDR 0x481980C8 |
||||
#define DDR_PHY_CMD_ADDR2 0x4819A000 |
||||
#define DDR_PHY_DATA_ADDR2 0x4819A0C8 |
||||
#define DDR_DATA_REGS_NR 4 |
||||
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE 0x48198000 |
||||
#define DDRPHY_1_CONFIG_BASE 0x4819A000 |
||||
#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ |
||||
DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) |
||||
|
||||
/* RTC base address */ |
||||
#define RTC_BASE 0x480C0000 |
||||
|
||||
#endif /* __AM33XX_HARDWARE_TI816X_H */ |
||||
@ -0,0 +1,142 @@ |
||||
/*
|
||||
* mux_am43xx.h |
||||
* |
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _MUX_AM43XX_H_ |
||||
#define _MUX_AM43XX_H_ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define MUX_CFG(value, offset) \ |
||||
__raw_writel(value, (CTRL_BASE + offset)); |
||||
|
||||
/* PAD Control Fields */ |
||||
#define SLEWCTRL (0x1 << 19) |
||||
#define RXACTIVE (0x1 << 18) |
||||
#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ |
||||
#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ |
||||
#define PULLUDEN (0x0 << 16) /* Pull up/down enable */ |
||||
#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */ |
||||
#define MODE(val) val /* used for Readability */ |
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS |
||||
* Field names corresponds to the pad signal name |
||||
*/ |
||||
struct pad_signals { |
||||
int gpmc_ad0; |
||||
int gpmc_ad1; |
||||
int gpmc_ad2; |
||||
int gpmc_ad3; |
||||
int gpmc_ad4; |
||||
int gpmc_ad5; |
||||
int gpmc_ad6; |
||||
int gpmc_ad7; |
||||
int gpmc_ad8; |
||||
int gpmc_ad9; |
||||
int gpmc_ad10; |
||||
int gpmc_ad11; |
||||
int gpmc_ad12; |
||||
int gpmc_ad13; |
||||
int gpmc_ad14; |
||||
int gpmc_ad15; |
||||
int gpmc_a0; |
||||
int gpmc_a1; |
||||
int gpmc_a2; |
||||
int gpmc_a3; |
||||
int gpmc_a4; |
||||
int gpmc_a5; |
||||
int gpmc_a6; |
||||
int gpmc_a7; |
||||
int gpmc_a8; |
||||
int gpmc_a9; |
||||
int gpmc_a10; |
||||
int gpmc_a11; |
||||
int gpmc_wait0; |
||||
int gpmc_wpn; |
||||
int gpmc_be1n; |
||||
int gpmc_csn0; |
||||
int gpmc_csn1; |
||||
int gpmc_csn2; |
||||
int gpmc_csn3; |
||||
int gpmc_clk; |
||||
int gpmc_advn_ale; |
||||
int gpmc_oen_ren; |
||||
int gpmc_wen; |
||||
int gpmc_be0n_cle; |
||||
int lcd_data0; |
||||
int lcd_data1; |
||||
int lcd_data2; |
||||
int lcd_data3; |
||||
int lcd_data4; |
||||
int lcd_data5; |
||||
int lcd_data6; |
||||
int lcd_data7; |
||||
int lcd_data8; |
||||
int lcd_data9; |
||||
int lcd_data10; |
||||
int lcd_data11; |
||||
int lcd_data12; |
||||
int lcd_data13; |
||||
int lcd_data14; |
||||
int lcd_data15; |
||||
int lcd_vsync; |
||||
int lcd_hsync; |
||||
int lcd_pclk; |
||||
int lcd_ac_bias_en; |
||||
int mmc0_dat3; |
||||
int mmc0_dat2; |
||||
int mmc0_dat1; |
||||
int mmc0_dat0; |
||||
int mmc0_clk; |
||||
int mmc0_cmd; |
||||
int mii1_col; |
||||
int mii1_crs; |
||||
int mii1_rxerr; |
||||
int mii1_txen; |
||||
int mii1_rxdv; |
||||
int mii1_txd3; |
||||
int mii1_txd2; |
||||
int mii1_txd1; |
||||
int mii1_txd0; |
||||
int mii1_txclk; |
||||
int mii1_rxclk; |
||||
int mii1_rxd3; |
||||
int mii1_rxd2; |
||||
int mii1_rxd1; |
||||
int mii1_rxd0; |
||||
int rmii1_refclk; |
||||
int mdio_data; |
||||
int mdio_clk; |
||||
int spi0_sclk; |
||||
int spi0_d0; |
||||
int spi0_d1; |
||||
int spi0_cs0; |
||||
int spi0_cs1; |
||||
int ecap0_in_pwm0_out; |
||||
int uart0_ctsn; |
||||
int uart0_rtsn; |
||||
int uart0_rxd; |
||||
int uart0_txd; |
||||
int uart1_ctsn; |
||||
int uart1_rtsn; |
||||
int uart1_rxd; |
||||
int uart1_txd; |
||||
int i2c0_sda; |
||||
int i2c0_scl; |
||||
int mcasp0_aclkx; |
||||
int mcasp0_fsx; |
||||
int mcasp0_axr0; |
||||
int mcasp0_ahclkr; |
||||
int mcasp0_aclkr; |
||||
int mcasp0_fsr; |
||||
int mcasp0_axr1; |
||||
int mcasp0_ahclkx; |
||||
}; |
||||
|
||||
#endif /* _MUX_AM43XX_H_ */ |
||||
@ -0,0 +1,363 @@ |
||||
/*
|
||||
* mux_ti816x.h |
||||
* |
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
||||
* Antoine Tenart, <atenart@adeneo-embedded.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation version 2. |
||||
* |
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
||||
* kind, whether express or implied; without even the implied warranty |
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef _MUX_TI816X_H_ |
||||
#define _MUX_TI816X_H_ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define MUX_CFG(value, offset) \ |
||||
__raw_writel(value, (CTRL_BASE + offset)); |
||||
|
||||
#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ |
||||
#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ |
||||
#define PULLUDEN (0x0 << 3) /* Pull up enabled */ |
||||
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ |
||||
#define MODE(val) (val) /* used for Readability */ |
||||
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS |
||||
* Field names corresponds to the pad signal name |
||||
*/ |
||||
struct pad_signals { |
||||
int pincntl1; |
||||
int pincntl2; |
||||
int pincntl3; |
||||
int pincntl4; |
||||
int pincntl5; |
||||
int pincntl6; |
||||
int pincntl7; |
||||
int pincntl8; |
||||
int pincntl9; |
||||
int pincntl10; |
||||
int pincntl11; |
||||
int pincntl12; |
||||
int pincntl13; |
||||
int pincntl14; |
||||
int pincntl15; |
||||
int pincntl16; |
||||
int pincntl17; |
||||
int pincntl18; |
||||
int pincntl19; |
||||
int pincntl20; |
||||
int pincntl21; |
||||
int pincntl22; |
||||
int pincntl23; |
||||
int pincntl24; |
||||
int pincntl25; |
||||
int pincntl26; |
||||
int pincntl27; |
||||
int pincntl28; |
||||
int pincntl29; |
||||
int pincntl30; |
||||
int pincntl31; |
||||
int pincntl32; |
||||
int pincntl33; |
||||
int pincntl34; |
||||
int pincntl35; |
||||
int pincntl36; |
||||
int pincntl37; |
||||
int pincntl38; |
||||
int pincntl39; |
||||
int pincntl40; |
||||
int pincntl41; |
||||
int pincntl42; |
||||
int pincntl43; |
||||
int pincntl44; |
||||
int pincntl45; |
||||
int pincntl46; |
||||
int pincntl47; |
||||
int pincntl48; |
||||
int pincntl49; |
||||
int pincntl50; |
||||
int pincntl51; |
||||
int pincntl52; |
||||
int pincntl53; |
||||
int pincntl54; |
||||
int pincntl55; |
||||
int pincntl56; |
||||
int pincntl57; |
||||
int pincntl58; |
||||
int pincntl59; |
||||
int pincntl60; |
||||
int pincntl61; |
||||
int pincntl62; |
||||
int pincntl63; |
||||
int pincntl64; |
||||
int pincntl65; |
||||
int pincntl66; |
||||
int pincntl67; |
||||
int pincntl68; |
||||
int pincntl69; |
||||
int pincntl70; |
||||
int pincntl71; |
||||
int pincntl72; |
||||
int pincntl73; |
||||
int pincntl74; |
||||
int pincntl75; |
||||
int pincntl76; |
||||
int pincntl77; |
||||
int pincntl78; |
||||
int pincntl79; |
||||
int pincntl80; |
||||
int pincntl81; |
||||
int pincntl82; |
||||
int pincntl83; |
||||
int pincntl84; |
||||
int pincntl85; |
||||
int pincntl86; |
||||
int pincntl87; |
||||
int pincntl88; |
||||
int pincntl89; |
||||
int pincntl90; |
||||
int pincntl91; |
||||
int pincntl92; |
||||
int pincntl93; |
||||
int pincntl94; |
||||
int pincntl95; |
||||
int pincntl96; |
||||
int pincntl97; |
||||
int pincntl98; |
||||
int pincntl99; |
||||
int pincntl100; |
||||
int pincntl101; |
||||
int pincntl102; |
||||
int pincntl103; |
||||
int pincntl104; |
||||
int pincntl105; |
||||
int pincntl106; |
||||
int pincntl107; |
||||
int pincntl108; |
||||
int pincntl109; |
||||
int pincntl110; |
||||
int pincntl111; |
||||
int pincntl112; |
||||
int pincntl113; |
||||
int pincntl114; |
||||
int pincntl115; |
||||
int pincntl116; |
||||
int pincntl117; |
||||
int pincntl118; |
||||
int pincntl119; |
||||
int pincntl120; |
||||
int pincntl121; |
||||
int pincntl122; |
||||
int pincntl123; |
||||
int pincntl124; |
||||
int pincntl125; |
||||
int pincntl126; |
||||
int pincntl127; |
||||
int pincntl128; |
||||
int pincntl129; |
||||
int pincntl130; |
||||
int pincntl131; |
||||
int pincntl132; |
||||
int pincntl133; |
||||
int pincntl134; |
||||
int pincntl135; |
||||
int pincntl136; |
||||
int pincntl137; |
||||
int pincntl138; |
||||
int pincntl139; |
||||
int pincntl140; |
||||
int pincntl141; |
||||
int pincntl142; |
||||
int pincntl143; |
||||
int pincntl144; |
||||
int pincntl145; |
||||
int pincntl146; |
||||
int pincntl147; |
||||
int pincntl148; |
||||
int pincntl149; |
||||
int pincntl150; |
||||
int pincntl151; |
||||
int pincntl152; |
||||
int pincntl153; |
||||
int pincntl154; |
||||
int pincntl155; |
||||
int pincntl156; |
||||
int pincntl157; |
||||
int pincntl158; |
||||
int pincntl159; |
||||
int pincntl160; |
||||
int pincntl161; |
||||
int pincntl162; |
||||
int pincntl163; |
||||
int pincntl164; |
||||
int pincntl165; |
||||
int pincntl166; |
||||
int pincntl167; |
||||
int pincntl168; |
||||
int pincntl169; |
||||
int pincntl170; |
||||
int pincntl171; |
||||
int pincntl172; |
||||
int pincntl173; |
||||
int pincntl174; |
||||
int pincntl175; |
||||
int pincntl176; |
||||
int pincntl177; |
||||
int pincntl178; |
||||
int pincntl179; |
||||
int pincntl180; |
||||
int pincntl181; |
||||
int pincntl182; |
||||
int pincntl183; |
||||
int pincntl184; |
||||
int pincntl185; |
||||
int pincntl186; |
||||
int pincntl187; |
||||
int pincntl188; |
||||
int pincntl189; |
||||
int pincntl190; |
||||
int pincntl191; |
||||
int pincntl192; |
||||
int pincntl193; |
||||
int pincntl194; |
||||
int pincntl195; |
||||
int pincntl196; |
||||
int pincntl197; |
||||
int pincntl198; |
||||
int pincntl199; |
||||
int pincntl200; |
||||
int pincntl201; |
||||
int pincntl202; |
||||
int pincntl203; |
||||
int pincntl204; |
||||
int pincntl205; |
||||
int pincntl206; |
||||
int pincntl207; |
||||
int pincntl208; |
||||
int pincntl209; |
||||
int pincntl210; |
||||
int pincntl211; |
||||
int pincntl212; |
||||
int pincntl213; |
||||
int pincntl214; |
||||
int pincntl215; |
||||
int pincntl216; |
||||
int pincntl217; |
||||
int pincntl218; |
||||
int pincntl219; |
||||
int pincntl220; |
||||
int pincntl221; |
||||
int pincntl222; |
||||
int pincntl223; |
||||
int pincntl224; |
||||
int pincntl225; |
||||
int pincntl226; |
||||
int pincntl227; |
||||
int pincntl228; |
||||
int pincntl229; |
||||
int pincntl230; |
||||
int pincntl231; |
||||
int pincntl232; |
||||
int pincntl233; |
||||
int pincntl234; |
||||
int pincntl235; |
||||
int pincntl236; |
||||
int pincntl237; |
||||
int pincntl238; |
||||
int pincntl239; |
||||
int pincntl240; |
||||
int pincntl241; |
||||
int pincntl242; |
||||
int pincntl243; |
||||
int pincntl244; |
||||
int pincntl245; |
||||
int pincntl246; |
||||
int pincntl247; |
||||
int pincntl248; |
||||
int pincntl249; |
||||
int pincntl250; |
||||
int pincntl251; |
||||
int pincntl252; |
||||
int pincntl253; |
||||
int pincntl254; |
||||
int pincntl255; |
||||
int pincntl256; |
||||
int pincntl257; |
||||
int pincntl258; |
||||
int pincntl259; |
||||
int pincntl260; |
||||
int pincntl261; |
||||
int pincntl262; |
||||
int pincntl263; |
||||
int pincntl264; |
||||
int pincntl265; |
||||
int pincntl266; |
||||
int pincntl267; |
||||
int pincntl268; |
||||
int pincntl269; |
||||
int pincntl270; |
||||
int pincntl271; |
||||
int pincntl272; |
||||
int pincntl273; |
||||
int pincntl274; |
||||
int pincntl275; |
||||
int pincntl276; |
||||
int pincntl277; |
||||
int pincntl278; |
||||
int pincntl279; |
||||
int pincntl280; |
||||
int pincntl281; |
||||
int pincntl282; |
||||
int pincntl283; |
||||
int pincntl284; |
||||
int pincntl285; |
||||
int pincntl286; |
||||
int pincntl287; |
||||
int pincntl288; |
||||
int pincntl289; |
||||
int pincntl290; |
||||
int pincntl291; |
||||
int pincntl292; |
||||
int pincntl293; |
||||
int pincntl294; |
||||
int pincntl295; |
||||
int pincntl296; |
||||
int pincntl297; |
||||
int pincntl298; |
||||
int pincntl299; |
||||
int pincntl300; |
||||
int pincntl301; |
||||
int pincntl302; |
||||
int pincntl303; |
||||
int pincntl304; |
||||
int pincntl305; |
||||
int pincntl306; |
||||
int pincntl307; |
||||
int pincntl308; |
||||
int pincntl309; |
||||
int pincntl310; |
||||
int pincntl311; |
||||
int pincntl312; |
||||
int pincntl313; |
||||
int pincntl314; |
||||
int pincntl315; |
||||
int pincntl316; |
||||
int pincntl317; |
||||
int pincntl318; |
||||
int pincntl319; |
||||
int pincntl320; |
||||
int pincntl321; |
||||
int pincntl322; |
||||
int pincntl323; |
||||
}; |
||||
|
||||
#endif /* endif _MUX_TI816X_H_ */ |
||||
@ -1,29 +1,27 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
SOBJS = reset.o
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = timer.o
|
||||
COBJS += ipam390.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
all: $(obj).depend $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
# This is for $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
@ -0,0 +1,229 @@ |
||||
Summary |
||||
======= |
||||
The README is for the boot procedure on the ipam390 board |
||||
|
||||
In the context of U-Boot, the board is booted in three stages. The initial |
||||
bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits |
||||
in the internal ROM. The RBL initializes the internal memory and then |
||||
depending on the exact board and pin configurations will initialize another |
||||
controller (such as NAND) to continue the boot process by loading |
||||
the secondary program loader (SPL). The SPL will initialize the system |
||||
further (some clocks, SDRAM). As on this board is used the falcon boot |
||||
mode, now 2 ways are possible depending on the GPIO 7_14 input pin, |
||||
connected with the "soft reset switch" |
||||
|
||||
If this pin is logical 1 (high level): |
||||
spl code starts the kernel image without delay |
||||
|
||||
If this pin is logical 0 (low level): |
||||
spl code starts the u-boot image |
||||
|
||||
AIS is an image format defined by TI for the images that are to be loaded |
||||
to memory by the RBL. The image is divided into a series of sections and |
||||
the image's entry point is specified. Each section comes with meta data |
||||
like the target address the section is to be copied to and the size of the |
||||
section, which is used by the RBL to load the image. At the end of the |
||||
image the RBL jumps to the image entry point. The AIS format allows for |
||||
other things such as programming the clocks and SDRAM if the header is |
||||
programmed for it. We do not take advantage of this and instead use SPL as |
||||
it allows for additional flexibility (run-time detect of board revision, |
||||
loading the next image from a different media, etc). |
||||
|
||||
Compilation |
||||
=========== |
||||
run "./MAKEALL ipam390" in the u-boot source tree. |
||||
Once this build completes you will have a u-boot.ais file that needs to |
||||
be written to the nand flash. |
||||
|
||||
Flashing the images to NAND |
||||
========================== |
||||
The AIS image can be written to NAND flash using the following commands. |
||||
Assuming that the network is configured and enabled and the u-boot.ais file |
||||
is tftp'able. |
||||
|
||||
U-Boot > print upd_uboot |
||||
upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize} |
||||
U-Boot > |
||||
U-Boot > run upd_uboot |
||||
Using DaVinci-EMAC device |
||||
TFTP from server 192.168.1.1; our IP address is 192.168.20.71 |
||||
Filename '/tftpboot/ipam390/u-boot.ais'. |
||||
Load address: 0xc0000000 |
||||
Loading: ################################## |
||||
1.5 MiB/s |
||||
done |
||||
Bytes transferred = 493716 (78894 hex) |
||||
|
||||
NAND erase.part: device 0 offset 0x20000, size 0x160000 |
||||
Erasing at 0x160000 -- 100% complete. |
||||
OK |
||||
|
||||
NAND write: device 0 offset 0x20000, size 0x78894 |
||||
493716 bytes written: OK |
||||
U-Boot > |
||||
|
||||
Recovery |
||||
======== |
||||
|
||||
In the case of a "bricked" board, you need to use the TI tools found |
||||
here[1] to create an uboot-uart-ais.bin file |
||||
|
||||
- cd to the u-boot source tree |
||||
|
||||
- compile the u-boot for the ipam390 board: |
||||
$ ./MAKEALL ipam390 |
||||
|
||||
-> Now we shall have u-boot.bin |
||||
|
||||
- Create u-boot-uart-ais.bin |
||||
$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini |
||||
ipam390-ais-uart.cfg -o ./uboot-uart-ais.bin ./u-boot.bin@0xC1080000; |
||||
|
||||
Note: The ipam390-ais-uart.cfg is found in the board directory |
||||
for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg |
||||
|
||||
- We can now run bootloader on IPAM390 via UART using the command below: |
||||
|
||||
$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin |
||||
NOTE: Do not cancel the command execution! The command takes 20+ seconds |
||||
to upload u-boot over serial and run it! |
||||
Outcome: |
||||
Waiting for the OMAP-L138... |
||||
(AIS Parse): Read magic word 0x41504954. |
||||
(AIS Parse): Waiting for BOOTME... (power on or reset target now) |
||||
(AIS Parse): BOOTME received! |
||||
(AIS Parse): Performing Start-Word Sync... |
||||
(AIS Parse): Performing Ping Opcode Sync... |
||||
(AIS Parse): Processing command 0: 0x5853590D. |
||||
(AIS Parse): Performing Opcode Sync... |
||||
(AIS Parse): Executing function... |
||||
(AIS Parse): Processing command 1: 0x5853590D. |
||||
(AIS Parse): Performing Opcode Sync... |
||||
(AIS Parse): Executing function... |
||||
(AIS Parse): Processing command 2: 0x5853590D. |
||||
(AIS Parse): Performing Opcode Sync... |
||||
(AIS Parse): Executing function... |
||||
(AIS Parse): Processing command 3: 0x5853590D. |
||||
(AIS Parse): Performing Opcode Sync... |
||||
(AIS Parse): Executing function... |
||||
(AIS Parse): Processing command 4: 0x5853590D. |
||||
(AIS Parse): Performing Opcode Sync... |
||||
(AIS Parse): Executing function... |
||||
(AIS Parse): Processing command 5: 0x58535901. |
||||
(AIS Parse): Performing Opcode Sync... |
||||
(AIS Parse): Loading section... |
||||
(AIS Parse): Loaded 326516-Byte section to address 0xC1080000. |
||||
(AIS Parse): Processing command 6: 0x58535906. |
||||
(AIS Parse): Performing Opcode Sync... |
||||
(AIS Parse): Performing jump and close... |
||||
(AIS Parse): AIS complete. Jump to address 0xC1080000. |
||||
(AIS Parse): Waiting for DONE... |
||||
(AIS Parse): Boot completed successfully. |
||||
|
||||
Operation completed successfully. |
||||
|
||||
Falcon Bootmode (boot linux without booting U-Boot) |
||||
=================================================== |
||||
|
||||
The Falcon Mode extends this way allowing to start the Linux kernel directly |
||||
from SPL. A new command is added to U-Boot to prepare the parameters that SPL |
||||
must pass to the kernel, using ATAGS or Device Tree. |
||||
|
||||
In normal mode, these parameters are generated each time before |
||||
loading the kernel, passing to Linux the address in memory where |
||||
the parameters can be read. |
||||
With Falcon Mode, this snapshot can be saved into persistent storage and SPL is |
||||
informed to load it before running the kernel. |
||||
|
||||
To boot the kernel, these steps under a Falcon-aware U-Boot are required: |
||||
|
||||
1. Boot the board into U-Boot. |
||||
Use the "spl export" command to generate the kernel parameters area or the DT. |
||||
U-Boot runs as when it boots the kernel, but stops before passing the control |
||||
to the kernel. |
||||
|
||||
Here the command sequence for the ipam390 board: |
||||
- load the linux kernel image into ram: |
||||
|
||||
U-Boot > nand read c0100000 2 200000 400000 |
||||
|
||||
NAND read: device 0 offset 0x200000, size 0x400000 |
||||
4194304 bytes read: OK |
||||
|
||||
- generate the bootparms image: |
||||
|
||||
U-Boot > spl export atags c0100000 |
||||
## Booting kernel from Legacy Image at c0100000 ... |
||||
Image Name: Linux-3.5.1 |
||||
Image Type: ARM Linux Kernel Image (uncompressed) |
||||
Data Size: 2504280 Bytes = 2.4 MiB |
||||
Load Address: c0008000 |
||||
Entry Point: c0008000 |
||||
Verifying Checksum ... OK |
||||
Loading Kernel Image ... OK |
||||
subcommand not supported |
||||
subcommand not supported |
||||
Argument image is now in RAM at: 0xc0000100 |
||||
|
||||
- copy the bootparms image into nand: |
||||
|
||||
U-Boot > mtdparts |
||||
|
||||
device nand0 <davinci_nand.0>, # parts = 6 |
||||
#: name size offset mask_flags |
||||
0: u-boot-env 0x00020000 0x00000000 0 |
||||
1: u-boot 0x00160000 0x00020000 0 |
||||
2: bootparms 0x00020000 0x00180000 0 |
||||
3: factory-info 0x00060000 0x001a0000 0 |
||||
4: kernel 0x00400000 0x00200000 0 |
||||
5: rootfs 0x07a00000 0x00600000 0 |
||||
|
||||
active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000 |
||||
|
||||
defaults: |
||||
mtdids : nand0=davinci_nand.0 |
||||
mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs) |
||||
U-Boot > nand erase.part bootparms |
||||
|
||||
NAND erase.part: device 0 offset 0x180000, size 0x20000 |
||||
Erasing at 0x180000 -- 100% complete. |
||||
OK |
||||
U-Boot > nand write c0000100 180000 20000 |
||||
|
||||
NAND write: device 0 offset 0x180000, size 0x20000 |
||||
131072 bytes written: OK |
||||
U-Boot > |
||||
|
||||
You can use also the predefined U-Boot Environment variable "setbootparms", |
||||
which will do all the above steps in one command: |
||||
|
||||
U-Boot > print setbootparms |
||||
setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000 |
||||
U-Boot > run setbootparms |
||||
|
||||
NAND read: device 0 offset 0x200000, size 0x400000 |
||||
4194304 bytes read: OK |
||||
## Booting kernel from Legacy Image at c0100000 ... |
||||
Image Name: Linux-3.5.1 |
||||
Image Type: ARM Linux Kernel Image (uncompressed) |
||||
Data Size: 2504280 Bytes = 2.4 MiB |
||||
Load Address: c0008000 |
||||
Entry Point: c0008000 |
||||
Verifying Checksum ... OK |
||||
Loading Kernel Image ... OK |
||||
subcommand not supported |
||||
subcommand not supported |
||||
Argument image is now in RAM at: 0xc0000100 |
||||
|
||||
NAND erase.part: device 0 offset 0x180000, size 0x20000 |
||||
Erasing at 0x180000 -- 100% complete. |
||||
OK |
||||
|
||||
NAND write: device 0 offset 0x180000, size 0x20000 |
||||
131072 bytes written: OK |
||||
U-Boot > |
||||
|
||||
Links |
||||
===== |
||||
[1] |
||||
http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/ |
||||
@ -0,0 +1,202 @@ |
||||
; General settings that can be overwritten in the host code |
||||
; that calls the AISGen library. |
||||
[General] |
||||
|
||||
; Can be 8 or 16 - used in emifa |
||||
busWidth=8 |
||||
|
||||
; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW |
||||
BootMode=UART |
||||
|
||||
; 8,16,24 - used for SPI,I2C |
||||
;AddrWidth=8 |
||||
|
||||
; NO_CRC,SECTION_CRC,SINGLE_CRC |
||||
crcCheckType=NO_CRC |
||||
|
||||
; This section allows setting the PLL0 system clock with a |
||||
; specified multiplier and divider as shown. The clock source |
||||
; can also be chosen for internal or external. |
||||
; |------24|------16|-------8|-------0| |
||||
; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV| |
||||
; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7| |
||||
;[PLL0CONFIG] |
||||
;PLL0CFG0 = 0x00180001 |
||||
;PLL0CFG1 = 0x00000205 |
||||
|
||||
[PLLANDCLOCKCONFIG] |
||||
PLL0CFG0 = 0x00180001 |
||||
PLL0CFG1 = 0x00000205 |
||||
PERIPHCLKCFG = 0x00000051 |
||||
|
||||
; This section allows setting up the PLL1. Usually this will |
||||
; take place as part of the EMIF3a DDR setup. The format of |
||||
; the input args is as follows: |
||||
; |------24|------16|-------8|-------0| |
||||
; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| |
||||
; PLL1CFG1: | RSVD | PLLDIV3| |
||||
[PLL1CONFIG] |
||||
PLL1CFG0 = 0x18010001 |
||||
PLL1CFG1 = 0x00000002 |
||||
|
||||
; This section lets us configure the peripheral interface |
||||
; of the current booting peripheral (I2C, SPI, or UART). |
||||
; Use with caution. The format of the PERIPHCLKCFG field |
||||
; is as follows: |
||||
; SPI: |------24|------16|-------8|-------0| |
||||
; | RSVD |PRESCALE| |
||||
; |
||||
; I2C: |------24|------16|-------8|-------0| |
||||
; | RSVD |PRESCALE| CLKL | CLKH | |
||||
; |
||||
; UART: |------24|------16|-------8|-------0| |
||||
; | RSVD | OSR | DLH | DLL | |
||||
[PERIPHCLKCFG] |
||||
PERIPHCLKCFG = 0x00000051 |
||||
|
||||
; This section can be used to configure the PLL1 and the EMIF3a registers |
||||
; for starting the DDR2 interface. |
||||
; See PLL1CONFIG section for the format of the PLL1CFG fields. |
||||
; |------24|------16|-------8|-------0| |
||||
; PLL1CFG0: | PLL1CFG | |
||||
; PLL1CFG1: | PLL1CFG | |
||||
; DDRPHYC1R: | DDRPHYC1R | |
||||
; SDCR: | SDCR | |
||||
; SDTIMR: | SDTIMR | |
||||
; SDTIMR2: | SDTIMR2 | |
||||
; SDRCR: | SDRCR | |
||||
; CLK2XSRC: | CLK2XSRC | |
||||
[EMIF3DDR] |
||||
PLL1CFG0 = 0x18010001 |
||||
PLL1CFG1 = 0x00000002 |
||||
DDRPHYC1R = 0x000000C2 |
||||
SDCR = 0x0017C432 |
||||
SDTIMR = 0x26922A09 |
||||
SDTIMR2 = 0x4414C722 |
||||
SDRCR = 0x00000498 |
||||
CLK2XSRC = 0x00000000 |
||||
|
||||
; This section can be used to configure the EMIFA to use |
||||
; CS0 as an SDRAM interface. The fields required to do this |
||||
; are given below. |
||||
; |------24|------16|-------8|-------0| |
||||
; SDBCR: | SDBCR | |
||||
; SDTIMR: | SDTIMR | |
||||
; SDRSRPDEXIT: | SDRSRPDEXIT | |
||||
; SDRCR: | SDRCR | |
||||
; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE | |
||||
;[EMIF25SDRAM] |
||||
;SDBCR = 0x00004421 |
||||
;SDTIMR = 0x42215810 |
||||
;SDRSRPDEXIT = 0x00000009 |
||||
;SDRCR = 0x00000410 |
||||
;DIV4p5_CLK_ENABLE = 0x00000001 |
||||
|
||||
; This section can be used to configure the async chip selects |
||||
; of the EMIFA (CS2-CS5). The fields required to do this |
||||
; are given below. |
||||
; |------24|------16|-------8|-------0| |
||||
; A1CR: | A1CR | |
||||
; A2CR: | A2CR | |
||||
; A3CR: | A3CR | |
||||
; A4CR: | A4CR | |
||||
; NANDFCR: | NANDFCR | |
||||
;[EMIF25ASYNC] |
||||
;A1CR = 0x00000000 |
||||
;A2CR = 0x00000000 |
||||
;A3CR = 0x00000000 |
||||
;A4CR = 0x00000000 |
||||
;NANDFCR = 0x00000000 |
||||
[EMIF25ASYNC] |
||||
A1CR = 0x00000000 |
||||
A2CR = 0x3FFFFFFE |
||||
A3CR = 0x00000000 |
||||
A4CR = 0x00000000 |
||||
NANDFCR = 0x00000012 |
||||
|
||||
; This section should be used in place of PLL0CONFIG when |
||||
; the I2C, SPI, or UART modes are being used. This ensures that |
||||
; the system PLL and the peripheral's clocks are changed together. |
||||
; See PLL0CONFIG section for the format of the PLL0CFG fields. |
||||
; See PERIPHCLKCFG section for the format of the CLKCFG field. |
||||
; |------24|------16|-------8|-------0| |
||||
; PLL0CFG0: | PLL0CFG | |
||||
; PLL0CFG1: | PLL0CFG | |
||||
; PERIPHCLKCFG: | CLKCFG | |
||||
;[PLLANDCLOCKCONFIG] |
||||
;PLL0CFG0 = 0x00180001 |
||||
;PLL0CFG1 = 0x00000205 |
||||
;PERIPHCLKCFG = 0x00010032 |
||||
|
||||
; This section should be used to setup the power state of modules |
||||
; of the two PSCs. This section can be included multiple times to |
||||
; allow the configuration of any or all of the device modules. |
||||
; |------24|------16|-------8|-------0| |
||||
; LPSCCFG: | PSCNUM | MODULE | PD | STATE | |
||||
;[PSCCONFIG] |
||||
;LPSCCFG= |
||||
|
||||
; This section allows setting of a single PINMUX register. |
||||
; This section can be included multiple times to allow setting |
||||
; as many PINMUX registers as needed. |
||||
; |------24|------16|-------8|-------0| |
||||
; REGNUM: | regNum | |
||||
; MASK: | mask | |
||||
; VALUE: | value | |
||||
;[PINMUX] |
||||
;REGNUM = 5 |
||||
;MASK = 0x00FF0000 |
||||
;VALUE = 0x00880000 |
||||
|
||||
; No Params required - simply include this section for the fast boot |
||||
; function to be called |
||||
;[FASTBOOT] |
||||
|
||||
; This section allows setting up the PLL1. Usually this will |
||||
; take place as part of the EMIF3a DDR setup. The format of |
||||
; the input args is as follows: |
||||
; |------24|------16|-------8|-------0| |
||||
; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| |
||||
; PLL1CFG1: | RSVD | PLLDIV3| |
||||
;[PLL1CONFIG] |
||||
;PLL1CFG0 = 0x15010001 |
||||
;PLL1CFG1 = 0x00000002 |
||||
|
||||
; This section can be used to configure the PLL1 and the EMIF3a registers |
||||
; for starting the DDR2 interface on ARM-boot D800K002 devices. |
||||
; |------24|------16|-------8|-------0| |
||||
; DDRPHYC1R: | DDRPHYC1R | |
||||
; SDCR: | SDCR | |
||||
; SDTIMR: | SDTIMR | |
||||
; SDTIMR2: | SDTIMR2 | |
||||
; SDRCR: | SDRCR | |
||||
; CLK2XSRC: | CLK2XSRC | |
||||
;[ARM_EMIF3DDR_PATCHFXN] |
||||
;DDRPHYC1R = 0x000000C2 |
||||
;SDCR = 0x0017C432 |
||||
;SDTIMR = 0x26922A09 |
||||
;SDTIMR2 = 0x4414C722 |
||||
;SDRCR = 0x00000498 |
||||
;CLK2XSRC = 0x00000000 |
||||
|
||||
; This section can be used to configure the PLL1 and the EMIF3a registers |
||||
; for starting the DDR2 interface on DSP-boot D800K002 devices. |
||||
; |------24|------16|-------8|-------0| |
||||
; DDRPHYC1R: | DDRPHYC1R | |
||||
; SDCR: | SDCR | |
||||
; SDTIMR: | SDTIMR | |
||||
; SDTIMR2: | SDTIMR2 | |
||||
; SDRCR: | SDRCR | |
||||
; CLK2XSRC: | CLK2XSRC | |
||||
;[DSP_EMIF3DDR_PATCHFXN] |
||||
;DDRPHYC1R = 0x000000C4 |
||||
;SDCR = 0x08134632 |
||||
;SDTIMR = 0x26922A09 |
||||
;SDTIMR2 = 0x0014C722 |
||||
;SDRCR = 0x00000492 |
||||
;CLK2XSRC = 0x00000000 |
||||
|
||||
;[INPUTFILE] |
||||
;FILENAME=u-boot.bin |
||||
;LOADADDRESS=0xC1080000 |
||||
;ENTRYPOINTADDRESS=0xC1080000 |
||||
@ -0,0 +1,348 @@ |
||||
/*
|
||||
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
||||
* Based on: |
||||
* U-Boot:board/davinci/da8xxevm/da850evm.c |
||||
* |
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* |
||||
* Based on da830evm.c. Original Copyrights follow: |
||||
* |
||||
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <net.h> |
||||
#include <netdev.h> |
||||
#include <spi.h> |
||||
#include <spi_flash.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/emif_defs.h> |
||||
#include <asm/arch/emac_defs.h> |
||||
#include <asm/arch/pinmux_defs.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/davinci_misc.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/gpio.h> |
||||
#include <hwconfig.h> |
||||
#include <bootstage.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII |
||||
#define HAS_RMII 1 |
||||
#else |
||||
#define HAS_RMII 0 |
||||
#endif |
||||
#endif /* CONFIG_DRIVER_TI_EMAC */ |
||||
|
||||
void dsp_lpsc_on(unsigned domain, unsigned int id) |
||||
{ |
||||
dv_reg_p mdstat, mdctl, ptstat, ptcmd; |
||||
struct davinci_psc_regs *psc_regs; |
||||
|
||||
psc_regs = davinci_psc0_regs; |
||||
mdstat = &psc_regs->psc0.mdstat[id]; |
||||
mdctl = &psc_regs->psc0.mdctl[id]; |
||||
ptstat = &psc_regs->ptstat; |
||||
ptcmd = &psc_regs->ptcmd; |
||||
|
||||
while (*ptstat & (0x1 << domain)) |
||||
; |
||||
|
||||
if ((*mdstat & 0x1f) == 0x03) |
||||
return; /* Already on and enabled */ |
||||
|
||||
*mdctl |= 0x03; |
||||
|
||||
*ptcmd = 0x1 << domain; |
||||
|
||||
while (*ptstat & (0x1 << domain)) |
||||
; |
||||
while ((*mdstat & 0x1f) != 0x03) |
||||
; /* Probably an overkill... */ |
||||
} |
||||
|
||||
static void dspwake(void) |
||||
{ |
||||
unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; |
||||
u32 val; |
||||
|
||||
/* if the device is ARM only, return */ |
||||
if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) |
||||
return; |
||||
|
||||
if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) |
||||
return; |
||||
|
||||
*resetvect++ = 0x1E000; /* DSP Idle */ |
||||
/* clear out the next 10 words as NOP */ |
||||
memset(resetvect, 0, sizeof(unsigned) * 10); |
||||
|
||||
/* setup the DSP reset vector */ |
||||
writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); |
||||
|
||||
dsp_lpsc_on(1, DAVINCI_LPSC_GEM); |
||||
val = readl(PSC0_MDCTL + (15 * 4)); |
||||
val |= 0x100; |
||||
writel(val, (PSC0_MDCTL + (15 * 4))); |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
dspwake(); |
||||
return 0; |
||||
} |
||||
|
||||
static const struct pinmux_config gpio_pins[] = { |
||||
/* GP7[14] selects bootmode*/ |
||||
{ pinmux(16), 8, 3 }, /* GP7[14] */ |
||||
}; |
||||
|
||||
const struct pinmux_resource pinmuxes[] = { |
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
PINMUX_ITEM(emac_pins_mdio), |
||||
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII |
||||
PINMUX_ITEM(emac_pins_rmii), |
||||
#else |
||||
PINMUX_ITEM(emac_pins_mii), |
||||
#endif |
||||
#endif |
||||
PINMUX_ITEM(uart2_pins_txrx), |
||||
PINMUX_ITEM(uart2_pins_rtscts), |
||||
PINMUX_ITEM(uart0_pins_txrx), |
||||
PINMUX_ITEM(uart0_pins_rtscts), |
||||
#ifdef CONFIG_NAND_DAVINCI |
||||
PINMUX_ITEM(emifa_pins_cs3), |
||||
PINMUX_ITEM(emifa_pins_nand), |
||||
#endif |
||||
PINMUX_ITEM(gpio_pins), |
||||
}; |
||||
|
||||
const int pinmuxes_size = ARRAY_SIZE(pinmuxes); |
||||
|
||||
const struct lpsc_resource lpsc[] = { |
||||
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ |
||||
{ DAVINCI_LPSC_EMAC }, /* image download */ |
||||
{ DAVINCI_LPSC_UART2 }, /* console */ |
||||
{ DAVINCI_LPSC_UART0 }, /* console */ |
||||
{ DAVINCI_LPSC_GPIO }, |
||||
}; |
||||
|
||||
const int lpsc_size = ARRAY_SIZE(lpsc); |
||||
|
||||
#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK |
||||
#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 |
||||
#endif |
||||
|
||||
#define REV_AM18X_EVM 0x100 |
||||
|
||||
/*
|
||||
* get_board_rev() - setup to pass kernel board revision information |
||||
* Returns: |
||||
* bit[0-3] Maximum cpu clock rate supported by onboard SoC |
||||
* 0000b - 300 MHz |
||||
* 0001b - 372 MHz |
||||
* 0010b - 408 MHz |
||||
* 0011b - 456 MHz |
||||
*/ |
||||
u32 get_board_rev(void) |
||||
{ |
||||
char *s; |
||||
u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; |
||||
u32 rev = 0; |
||||
|
||||
s = getenv("maxcpuclk"); |
||||
if (s) |
||||
maxcpuclk = simple_strtoul(s, NULL, 10); |
||||
|
||||
if (maxcpuclk >= 456000000) |
||||
rev = 3; |
||||
else if (maxcpuclk >= 408000000) |
||||
rev = 2; |
||||
else if (maxcpuclk >= 372000000) |
||||
rev = 1; |
||||
#ifdef CONFIG_DA850_AM18X_EVM |
||||
rev |= REV_AM18X_EVM; |
||||
#endif |
||||
return rev; |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
/*
|
||||
* Power on required peripherals |
||||
* ARM does not have access by default to PSC0 and PSC1 |
||||
* assuming here that the DSP bootloader has set the IOPU |
||||
* such that PSC access is available to ARM |
||||
*/ |
||||
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
#ifndef CONFIG_USE_IRQ |
||||
irq_init(); |
||||
#endif |
||||
|
||||
/* arch number of the board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; |
||||
|
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
||||
|
||||
/* setup the SUSPSRC for ARM to control emulation suspend */ |
||||
writel(readl(&davinci_syscfg_regs->suspsrc) & |
||||
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | |
||||
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | |
||||
DAVINCI_SYSCFG_SUSPSRC_UART0), |
||||
&davinci_syscfg_regs->suspsrc); |
||||
|
||||
/* configure pinmux settings */ |
||||
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) |
||||
return 1; |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
davinci_emac_mii_mode_sel(HAS_RMII); |
||||
#endif /* CONFIG_DRIVER_TI_EMAC */ |
||||
|
||||
/* enable the console UART */ |
||||
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | |
||||
DAVINCI_UART_PWREMU_MGMT_UTRST), |
||||
#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) |
||||
&davinci_uart0_ctrl_regs->pwremu_mgmt); |
||||
#else |
||||
&davinci_uart2_ctrl_regs->pwremu_mgmt); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
/*
|
||||
* Initializes on-board ethernet controllers. |
||||
*/ |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
if (!davinci_emac_initialize()) { |
||||
printf("Error: Ethernet init failed!\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_DRIVER_TI_EMAC */ |
||||
|
||||
static int init_led(int gpio, char *name, int val) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = gpio_request(gpio, name); |
||||
if (ret) |
||||
return -1; |
||||
ret = gpio_direction_output(gpio, val); |
||||
if (ret) |
||||
return -1; |
||||
|
||||
return gpio; |
||||
} |
||||
|
||||
#define LED_ON 0 |
||||
#define LED_OFF 1 |
||||
|
||||
#if !defined(CONFIG_SPL_BUILD) |
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS |
||||
void show_boot_progress(int status) |
||||
{ |
||||
static int red; |
||||
static int green; |
||||
|
||||
if (red == 0) |
||||
red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); |
||||
if (red != CONFIG_IPAM390_GPIO_LED_RED) |
||||
return; |
||||
if (green == 0) |
||||
green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", |
||||
LED_OFF); |
||||
if (green != CONFIG_IPAM390_GPIO_LED_GREEN) |
||||
return; |
||||
|
||||
switch (status) { |
||||
case BOOTSTAGE_ID_RUN_OS: |
||||
/*
|
||||
* set normal state |
||||
* LED Red : off |
||||
* LED green: off |
||||
*/ |
||||
gpio_set_value(red, LED_OFF); |
||||
gpio_set_value(green, LED_OFF); |
||||
break; |
||||
case BOOTSTAGE_ID_MAIN_LOOP: |
||||
/*
|
||||
* U-Boot operation |
||||
* LED Red : on |
||||
* LED green: on |
||||
*/ |
||||
gpio_set_value(red, LED_ON); |
||||
gpio_set_value(green, LED_ON); |
||||
break; |
||||
} |
||||
} |
||||
#endif |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT |
||||
int spl_start_uboot(void) |
||||
{ |
||||
int ret; |
||||
int bootmode = 0; |
||||
|
||||
/*
|
||||
* GP7[14] selects bootmode: |
||||
* 1: boot linux |
||||
* 0: boot u-boot |
||||
* if error accessing gpio boot U-Boot |
||||
* |
||||
* SPL bootmode |
||||
* 0: boot linux |
||||
* 1: boot u-boot |
||||
*/ |
||||
ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode"); |
||||
if (ret) |
||||
bootmode = 1; |
||||
if (!bootmode) { |
||||
ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE); |
||||
if (ret) |
||||
bootmode = 1; |
||||
} |
||||
if (!bootmode) |
||||
ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE); |
||||
if (!bootmode) |
||||
if (ret == 0) |
||||
bootmode = 1; |
||||
if (bootmode) { |
||||
/*
|
||||
* Booting U-Boot |
||||
* LED Red : on |
||||
* LED green: off |
||||
*/ |
||||
init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); |
||||
init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); |
||||
} else { |
||||
/*
|
||||
* Booting Linux |
||||
* LED Red : off |
||||
* LED green: off |
||||
*/ |
||||
init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); |
||||
init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); |
||||
} |
||||
return bootmode; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,53 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
||||
* |
||||
* (C) Copyright 2008 |
||||
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ |
||||
LENGTH = CONFIG_SPL_MAX_FOOTPRINT } |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
__start = .; |
||||
arch/arm/cpu/arm926ejs/start.o (.text*) |
||||
*(.text*) |
||||
} >.sram |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram |
||||
|
||||
. = ALIGN(4); |
||||
.rel.dyn : { |
||||
__rel_dyn_start = .; |
||||
*(.rel*) |
||||
__rel_dyn_end = .; |
||||
} >.sram |
||||
|
||||
.bss : |
||||
{ |
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
*(.bss*) |
||||
. = ALIGN(4); |
||||
__bss_end = .; |
||||
} >.sram |
||||
|
||||
__image_copy_end = .; |
||||
_end = .; |
||||
} |
||||
@ -1,28 +0,0 @@ |
||||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2011 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := mx6qsabrelite.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -1,832 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6q_pins.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <asm/imx-common/mxc_i2c.h> |
||||
#include <asm/imx-common/boot_mode.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <malloc.h> |
||||
#include <micrel.h> |
||||
#include <miiphy.h> |
||||
#include <netdev.h> |
||||
#include <linux/fb.h> |
||||
#include <ipu_pixfmt.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/mxc_hdmi.h> |
||||
#include <i2c.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
||||
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ |
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
||||
|
||||
#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
iomux_v3_cfg_t const uart1_pads[] = { |
||||
MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const uart2_pads[] = { |
||||
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
||||
|
||||
/* I2C1, SGTL5000 */ |
||||
struct i2c_pads_info i2c_pad_info0 = { |
||||
.scl = { |
||||
.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, |
||||
.gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, |
||||
.gp = IMX_GPIO_NR(3, 21) |
||||
}, |
||||
.sda = { |
||||
.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, |
||||
.gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, |
||||
.gp = IMX_GPIO_NR(3, 28) |
||||
} |
||||
}; |
||||
|
||||
/* I2C2 Camera, MIPI */ |
||||
struct i2c_pads_info i2c_pad_info1 = { |
||||
.scl = { |
||||
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, |
||||
.gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, |
||||
.gp = IMX_GPIO_NR(4, 12) |
||||
}, |
||||
.sda = { |
||||
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, |
||||
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, |
||||
.gp = IMX_GPIO_NR(4, 13) |
||||
} |
||||
}; |
||||
|
||||
/* I2C3, J15 - RGB connector */ |
||||
struct i2c_pads_info i2c_pad_info2 = { |
||||
.scl = { |
||||
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, |
||||
.gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, |
||||
.gp = IMX_GPIO_NR(1, 5) |
||||
}, |
||||
.sda = { |
||||
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, |
||||
.gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, |
||||
.gp = IMX_GPIO_NR(7, 11) |
||||
} |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = { |
||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const usdhc4_pads[] = { |
||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const enet_pads1[] = { |
||||
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
/* pin 35 - 1 (PHY_AD2) on reset */ |
||||
MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 32 - 1 - (MODE0) all */ |
||||
MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 31 - 1 - (MODE1) all */ |
||||
MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 28 - 1 - (MODE2) all */ |
||||
MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 27 - 1 - (MODE3) all */ |
||||
MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ |
||||
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 42 PHY nRST */ |
||||
MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const enet_pads2[] = { |
||||
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
}; |
||||
|
||||
/* Button assignments for J14 */ |
||||
static iomux_v3_cfg_t const button_pads[] = { |
||||
/* Menu */ |
||||
MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
||||
/* Back */ |
||||
MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
||||
/* Labelled Search (mapped to Power under Android) */ |
||||
MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
||||
/* Home */ |
||||
MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
||||
/* Volume Down */ |
||||
MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
||||
/* Volume Up */ |
||||
MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
||||
}; |
||||
|
||||
static void setup_iomux_enet(void) |
||||
{ |
||||
gpio_direction_output(IMX_GPIO_NR(3, 23), 0); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 30), 1); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 25), 1); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 27), 1); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 28), 1); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 29), 1); |
||||
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 24), 1); |
||||
|
||||
/* Need delay 10ms according to KSZ9021 spec */ |
||||
udelay(1000 * 10); |
||||
gpio_set_value(IMX_GPIO_NR(3, 23), 1); |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); |
||||
} |
||||
|
||||
iomux_v3_cfg_t const usb_pads[] = { |
||||
MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
static void setup_iomux_uart(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
||||
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
||||
} |
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6 |
||||
int board_ehci_hcd_init(int port) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); |
||||
|
||||
/* Reset USB hub */ |
||||
gpio_direction_output(IMX_GPIO_NR(7, 12), 0); |
||||
mdelay(2); |
||||
gpio_set_value(IMX_GPIO_NR(7, 12), 1); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
struct fsl_esdhc_cfg usdhc_cfg[2] = { |
||||
{USDHC3_BASE_ADDR}, |
||||
{USDHC4_BASE_ADDR}, |
||||
}; |
||||
|
||||
int board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
int ret; |
||||
|
||||
if (cfg->esdhc_base == USDHC3_BASE_ADDR) { |
||||
gpio_direction_input(IMX_GPIO_NR(7, 0)); |
||||
ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); |
||||
} else { |
||||
gpio_direction_input(IMX_GPIO_NR(2, 6)); |
||||
ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
s32 status = 0; |
||||
u32 index = 0; |
||||
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
||||
|
||||
usdhc_cfg[0].max_bus_width = 4; |
||||
usdhc_cfg[1].max_bus_width = 4; |
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { |
||||
switch (index) { |
||||
case 0: |
||||
imx_iomux_v3_setup_multiple_pads( |
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
||||
break; |
||||
case 1: |
||||
imx_iomux_v3_setup_multiple_pads( |
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
||||
break; |
||||
default: |
||||
printf("Warning: you configured more USDHC controllers" |
||||
"(%d) then supported by the board (%d)\n", |
||||
index + 1, CONFIG_SYS_FSL_USDHC_NUM); |
||||
return status; |
||||
} |
||||
|
||||
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); |
||||
} |
||||
|
||||
return status; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MXC_SPI |
||||
iomux_v3_cfg_t const ecspi1_pads[] = { |
||||
/* SS1 */ |
||||
MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), |
||||
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
||||
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
||||
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
||||
}; |
||||
|
||||
void setup_spi(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, |
||||
ARRAY_SIZE(ecspi1_pads)); |
||||
} |
||||
#endif |
||||
|
||||
int board_phy_config(struct phy_device *phydev) |
||||
{ |
||||
/* min rx data delay */ |
||||
ksz9021_phy_extended_write(phydev, |
||||
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); |
||||
/* min tx data delay */ |
||||
ksz9021_phy_extended_write(phydev, |
||||
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); |
||||
/* max rx/tx clock delay, min rx/tx control */ |
||||
ksz9021_phy_extended_write(phydev, |
||||
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); |
||||
if (phydev->drv->config) |
||||
phydev->drv->config(phydev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
uint32_t base = IMX_FEC_BASE; |
||||
struct mii_dev *bus = NULL; |
||||
struct phy_device *phydev = NULL; |
||||
int ret; |
||||
|
||||
setup_iomux_enet(); |
||||
|
||||
#ifdef CONFIG_FEC_MXC |
||||
bus = fec_get_miibus(base, -1); |
||||
if (!bus) |
||||
return 0; |
||||
/* scan phy 4,5,6,7 */ |
||||
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); |
||||
if (!phydev) { |
||||
free(bus); |
||||
return 0; |
||||
} |
||||
printf("using phy at %d\n", phydev->addr); |
||||
ret = fec_probe(bis, -1, base, bus, phydev); |
||||
if (ret) { |
||||
printf("FEC MXC: %s:failed\n", __func__); |
||||
free(phydev); |
||||
free(bus); |
||||
} |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
static void setup_buttons(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(button_pads, |
||||
ARRAY_SIZE(button_pads)); |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_SATA |
||||
|
||||
int setup_sata(void) |
||||
{ |
||||
struct iomuxc_base_regs *const iomuxc_regs |
||||
= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; |
||||
int ret = enable_sata_clock(); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
clrsetbits_le32(&iomuxc_regs->gpr[13], |
||||
IOMUXC_GPR13_SATA_MASK, |
||||
IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB |
||||
|IOMUXC_GPR13_SATA_PHY_7_SATA2M |
||||
|IOMUXC_GPR13_SATA_SPEED_3G |
||||
|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) |
||||
|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED |
||||
|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 |
||||
|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB |
||||
|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V |
||||
|IOMUXC_GPR13_SATA_PHY_1_SLOW); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3) |
||||
|
||||
static iomux_v3_cfg_t const backlight_pads[] = { |
||||
/* Backlight on RGB connector: J15 */ |
||||
MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) |
||||
|
||||
/* Backlight on LVDS connector: J6 */ |
||||
MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const rgb_pads[] = { |
||||
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, |
||||
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, |
||||
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, |
||||
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, |
||||
MX6_PAD_DI0_PIN4__GPIO_4_20, |
||||
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, |
||||
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, |
||||
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, |
||||
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, |
||||
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, |
||||
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, |
||||
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, |
||||
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, |
||||
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, |
||||
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, |
||||
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, |
||||
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, |
||||
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, |
||||
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, |
||||
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, |
||||
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, |
||||
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, |
||||
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, |
||||
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, |
||||
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, |
||||
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, |
||||
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, |
||||
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, |
||||
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, |
||||
}; |
||||
|
||||
struct display_info_t { |
||||
int bus; |
||||
int addr; |
||||
int pixfmt; |
||||
int (*detect)(struct display_info_t const *dev); |
||||
void (*enable)(struct display_info_t const *dev); |
||||
struct fb_videomode mode; |
||||
}; |
||||
|
||||
|
||||
static int detect_hdmi(struct display_info_t const *dev) |
||||
{ |
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
||||
return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; |
||||
} |
||||
|
||||
static void enable_hdmi(struct display_info_t const *dev) |
||||
{ |
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
||||
u8 reg; |
||||
printf("%s: setup HDMI monitor\n", __func__); |
||||
reg = readb(&hdmi->phy_conf0); |
||||
reg |= HDMI_PHY_CONF0_PDZ_MASK; |
||||
writeb(reg, &hdmi->phy_conf0); |
||||
|
||||
udelay(3000); |
||||
reg |= HDMI_PHY_CONF0_ENTMDS_MASK; |
||||
writeb(reg, &hdmi->phy_conf0); |
||||
udelay(3000); |
||||
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; |
||||
writeb(reg, &hdmi->phy_conf0); |
||||
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); |
||||
} |
||||
|
||||
static int detect_i2c(struct display_info_t const *dev) |
||||
{ |
||||
return ((0 == i2c_set_bus_num(dev->bus)) |
||||
&& |
||||
(0 == i2c_probe(dev->addr))); |
||||
} |
||||
|
||||
static void enable_lvds(struct display_info_t const *dev) |
||||
{ |
||||
struct iomuxc *iomux = (struct iomuxc *) |
||||
IOMUXC_BASE_ADDR; |
||||
u32 reg = readl(&iomux->gpr[2]); |
||||
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; |
||||
writel(reg, &iomux->gpr[2]); |
||||
gpio_direction_output(LVDS_BACKLIGHT_GP, 1); |
||||
} |
||||
|
||||
static void enable_rgb(struct display_info_t const *dev) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads( |
||||
rgb_pads, |
||||
ARRAY_SIZE(rgb_pads)); |
||||
gpio_direction_output(RGB_BACKLIGHT_GP, 1); |
||||
} |
||||
|
||||
static struct display_info_t const displays[] = {{ |
||||
.bus = -1, |
||||
.addr = 0, |
||||
.pixfmt = IPU_PIX_FMT_RGB24, |
||||
.detect = detect_hdmi, |
||||
.enable = enable_hdmi, |
||||
.mode = { |
||||
.name = "HDMI", |
||||
.refresh = 60, |
||||
.xres = 1024, |
||||
.yres = 768, |
||||
.pixclock = 15385, |
||||
.left_margin = 220, |
||||
.right_margin = 40, |
||||
.upper_margin = 21, |
||||
.lower_margin = 7, |
||||
.hsync_len = 60, |
||||
.vsync_len = 10, |
||||
.sync = FB_SYNC_EXT, |
||||
.vmode = FB_VMODE_NONINTERLACED |
||||
} }, { |
||||
.bus = 2, |
||||
.addr = 0x4, |
||||
.pixfmt = IPU_PIX_FMT_LVDS666, |
||||
.detect = detect_i2c, |
||||
.enable = enable_lvds, |
||||
.mode = { |
||||
.name = "Hannstar-XGA", |
||||
.refresh = 60, |
||||
.xres = 1024, |
||||
.yres = 768, |
||||
.pixclock = 15385, |
||||
.left_margin = 220, |
||||
.right_margin = 40, |
||||
.upper_margin = 21, |
||||
.lower_margin = 7, |
||||
.hsync_len = 60, |
||||
.vsync_len = 10, |
||||
.sync = FB_SYNC_EXT, |
||||
.vmode = FB_VMODE_NONINTERLACED |
||||
} }, { |
||||
.bus = 2, |
||||
.addr = 0x38, |
||||
.pixfmt = IPU_PIX_FMT_LVDS666, |
||||
.detect = detect_i2c, |
||||
.enable = enable_lvds, |
||||
.mode = { |
||||
.name = "wsvga-lvds", |
||||
.refresh = 60, |
||||
.xres = 1024, |
||||
.yres = 600, |
||||
.pixclock = 15385, |
||||
.left_margin = 220, |
||||
.right_margin = 40, |
||||
.upper_margin = 21, |
||||
.lower_margin = 7, |
||||
.hsync_len = 60, |
||||
.vsync_len = 10, |
||||
.sync = FB_SYNC_EXT, |
||||
.vmode = FB_VMODE_NONINTERLACED |
||||
} }, { |
||||
.bus = 2, |
||||
.addr = 0x48, |
||||
.pixfmt = IPU_PIX_FMT_RGB666, |
||||
.detect = detect_i2c, |
||||
.enable = enable_rgb, |
||||
.mode = { |
||||
.name = "wvga-rgb", |
||||
.refresh = 57, |
||||
.xres = 800, |
||||
.yres = 480, |
||||
.pixclock = 37037, |
||||
.left_margin = 40, |
||||
.right_margin = 60, |
||||
.upper_margin = 10, |
||||
.lower_margin = 10, |
||||
.hsync_len = 20, |
||||
.vsync_len = 10, |
||||
.sync = 0, |
||||
.vmode = FB_VMODE_NONINTERLACED |
||||
} } }; |
||||
|
||||
int board_video_skip(void) |
||||
{ |
||||
int i; |
||||
int ret; |
||||
char const *panel = getenv("panel"); |
||||
if (!panel) { |
||||
for (i = 0; i < ARRAY_SIZE(displays); i++) { |
||||
struct display_info_t const *dev = displays+i; |
||||
if (dev->detect(dev)) { |
||||
panel = dev->mode.name; |
||||
printf("auto-detected panel %s\n", panel); |
||||
break; |
||||
} |
||||
} |
||||
if (!panel) { |
||||
panel = displays[0].mode.name; |
||||
printf("No panel detected: default to %s\n", panel); |
||||
} |
||||
} else { |
||||
for (i = 0; i < ARRAY_SIZE(displays); i++) { |
||||
if (!strcmp(panel, displays[i].mode.name)) |
||||
break; |
||||
} |
||||
} |
||||
if (i < ARRAY_SIZE(displays)) { |
||||
ret = ipuv3_fb_init(&displays[i].mode, 0, |
||||
displays[i].pixfmt); |
||||
if (!ret) { |
||||
displays[i].enable(displays+i); |
||||
printf("Display: %s (%ux%u)\n", |
||||
displays[i].mode.name, |
||||
displays[i].mode.xres, |
||||
displays[i].mode.yres); |
||||
} else |
||||
printf("LCD %s cannot be configured: %d\n", |
||||
displays[i].mode.name, ret); |
||||
} else { |
||||
printf("unsupported panel %s\n", panel); |
||||
ret = -EINVAL; |
||||
} |
||||
return (0 != ret); |
||||
} |
||||
|
||||
static void setup_display(void) |
||||
{ |
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
||||
|
||||
int reg; |
||||
|
||||
/* Turn on LDB0,IPU,IPU DI0 clocks */ |
||||
reg = __raw_readl(&mxc_ccm->CCGR3); |
||||
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET |
||||
|MXC_CCM_CCGR3_LDB_DI0_MASK; |
||||
writel(reg, &mxc_ccm->CCGR3); |
||||
|
||||
/* Turn on HDMI PHY clock */ |
||||
reg = __raw_readl(&mxc_ccm->CCGR2); |
||||
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK |
||||
|MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; |
||||
writel(reg, &mxc_ccm->CCGR2); |
||||
|
||||
/* clear HDMI PHY reset */ |
||||
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); |
||||
|
||||
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ |
||||
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); |
||||
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set); |
||||
|
||||
/* set LDB0, LDB1 clk select to 011/011 */ |
||||
reg = readl(&mxc_ccm->cs2cdr); |
||||
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
||||
|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); |
||||
reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
||||
|(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); |
||||
writel(reg, &mxc_ccm->cs2cdr); |
||||
|
||||
reg = readl(&mxc_ccm->cscmr2); |
||||
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; |
||||
writel(reg, &mxc_ccm->cscmr2); |
||||
|
||||
reg = readl(&mxc_ccm->chsccdr); |
||||
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
||||
|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
||||
|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); |
||||
reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) |
||||
|(CHSCCDR_PODF_DIVIDE_BY_3 |
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
||||
|(CHSCCDR_IPU_PRE_CLK_540M_PFD |
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); |
||||
writel(reg, &mxc_ccm->chsccdr); |
||||
|
||||
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
||||
|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
||||
|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
||||
|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
||||
|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
||||
|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
||||
|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
||||
|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
||||
|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; |
||||
writel(reg, &iomux->gpr[2]); |
||||
|
||||
reg = readl(&iomux->gpr[3]); |
||||
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
||||
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 |
||||
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); |
||||
writel(reg, &iomux->gpr[3]); |
||||
|
||||
/* backlights off until needed */ |
||||
imx_iomux_v3_setup_multiple_pads(backlight_pads, |
||||
ARRAY_SIZE(backlight_pads)); |
||||
gpio_direction_input(LVDS_BACKLIGHT_GP); |
||||
gpio_direction_input(RGB_BACKLIGHT_GP); |
||||
} |
||||
#endif |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
setup_iomux_uart(); |
||||
setup_buttons(); |
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3) |
||||
setup_display(); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Do not overwrite the console |
||||
* Use always serial for U-Boot console |
||||
*/ |
||||
int overwrite_console(void) |
||||
{ |
||||
return 1; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
#ifdef CONFIG_MXC_SPI |
||||
setup_spi(); |
||||
#endif |
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); |
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); |
||||
|
||||
#ifdef CONFIG_CMD_SATA |
||||
setup_sata(); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: MX6Q-Sabre Lite\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
struct button_key { |
||||
char const *name; |
||||
unsigned gpnum; |
||||
char ident; |
||||
}; |
||||
|
||||
static struct button_key const buttons[] = { |
||||
{"back", IMX_GPIO_NR(2, 2), 'B'}, |
||||
{"home", IMX_GPIO_NR(2, 4), 'H'}, |
||||
{"menu", IMX_GPIO_NR(2, 1), 'M'}, |
||||
{"search", IMX_GPIO_NR(2, 3), 'S'}, |
||||
{"volup", IMX_GPIO_NR(7, 13), 'V'}, |
||||
{"voldown", IMX_GPIO_NR(4, 5), 'v'}, |
||||
}; |
||||
|
||||
/*
|
||||
* generate a null-terminated string containing the buttons pressed |
||||
* returns number of keys pressed |
||||
*/ |
||||
static int read_keys(char *buf) |
||||
{ |
||||
int i, numpressed = 0; |
||||
for (i = 0; i < ARRAY_SIZE(buttons); i++) { |
||||
if (!gpio_get_value(buttons[i].gpnum)) |
||||
buf[numpressed++] = buttons[i].ident; |
||||
} |
||||
buf[numpressed] = '\0'; |
||||
return numpressed; |
||||
} |
||||
|
||||
static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
char envvalue[ARRAY_SIZE(buttons)+1]; |
||||
int numpressed = read_keys(envvalue); |
||||
setenv("keybd", envvalue); |
||||
return numpressed == 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
kbd, 1, 1, do_kbd, |
||||
"Tests for keypresses, sets 'keybd' environment variable", |
||||
"Returns 0 (true) to shell if key is pressed." |
||||
); |
||||
|
||||
#ifdef CONFIG_PREBOOT |
||||
static char const kbd_magic_prefix[] = "key_magic"; |
||||
static char const kbd_command_prefix[] = "key_cmd"; |
||||
|
||||
static void preboot_keys(void) |
||||
{ |
||||
int numpressed; |
||||
char keypress[ARRAY_SIZE(buttons)+1]; |
||||
numpressed = read_keys(keypress); |
||||
if (numpressed) { |
||||
char *kbd_magic_keys = getenv("magic_keys"); |
||||
char *suffix; |
||||
/*
|
||||
* loop over all magic keys |
||||
*/ |
||||
for (suffix = kbd_magic_keys; *suffix; ++suffix) { |
||||
char *keys; |
||||
char magic[sizeof(kbd_magic_prefix) + 1]; |
||||
sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); |
||||
keys = getenv(magic); |
||||
if (keys) { |
||||
if (!strcmp(keys, keypress)) |
||||
break; |
||||
} |
||||
} |
||||
if (*suffix) { |
||||
char cmd_name[sizeof(kbd_command_prefix) + 1]; |
||||
char *cmd; |
||||
sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); |
||||
cmd = getenv(cmd_name); |
||||
if (cmd) { |
||||
setenv("preboot", cmd); |
||||
return; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_BMODE |
||||
static const struct boot_mode board_boot_modes[] = { |
||||
/* 4 bit bus width */ |
||||
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, |
||||
{"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
||||
{NULL, 0}, |
||||
}; |
||||
#endif |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_PREBOOT |
||||
preboot_keys(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_BMODE |
||||
add_board_boot_modes(board_boot_modes); |
||||
#endif |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,160 @@ |
||||
Summary |
||||
======= |
||||
|
||||
This document covers various features of the 'am335x_evm' build, and some of |
||||
the related build targets (am335x_evm_uartN, etc). |
||||
|
||||
Hardware |
||||
======== |
||||
|
||||
The binary produced by this board supports, based on parsing of the EEPROM |
||||
documented in TI's reference designs: |
||||
- AM335x GP EVM |
||||
- AM335x EVM SK |
||||
- Beaglebone White |
||||
- Beaglebone Black |
||||
' |
||||
NAND |
||||
==== |
||||
|
||||
The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In |
||||
this example to program the NAND we assume that an SD card has been |
||||
inserted with the files to write in the first SD slot and that mtdparts |
||||
have been configured correctly for the board. As a time saving measure we |
||||
load MLO into memory in one location, copy it into the three locatations |
||||
that the ROM checks for additional valid copies, then load U-Boot into |
||||
memory. We then write that whole section of memory to NAND. |
||||
|
||||
U-Boot # mmc rescan |
||||
U-Boot # env default -f -a |
||||
U-Boot # nand erase.chip |
||||
U-Boot # saveenv |
||||
U-Boot # load mmc 0 81000000 MLO |
||||
U-Boot # cp.b 81000000 81020000 20000 |
||||
U-Boot # cp.b 81000000 81040000 20000 |
||||
U-Boot # cp.b 81000000 81060000 20000 |
||||
U-Boot # load mmc 0 81080000 u-boot.img |
||||
U-Boot # nand write 81000000 0 260000 |
||||
U-Boot # load mmc 0 ${loadaddr} uImage |
||||
U-Boot # nand write ${loadaddr} kernel 500000 |
||||
|
||||
NOR |
||||
=== |
||||
|
||||
The Beaglebone White can be equiped with a "memory cape" that in turn can |
||||
have a NOR module plugged into it. In this case it is then possible to |
||||
program and boot from NOR. Note that due to how U-Boot is architectured we |
||||
must build a specific version of U-Boot that knows we have NOR flash. This |
||||
build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot' |
||||
build that will assume that the environment is on NOR rather than NAND. In |
||||
the following example we assume that and SD card has been populated with |
||||
MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the |
||||
'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a |
||||
binary must be written to the start of NOR, with no header or similar |
||||
prepended. In the following example we use a size of 512KiB (0x80000) |
||||
as that is how much space we set aside before the environment, as per |
||||
the config file. |
||||
|
||||
U-Boot # mmc rescan |
||||
U-Boot # load mmc 0 ${loadaddr} u-boot.bin |
||||
U-Boot # protect off 08000000 +80000 |
||||
U-Boot # erase 08000000 +80000 |
||||
U-Boot # cp.b ${loadaddr} 08000000 ${filesize} |
||||
|
||||
Falcon Mode |
||||
=========== |
||||
|
||||
The default build includes "Falcon Mode" (see doc/README.falcon) via NAND, |
||||
eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is |
||||
to read a 'c' on the console while in SPL at any point prior to loading the |
||||
OS payload (so as soon as possible) to opt to booting full U-Boot. Also |
||||
note that while one can program Falcon Mode "in place" great care needs to |
||||
be taken by the user to not 'brick' their setup. As these are all eval |
||||
boards with multiple boot methods, recovery should not be an issue in this |
||||
worst-case however. |
||||
|
||||
Falcon Mode: eMMC |
||||
================= |
||||
|
||||
The recommended layout in this case is: |
||||
|
||||
MMC BLOCKS |--------------------------------| LOCATION IN BYTES |
||||
0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000 |
||||
0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000 |
||||
0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000 |
||||
0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000 |
||||
0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000 |
||||
0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000 |
||||
0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000 |
||||
|
||||
Note that when we run 'spl export' it will prepare to boot the kernel. |
||||
This includes relocation of the uImage from where we loaded it to the entry |
||||
point defined in the header. As these locations overlap by default, it |
||||
would leave us with an image that if written to MMC will not boot, so |
||||
instead of using the loadaddr variable we use 0x81000000 in the following |
||||
example. In this example we are loading from the network, for simplicity, |
||||
and assume a valid partition table already exists and 'mmc dev' has already |
||||
been run to select the correct device. Also note that if you previously |
||||
had a FAT partition (such as on a Beaglebone Black) it is not enough to |
||||
write garbage into the area, you must delete it from the partition table |
||||
first. |
||||
|
||||
# Ensure we are able to talk with this mmc device |
||||
U-Boot # mmc rescan |
||||
U-Boot # tftp 81000000 am335x/MLO |
||||
# Write to two of the backup locations ROM uses |
||||
U-Boot # mmc write 81000000 100 100 |
||||
U-Boot # mmc write 81000000 200 100 |
||||
# Write U-Boot to the location set in the config |
||||
U-Boot # tftp 81000000 am335x/u-boot.img |
||||
U-Boot # mmc write 81000000 300 400 |
||||
# Load kernel and device tree into memory, perform export |
||||
U-Boot # tftp 81000000 am335x/uImage |
||||
U-Boot # run findfdt |
||||
U-Boot # tftp ${fdtaddr} am335x/${fdtfile} |
||||
U-Boot # run mmcargs |
||||
U-Boot # spl export fdt 81000000 - ${fdtaddr} |
||||
# Write the updated device tree to MMC |
||||
U-Boot # mmc write ${fdtaddr} 80 80 |
||||
# Write the uImage to MMC |
||||
U-Boot # mmc write 81000000 900 2000 |
||||
|
||||
Falcon Mode: FAT SD cards |
||||
========================= |
||||
|
||||
In this case the additional file is written to the filesystem. In this |
||||
example we assume that the uImage and device tree to be used are already on |
||||
the FAT filesystem (only the uImage MUST be for this to function |
||||
afterwards) along with a Falcon Mode aware MLO and the FAT partition has |
||||
already been created and marked bootable: |
||||
|
||||
U-Boot # mmc rescan |
||||
# Load kernel and device tree into memory, perform export |
||||
U-Boot # load mmc 0:1 ${loadaddr} uImage |
||||
U-Boot # run findfdt |
||||
U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile} |
||||
U-Boot # run mmcargs |
||||
U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} |
||||
|
||||
This will print a number of lines and then end with something like: |
||||
Using Device Tree in place at 80f80000, end 80f85928 |
||||
Using Device Tree in place at 80f80000, end 80f88928 |
||||
So then you: |
||||
|
||||
U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928 |
||||
|
||||
Falcon Mode: NAND |
||||
================= |
||||
|
||||
In this case the additional data is written to another partition of the |
||||
NAND. In this example we assume that the uImage and device tree to be are |
||||
already located on the NAND somewhere (such as fileystem or mtd partition) |
||||
along with a Falcon Mode aware MLO written to the correct locations for |
||||
booting and mtdparts have been configured correctly for the board: |
||||
|
||||
U-Boot # nand read ${loadaddr} kernel |
||||
U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb |
||||
U-Boot # run nandargs |
||||
U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} |
||||
U-Boot # nand erase.part u-boot-spl-os |
||||
U-Boot # nand write ${fdtaddr} u-boot-spl-os |
||||
@ -0,0 +1,117 @@ |
||||
/* |
||||
* Copyright (c) 2004-2008 Texas Instruments |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
*(.__image_copy_start) |
||||
CPUDIR/start.o (.text*) |
||||
board/ti/am335x/libam335x.o (.text*) |
||||
*(.text*) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { |
||||
*(.data*) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
|
||||
. = .; |
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
|
||||
.image_copy_end : |
||||
{ |
||||
*(.__image_copy_end) |
||||
} |
||||
|
||||
.rel_dyn_start : |
||||
{ |
||||
*(.__rel_dyn_start) |
||||
} |
||||
|
||||
.rel.dyn : { |
||||
*(.rel*) |
||||
} |
||||
|
||||
.rel_dyn_end : |
||||
{ |
||||
*(.__rel_dyn_end) |
||||
} |
||||
|
||||
_end = .; |
||||
|
||||
/* |
||||
* Deprecated: this MMU section is used by pxa at present but |
||||
* should not be used by new boards/CPUs. |
||||
*/ |
||||
. = ALIGN(4096); |
||||
.mmutable : { |
||||
*(.mmutable) |
||||
} |
||||
|
||||
/* |
||||
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c |
||||
* __bss_base and __bss_limit are for linker only (overlay ordering) |
||||
*/ |
||||
|
||||
.bss_start __rel_dyn_start (OVERLAY) : { |
||||
KEEP(*(.__bss_start)); |
||||
__bss_base = .; |
||||
} |
||||
|
||||
.bss __bss_base (OVERLAY) : { |
||||
*(.bss*) |
||||
. = ALIGN(4); |
||||
__bss_limit = .; |
||||
} |
||||
|
||||
.bss_end __bss_limit (OVERLAY) : { |
||||
KEEP(*(.__bss_end)); |
||||
} |
||||
|
||||
/DISCARD/ : { *(.dynsym) } |
||||
/DISCARD/ : { *(.dynstr*) } |
||||
/DISCARD/ : { *(.dynamic*) } |
||||
/DISCARD/ : { *(.plt*) } |
||||
/DISCARD/ : { *(.interp*) } |
||||
/DISCARD/ : { *(.gnu*) } |
||||
} |
||||
@ -0,0 +1,38 @@ |
||||
#
|
||||
# Makefile
|
||||
#
|
||||
# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD |
||||
COBJS := mux.o
|
||||
endif |
||||
|
||||
COBJS += board.o
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,57 @@ |
||||
/*
|
||||
* board.c |
||||
* |
||||
* Board functions for TI AM43XX based boards |
||||
* |
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <spl.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/mux.h> |
||||
#include "board.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
|
||||
const struct dpll_params dpll_ddr = { |
||||
-1, -1, -1, -1, -1, -1, -1}; |
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void) |
||||
{ |
||||
return &dpll_ddr; |
||||
} |
||||
|
||||
void set_uart_mux_conf(void) |
||||
{ |
||||
enable_uart0_pin_mux(); |
||||
} |
||||
|
||||
void set_mux_conf_regs(void) |
||||
{ |
||||
enable_board_pin_mux(); |
||||
} |
||||
|
||||
void sdram_init(void) |
||||
{ |
||||
} |
||||
#endif |
||||
|
||||
int board_init(void) |
||||
{ |
||||
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT |
||||
int board_late_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,17 @@ |
||||
/*
|
||||
* board.h |
||||
* |
||||
* TI AM437x boards information header |
||||
* Derived from AM335x board. |
||||
* |
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _BOARD_H_ |
||||
#define _BOARD_H_ |
||||
|
||||
void enable_uart0_pin_mux(void); |
||||
void enable_board_pin_mux(void); |
||||
#endif |
||||
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* mux.c |
||||
* |
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/mux.h> |
||||
#include "board.h" |
||||
|
||||
static struct module_pin_mux uart0_pin_mux[] = { |
||||
{OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */ |
||||
{OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */ |
||||
{-1}, |
||||
}; |
||||
|
||||
void enable_uart0_pin_mux(void) |
||||
{ |
||||
configure_module_pin_mux(uart0_pin_mux); |
||||
} |
||||
|
||||
void enable_board_pin_mux(void) |
||||
{ |
||||
} |
||||
@ -0,0 +1,37 @@ |
||||
#
|
||||
# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
||||
# Antoine Tenart, <atenart@adeneo-embedded.com>
|
||||
#
|
||||
# Based on TI-PSP-04.00.02.14 :
|
||||
#
|
||||
# Copyright (C) 2009, Texas Instruments, Incorporated
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := evm.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
clean: |
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue