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sh: lowlevel_init coding style cleanup

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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
master
Jean-Christophe PLAGNIOL-VILLARD 16 years ago committed by Nobuhiro Iwamatsu
parent 85cb052ee4
commit e443077962
10 changed files with 640 additions and 634 deletions
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  1. 44
      board/mpr2/lowlevel_init.S
  2. 34
      board/ms7722se/lowlevel_init.S
  3. 150
      board/ms7750se/lowlevel_init.S
  4. 10
      board/renesas/MigoR/lowlevel_init.S
  5. 86
      board/renesas/ap325rxa/lowlevel_init.S
  6. 126
      board/renesas/r2dplus/lowlevel_init.S
  7. 446
      board/renesas/r7780mp/lowlevel_init.S
  8. 214
      board/renesas/rsk7203/lowlevel_init.S
  9. 162
      board/renesas/sh7763rdp/lowlevel_init.S
  10. 2
      board/renesas/sh7785lcr/lowlevel_init.S

44
board/mpr2/lowlevel_init.S
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@ -33,17 +33,17 @@ lowlevel_init:
/*
* Set frequency multipliers and dividers in FRQCR.
*/
mov.l WTCSR_A,r1
mov.l WTCSR_D,r0
mov.w r0,@r1
mov.l WTCSR_A, r1
mov.l WTCSR_D, r0
mov.w r0, @r1
mov.l WTCNT_A,r1
mov.l WTCNT_D,r0
mov.w r0,@r1
mov.l WTCNT_A, r1
mov.l WTCNT_D, r0
mov.w r0, @r1
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.w r0,@r1
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.w r0, @r1
/*
* Setup CS0 (Flash).
@ -112,21 +112,27 @@ WTCSR_D: .long 0xA507 /* divide by 4096 */
/*
* Spansion S29GL256N11 @ 48 MHz
*/
CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */
CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
/* 1 idle cycle inserted, normal space, 16 bit */
CS0BCR_D: .long 0x12490400
/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
CS0WCR_D: .long 0x00000340
/*
* Samsung K4S511632B-UL75 @ 48 MHz
* Micron MT48LC32M16A2-75 @ 48 MHz
*/
CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */
SDCR_D2: .long 0x00000812 /* refresh */
RTCSR_D: .long 0xA55A0008 /* 1/4, once */
RTCNT_D: .long 0xA55A005D /* count 93 */
RTCOR_D: .long 0xa55a005d /* count 93 */
SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */
/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
CS3BCR_D: .long 0x10004400
/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
CS3WCR_D: .long 0x00000091
/* no refresh, 13 rows, 10 cols, NO bank active mode */
SDCR_D1: .long 0x00000012
SDCR_D2: .long 0x00000812 /* refresh */
RTCSR_D: .long 0xA55A0008 /* 1/4, once */
RTCNT_D: .long 0xA55A005D /* count 93 */
RTCOR_D: .long 0xa55a005d /* count 93 */
/* mode register CL2, burst read and SINGLE WRITE */
SDMR3_D: .long 0x440
/*
* Registers

34
board/ms7722se/lowlevel_init.S
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@ -29,11 +29,11 @@
#include <asm/processor.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
@ -203,7 +203,7 @@ bsc_init:
mov #0x00, r0 ! SDMR3 data -> R0
mov.b r0, @r1 ! SDMR3 set
! BL bit off (init = ON) (?!?)
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
@ -232,28 +232,28 @@ MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
FRQCR_D: .long 0x07022538
PSELA_A: .long 0xa405014E
PSELA_D: .word 0x0A10
PSELA_A: .long 0xa405014E
PSELA_D: .word 0x0A10
.align 2
DRVCR_A: .long 0xa405018A
DRVCR_D: .word 0x0554
DRVCR_A: .long 0xa405018A
DRVCR_D: .word 0x0554
.align 2
PCCR_A: .long 0xa4050104
PCCR_D: .word 0x8800
PCCR_A: .long 0xa4050104
PCCR_D: .word 0x8800
.align 2
PECR_A: .long 0xa4050108
PECR_D: .word 0x0000
PECR_A: .long 0xa4050108
PECR_D: .word 0x0000
.align 2
PJCR_A: .long 0xa4050110
PJCR_D: .word 0x1000
PJCR_A: .long 0xa4050110
PJCR_D: .word 0x1000
.align 2
PXCR_A: .long 0xa4050148
PXCR_D: .word 0x0AAA
PXCR_A: .long 0xa4050148
PXCR_D: .word 0x0AAA
.align 2
CMNCR_A: .long CMNCR

150
board/ms7750se/lowlevel_init.S
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@ -31,118 +31,118 @@
#include <asm/processor.h>
#ifdef CONFIG_CPU_SH7751
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#ifdef CONFIG_MARUBUN_PCCARD
#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#else /* CONFIG_MARUBUN_PCCARD */
#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#endif /* CONFIG_MARUBUN_PCCARD */
#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
#else /* CONFIG_CPU_SH7751 */
#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:15 A0B:7 */
#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:15 A0B:7 */
#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
#endif /* CONFIG_CPU_SH7751 */
.global lowlevel_init
.text
.align 2
.align 2
lowlevel_init:
mov.l CCR_A, r1 ! CCR Address
mov.l CCR_D_DISABLE, r0 ! CCR Data
mov.l r0, @r1
mov.l CCR_A, r1 ! CCR Address
mov.l CCR_D_DISABLE, r0 ! CCR Data
mov.l r0, @r1
init_bsc:
mov.l FRQCR_A,r1 /* FRQCR Address */
mov.l FRQCR_D,r0 /* FRQCR Data */
mov.w r0,@r1
mov.l FRQCR_A, r1 /* FRQCR Address */
mov.l FRQCR_D, r0 /* FRQCR Data */
mov.w r0, @r1
mov.l BCR1_A,r1 /* BCR1 Address */
mov.l BCR1_D,r0 /* BCR1 Data */
mov.l r0,@r1
mov.l BCR1_A, r1 /* BCR1 Address */
mov.l BCR1_D, r0 /* BCR1 Data */
mov.l r0, @r1
mov.l BCR2_A,r1 /* BCR2 Address */
mov.l BCR2_D,r0 /* BCR2 Data */
mov.w r0,@r1
mov.l BCR2_A, r1 /* BCR2 Address */
mov.l BCR2_D, r0 /* BCR2 Data */
mov.w r0, @r1
mov.l WCR1_A,r1 /* WCR1 Address */
mov.l WCR1_D,r0 /* WCR1 Data */
mov.l r0,@r1
mov.l WCR1_A, r1 /* WCR1 Address */
mov.l WCR1_D, r0 /* WCR1 Data */
mov.l r0, @r1
mov.l WCR2_A,r1 /* WCR2 Address */
mov.l WCR2_D,r0 /* WCR2 Data */
mov.l r0,@r1
mov.l WCR2_A, r1 /* WCR2 Address */
mov.l WCR2_D, r0 /* WCR2 Data */
mov.l r0, @r1
mov.l WCR3_A,r1 /* WCR3 Address */
mov.l WCR3_D,r0 /* WCR3 Data */
mov.l r0,@r1
mov.l WCR3_A, r1 /* WCR3 Address */
mov.l WCR3_D, r0 /* WCR3 Data */
mov.l r0, @r1
mov.l MCR_A,r1 /* MCR Address */
mov.l MCR_D1,r0 /* MCR Data1 */
mov.l r0,@r1
mov.l MCR_A, r1 /* MCR Address */
mov.l MCR_D1, r0 /* MCR Data1 */
mov.l r0, @r1
mov.l SDMR3_A,r1 /* Set SDRAM mode */
mov #0,r0
mov.b r0,@r1
mov.l SDMR3_A, r1 /* Set SDRAM mode */
mov #0, r0
mov.b r0, @r1
! Do you need PCMCIA setting?
! If so, please add the lines here...
mov.l RTCNT_A,r1 /* RTCNT Address */
mov.l RTCNT_D,r0 /* RTCNT Data */
mov.w r0,@r1
mov.l RTCNT_A, r1 /* RTCNT Address */
mov.l RTCNT_D, r0 /* RTCNT Data */
mov.w r0, @r1
mov.l RTCOR_A,r1 /* RTCOR Address */
mov.l RTCOR_D,r0 /* RTCOR Data */
mov.w r0,@r1
mov.l RTCOR_A, r1 /* RTCOR Address */
mov.l RTCOR_D, r0 /* RTCOR Data */
mov.w r0, @r1
mov.l RTCSR_A,r1 /* RTCSR Address */
mov.l RTCSR_D,r0 /* RTCSR Data */
mov.w r0,@r1
mov.l RTCSR_A, r1 /* RTCSR Address */
mov.l RTCSR_D, r0 /* RTCSR Data */
mov.w r0, @r1
mov.l RFCR_A,r1 /* RFCR Address */
mov.l RFCR_D,r0 /* RFCR Data */
mov.w r0,@r1 /* Clear reflesh counter */
mov.l RFCR_A, r1 /* RFCR Address */
mov.l RFCR_D, r0 /* RFCR Data */
mov.w r0, @r1 /* Clear reflesh counter */
/* Wait DRAM refresh 30 times */
mov #30,r3
mov #30, r3
1:
mov.w @r1,r0
extu.w r0,r2
cmp/hi r3,r2
mov.w @r1, r0
extu.w r0, r2
cmp/hi r3, r2
bf 1b
mov.l MCR_A,r1 /* MCR Address */
mov.l MCR_D2,r0 /* MCR Data2 */
mov.l r0,@r1
mov.l MCR_A, r1 /* MCR Address */
mov.l MCR_D2, r0 /* MCR Data2 */
mov.l r0, @r1
mov.l SDMR3_A,r1 /* Set SDRAM mode */
mov #0,r0
mov.b r0,@r1
mov.l SDMR3_A, r1 /* Set SDRAM mode */
mov #0, r0
mov.b r0, @r1
rts
nop
nop
.align 2
CCR_A: .long CCR
CCR_D_DISABLE: .long 0x0808
CCR_A: .long CCR
CCR_D_DISABLE: .long 0x0808
FRQCR_A: .long FRQCR
FRQCR_D:
#ifdef CONFIG_CPU_TYPE_R

10
board/renesas/MigoR/lowlevel_init.S
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@ -29,11 +29,11 @@
#include <asm/processor.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
@ -176,7 +176,7 @@ bsc_init:
mov #0x00, r0 ! SDMR3 data -> R0
mov.b r0, @r1 ! SDMR3 set
! BL bit off (init = ON) (?!?)
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1

86
board/renesas/ap325rxa/lowlevel_init.S
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@ -39,111 +39,111 @@
lowlevel_init:
mov.l DRVCRA_A, r1
mov.l DRVCRA_D, r0
mov.l DRVCRA_D, r0
mov.w r0, @r1
mov.l DRVCRB_A, r1
mov.l DRVCRB_D, r0
mov.l DRVCRB_D, r0
mov.w r0, @r1
mov.l RWTCSR_A, r1
mov.l RWTCSR_D1, r0
mov.l RWTCSR_D1, r0
mov.w r0, @r1
mov.l RWTCNT_A, r1
mov.l RWTCNT_D, r0
mov.l RWTCNT_D, r0
mov.w r0, @r1
mov.l RWTCSR_A, r1
mov.l RWTCSR_D2, r0
mov.l RWTCSR_D2, r0
mov.w r0, @r1
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.l FRQCR_D, r0
mov.l r0, @r1
mov.l CMNCR_A, r1
mov.l CMNCR_D, r0
mov.l r0, @r1
mov.l CS0BCR_A ,r1
mov.l CS0BCR_D ,r0
mov.l CS0BCR_A, r1
mov.l CS0BCR_D, r0
mov.l r0, @r1
mov.l CS4BCR_A ,r1
mov.l CS4BCR_D ,r0
mov.l CS4BCR_A, r1
mov.l CS4BCR_D, r0
mov.l r0, @r1
mov.l CS5ABCR_A ,r1
mov.l CS5ABCR_D ,r0
mov.l CS5ABCR_A, r1
mov.l CS5ABCR_D, r0
mov.l r0, @r1
mov.l CS5BBCR_A ,r1
mov.l CS5BBCR_D ,r0
mov.l CS5BBCR_A, r1
mov.l CS5BBCR_D, r0
mov.l r0, @r1
mov.l CS6ABCR_A ,r1
mov.l CS6ABCR_D ,r0
mov.l CS6ABCR_A, r1
mov.l CS6ABCR_D, r0
mov.l r0, @r1
mov.l CS6BBCR_A ,r1
mov.l CS6BBCR_D ,r0
mov.l CS6BBCR_A, r1
mov.l CS6BBCR_D, r0
mov.l r0, @r1
mov.l CS0WCR_A ,r1
mov.l CS0WCR_D ,r0
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
mov.l CS4WCR_A ,r1
mov.l CS4WCR_D ,r0
mov.l CS4WCR_A, r1
mov.l CS4WCR_D, r0
mov.l r0, @r1
mov.l CS5AWCR_A ,r1
mov.l CS5AWCR_D ,r0
mov.l CS5AWCR_A, r1
mov.l CS5AWCR_D, r0
mov.l r0, @r1
mov.l CS5BWCR_A ,r1
mov.l CS5BWCR_D ,r0
mov.l CS5BWCR_A, r1
mov.l CS5BWCR_D, r0
mov.l r0, @r1
mov.l CS6AWCR_A ,r1
mov.l CS6AWCR_D ,r0
mov.l CS6AWCR_A, r1
mov.l CS6AWCR_D, r0
mov.l r0, @r1
mov.l CS6BWCR_A ,r1
mov.l CS6BWCR_D ,r0
mov.l CS6BWCR_A, r1
mov.l CS6BWCR_D, r0
mov.l r0, @r1
mov.l SBSC_SDCR_A, r1
mov.l SBSC_SDCR_D1, r0
mov.l SBSC_SDCR_D1, r0
mov.l r0, @r1
mov.l SBSC_SDWCR_A, r1
mov.l SBSC_SDWCR_D, r0
mov.l SBSC_SDWCR_D, r0
mov.l r0, @r1
mov.l SBSC_SDPCR_A, r1
mov.l SBSC_SDPCR_D, r0
mov.l SBSC_SDPCR_D, r0
mov.l r0, @r1
mov.l SBSC_RTCSR_A, r1
mov.l SBSC_RTCSR_D, r0
mov.l SBSC_RTCSR_D, r0
mov.l r0, @r1
mov.l SBSC_RTCNT_A, r1
mov.l SBSC_RTCNT_D, r0
mov.l SBSC_RTCNT_D, r0
mov.l r0, @r1
mov.l SBSC_RTCOR_A, r1
mov.l SBSC_RTCOR_D, r0
mov.l SBSC_RTCOR_D, r0
mov.l r0, @r1
mov.l SBSC_SDMR3_A1, r1
mov.l SBSC_SDMR3_D, r0
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
mov.l SBSC_SDMR3_A2, r1
mov.l SBSC_SDMR3_D, r0
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
mov.l SLEEP_CNT, r1
@ -153,18 +153,18 @@ lowlevel_init:
dt r1
mov.l SBSC_SDMR3_A3, r1
mov.l SBSC_SDMR3_D, r0
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
mov.l SBSC_SDCR_A, r1
mov.l SBSC_SDCR_D2, r0
mov.l SBSC_SDCR_D2, r0
mov.l r0, @r1
mov.l CCR_A, r1
mov.l CCR_D, r0
mov.l CCR_D, r0
mov.l r0, @r1
! BL bit off (init = ON) (?!?)
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
@ -211,7 +211,7 @@ SBSC_SDMR3_D: .long 0x00
CMNCR_A: .long CMNCR
CS0BCR_A: .long CS0BCR
CS4BCR_A: .long CS4BCR
CS5ABCR_A: .long CS5ABCR
CS5ABCR_A: .long CS5ABCR
CS5BBCR_A: .long CS5BBCR
CS6ABCR_A: .long CS6ABCR
CS6BBCR_A: .long CS6BBCR

126
board/renesas/r2dplus/lowlevel_init.S
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@ -17,92 +17,92 @@ lowlevel_init:
mov.l CCR_A, r1
mov.l CCR_D_D, r0
mov.l r0,@r1
mov.l r0, @r1
mov.l MMUCR_A,r1
mov.l MMUCR_D,r0
mov.l r0,@r1
mov.l MMUCR_A, r1
mov.l MMUCR_D, r0
mov.l r0, @r1
mov.l BCR1_A,r1
mov.l BCR1_D,r0
mov.l r0,@r1
mov.l BCR1_A, r1
mov.l BCR1_D, r0
mov.l r0, @r1
mov.l BCR2_A,r1
mov.l BCR2_D,r0
mov.w r0,@r1
mov.l BCR2_A, r1
mov.l BCR2_D, r0
mov.w r0, @r1
mov.l BCR3_A,r1
mov.l BCR3_D,r0
mov.w r0,@r1
mov.l BCR3_A, r1
mov.l BCR3_D, r0
mov.w r0, @r1
mov.l BCR4_A,r1
mov.l BCR4_D,r0
mov.l r0,@r1
mov.l BCR4_A, r1
mov.l BCR4_D, r0
mov.l r0, @r1
mov.l WCR1_A,r1
mov.l WCR1_D,r0
mov.l r0,@r1
mov.l WCR1_A, r1
mov.l WCR1_D, r0
mov.l r0, @r1
mov.l WCR2_A,r1
mov.l WCR2_D,r0
mov.l r0,@r1
mov.l WCR2_A, r1
mov.l WCR2_D, r0
mov.l r0, @r1
mov.l WCR3_A,r1
mov.l WCR3_D,r0
mov.l r0,@r1
mov.l WCR3_A, r1
mov.l WCR3_D, r0
mov.l r0, @r1
mov.l PCR_A,r1
mov.l PCR_D,r0
mov.w r0,@r1
mov.l PCR_A, r1
mov.l PCR_D, r0
mov.w r0, @r1
mov.l LED_A,r1
mov #0xff,r0
mov.w r0,@r1
mov.l LED_A, r1
mov #0xff, r0
mov.w r0, @r1
mov.l MCR_A,r1
mov.l MCR_D1,r0
mov.l r0,@r1
mov.l MCR_A, r1
mov.l MCR_D1, r0
mov.l r0, @r1
mov.l RTCNT_A,r1
mov.l RTCNT_D,r0
mov.w r0,@r1
mov.l RTCNT_A, r1
mov.l RTCNT_D, r0
mov.w r0, @r1
mov.l RTCOR_A,r1
mov.l RTCOR_D,r0
mov.w r0,@r1
mov.l RTCOR_A, r1
mov.l RTCOR_D, r0
mov.w r0, @r1
mov.l RFCR_A,r1
mov.l RFCR_D,r0
mov.w r0,@r1
mov.l RFCR_A, r1
mov.l RFCR_D, r0
mov.w r0, @r1
mov.l RTCSR_A,r1
mov.l RTCSR_D,r0
mov.w r0,@r1
mov.l RTCSR_A, r1
mov.l RTCSR_D, r0
mov.w r0, @r1
mov.l SDMR3_A,r1
mov #0x55,r0
mov.b r0,@r1
mov.l SDMR3_A, r1
mov #0x55, r0
mov.b r0, @r1
/* Wait DRAM refresh 30 times */
mov.l RFCR_A,r1
mov #30,r3
mov.l RFCR_A, r1
mov #30, r3
1:
mov.w @r1,r0
extu.w r0,r2
cmp/hi r3,r2
mov.w @r1, r0
extu.w r0, r2
cmp/hi r3, r2
bf 1b
mov.l MCR_A,r1
mov.l MCR_D2,r0
mov.l r0,@r1
mov.l MCR_A, r1
mov.l MCR_D2, r0
mov.l r0, @r1
mov.l SDMR3_A,r1
mov #0,r0
mov.b r0,@r1
mov.l SDMR3_A, r1
mov #0, r0
mov.b r0, @r1
mov.l IRLMASK_A,r1
mov.l IRLMASK_D,r0
mov.l r0,@r1
mov.l IRLMASK_A, r1
mov.l IRLMASK_D, r0
mov.l r0, @r1
mov.l CCR_A, r1
mov.l CCR_D_E, r0

446
board/renesas/r7780mp/lowlevel_init.S
Unescape View File

@ -24,11 +24,11 @@
#include <asm/processor.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
@ -47,54 +47,54 @@ lowlevel_init:
mov.l r0, @r1
/* pin_multi_setting */
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR1,r0
mov.l r0,@r1
mov.l BBG_PMMR_A, r1
mov.l BBG_PMMR_D_PMSR1, r0
mov.l r0, @r1
mov.l BBG_PMSR1_A,r1
mov.l BBG_PMSR1_D,r0
mov.l r0,@r1
mov.l BBG_PMSR1_A, r1
mov.l BBG_PMSR1_D, r0
mov.l r0, @r1
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR2,r0
mov.l r0,@r1
mov.l BBG_PMMR_A, r1
mov.l BBG_PMMR_D_PMSR2, r0
mov.l r0, @r1
mov.l BBG_PMSR2_A,r1
mov.l BBG_PMSR2_D,r0
mov.l r0,@r1
mov.l BBG_PMSR2_A, r1
mov.l BBG_PMSR2_D, r0
mov.l r0, @r1
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR3,r0
mov.l r0,@r1
mov.l BBG_PMMR_A, r1
mov.l BBG_PMMR_D_PMSR3, r0
mov.l r0, @r1
mov.l BBG_PMSR3_A,r1
mov.l BBG_PMSR3_D,r0
mov.l r0,@r1
mov.l BBG_PMSR3_A, r1
mov.l BBG_PMSR3_D, r0
mov.l r0, @r1
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR4,r0
mov.l r0,@r1
mov.l BBG_PMMR_A, r1
mov.l BBG_PMMR_D_PMSR4, r0
mov.l r0, @r1
mov.l BBG_PMSR4_A,r1
mov.l BBG_PMSR4_D,r0
mov.l r0,@r1
mov.l BBG_PMSR4_A, r1
mov.l BBG_PMSR4_D, r0
mov.l r0, @r1
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSRG,r0
mov.l r0,@r1
mov.l BBG_PMMR_A, r1
mov.l BBG_PMMR_D_PMSRG, r0
mov.l r0, @r1
mov.l BBG_PMSRG_A,r1
mov.l BBG_PMSRG_D,r0
mov.l r0,@r1
mov.l BBG_PMSRG_A, r1
mov.l BBG_PMSRG_D, r0
mov.l r0, @r1
/* cpg_setting */
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.l r0,@r1
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.l r0, @r1
mov.l DLLCSR_A,r1
mov.l DLLCSR_D,r0
mov.l r0,@r1
mov.l DLLCSR_A, r1
mov.l DLLCSR_D, r0
mov.l r0, @r1
nop
nop
@ -108,111 +108,111 @@ lowlevel_init:
nop
/* wait 200us */
mov.l REPEAT0_R3,r3
mov #0,r2
mov.l REPEAT0_R3, r3
mov #0, r2
repeat0:
add #1,r2
cmp/hs r3,r2
bf repeat0
add #1, r2
cmp/hs r3, r2
bf repeat0
nop
/* bsc_setting */
mov.l MMSELR_A,r1
mov.l MMSELR_D,r0
mov.l r0,@r1
mov.l MMSELR_A, r1
mov.l MMSELR_D, r0
mov.l r0, @r1
mov.l BCR_A,r1
mov.l BCR_D,r0
mov.l r0,@r1
mov.l BCR_A, r1
mov.l BCR_D, r0
mov.l r0, @r1
mov.l CS0BCR_A,r1
mov.l CS0BCR_D,r0
mov.l r0,@r1
mov.l CS0BCR_A, r1
mov.l CS0BCR_D, r0
mov.l r0, @r1
mov.l CS1BCR_A,r1
mov.l CS1BCR_D,r0
mov.l r0,@r1
mov.l CS1BCR_A, r1
mov.l CS1BCR_D, r0
mov.l r0, @r1
mov.l CS2BCR_A,r1
mov.l CS2BCR_D,r0
mov.l r0,@r1
mov.l CS2BCR_A, r1
mov.l CS2BCR_D, r0
mov.l r0, @r1
mov.l CS4BCR_A,r1
mov.l CS4BCR_D,r0
mov.l r0,@r1
mov.l CS4BCR_A, r1
mov.l CS4BCR_D, r0
mov.l r0, @r1
mov.l CS5BCR_A,r1
mov.l CS5BCR_D,r0
mov.l r0,@r1
mov.l CS5BCR_A, r1
mov.l CS5BCR_D, r0
mov.l r0, @r1
mov.l CS6BCR_A,r1
mov.l CS6BCR_D,r0
mov.l r0,@r1
mov.l CS6BCR_A, r1
mov.l CS6BCR_D, r0
mov.l r0, @r1
mov.l CS0WCR_A,r1
mov.l CS0WCR_D,r0
mov.l r0,@r1
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
mov.l CS1WCR_A,r1
mov.l CS1WCR_D,r0
mov.l r0,@r1
mov.l CS1WCR_A, r1
mov.l CS1WCR_D, r0
mov.l r0, @r1
mov.l CS2WCR_A,r1
mov.l CS2WCR_D,r0
mov.l r0,@r1
mov.l CS2WCR_A, r1
mov.l CS2WCR_D, r0
mov.l r0, @r1
mov.l CS4WCR_A,r1
mov.l CS4WCR_D,r0
mov.l r0,@r1
mov.l CS4WCR_A, r1
mov.l CS4WCR_D, r0
mov.l r0, @r1
mov.l CS5WCR_A,r1
mov.l CS5WCR_D,r0
mov.l r0,@r1
mov.l CS5WCR_A, r1
mov.l CS5WCR_D, r0
mov.l r0, @r1
mov.l CS6WCR_A,r1
mov.l CS6WCR_D,r0
mov.l r0,@r1
mov.l CS6WCR_A, r1
mov.l CS6WCR_D, r0
mov.l r0, @r1
mov.l CS5PCR_A,r1
mov.l CS5PCR_D,r0
mov.l r0,@r1
mov.l CS5PCR_A, r1
mov.l CS5PCR_D, r0
mov.l r0, @r1
mov.l CS6PCR_A,r1
mov.l CS6PCR_D,r0
mov.l r0,@r1
mov.l CS6PCR_A, r1
mov.l CS6PCR_D, r0
mov.l r0, @r1
/* ddr_setting */
/* wait 200us */
mov.l REPEAT0_R3,r3
mov #0,r2
mov.l REPEAT0_R3, r3
mov #0, r2
repeat1:
add #1,r2
cmp/hs r3,r2
bf repeat1
add #1, r2
cmp/hs r3, r2
bf repeat1
nop
mov.l MIM_U_A,r0
mov.l MIM_U_D,r1
mov.l MIM_U_A, r0
mov.l MIM_U_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
mov.l MIM_L_A,r0
mov.l MIM_L_D0,r1
mov.l MIM_L_A, r0
mov.l MIM_L_D0, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
mov.l STR_L_A,r0
mov.l STR_L_D,r1
mov.l STR_L_A, r0
mov.l STR_L_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
mov.l SDR_L_A,r0
mov.l SDR_L_D,r1
mov.l SDR_L_A, r0
mov.l SDR_L_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
@ -220,193 +220,193 @@ repeat1:
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D0,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D0, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
mov.l SCR_L_A,r0
mov.l SCR_L_D1,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D1, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l EMRS_A,r0
mov.l EMRS_D,r1
mov.l EMRS_A, r0
mov.l EMRS_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l MRS1_A,r0
mov.l MRS1_D,r1
mov.l MRS1_A, r0
mov.l MRS1_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D2,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D2, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D3,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D3, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D4,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D4, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l MRS2_A,r0
mov.l MRS2_D,r1
mov.l MRS2_A, r0
mov.l MRS2_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D5,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D5, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
/* wait 200us */
mov.l REPEAT0_R1,r3
mov #0,r2
mov.l REPEAT0_R1, r3
mov #0, r2
repeat2:
add #1,r2
cmp/hs r3,r2
bf repeat2
add #1, r2
cmp/hs r3, r2
bf repeat2
synco
mov.l MIM_L_A,r0
mov.l MIM_L_D1,r1
mov.l MIM_L_A, r0
mov.l MIM_L_D1, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
rts
nop
.align 4
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA507
RWTCNT_D: .word 0x5A00
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA507
RWTCNT_D: .word 0x5A00
.align 2
BBG_PMMR_A: .long 0xFF800010
BBG_PMSR1_A: .long 0xFF800014
BBG_PMSR2_A: .long 0xFF800018
BBG_PMSR3_A: .long 0xFF80001C
BBG_PMSR4_A: .long 0xFF800020
BBG_PMSRG_A: .long 0xFF800024
BBG_PMMR_D_PMSR1: .long 0xffffbffd
BBG_PMSR1_D: .long 0x00004002
BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
BBG_PMSR2_D: .long 0x03de5800
BBG_PMMR_D_PMSR3: .long 0xfffffff8
BBG_PMSR3_D: .long 0x00000007
BBG_PMMR_D_PMSR4: .long 0xdffdfff9
BBG_PMSR4_D: .long 0x20020006
BBG_PMMR_D_PMSRG: .long 0xffffffff
BBG_PMSRG_D: .long 0x00000000
FRQCR_A: .long FRQCR
DLLCSR_A: .long 0xffc40010
FRQCR_D: .long 0x40233035
DLLCSR_D: .long 0x00000000
BBG_PMMR_A: .long 0xFF800010
BBG_PMSR1_A: .long 0xFF800014
BBG_PMSR2_A: .long 0xFF800018
BBG_PMSR3_A: .long 0xFF80001C
BBG_PMSR4_A: .long 0xFF800020
BBG_PMSRG_A: .long 0xFF800024
BBG_PMMR_D_PMSR1: .long 0xffffbffd
BBG_PMSR1_D: .long 0x00004002
BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
BBG_PMSR2_D: .long 0x03de5800
BBG_PMMR_D_PMSR3: .long 0xfffffff8
BBG_PMSR3_D: .long 0x00000007
BBG_PMMR_D_PMSR4: .long 0xdffdfff9
BBG_PMSR4_D: .long 0x20020006
BBG_PMMR_D_PMSRG: .long 0xffffffff
BBG_PMSRG_D: .long 0x00000000
FRQCR_A: .long FRQCR
DLLCSR_A: .long 0xffc40010
FRQCR_D: .long 0x40233035
DLLCSR_D: .long 0x00000000
/* for DDR-SDRAM */
MIM_U_A: .long MIM_1
MIM_L_A: .long MIM_2
SCR_U_A: .long SCR_1
SCR_L_A: .long SCR_2
STR_U_A: .long STR_1
STR_L_A: .long STR_2
SDR_U_A: .long SDR_1
SDR_L_A: .long SDR_2
EMRS_A: .long 0xFEC02000
MRS1_A: .long 0xFEC00B08
MRS2_A: .long 0xFEC00308
MIM_U_D: .long 0x00004000
MIM_L_D0: .long 0x03e80009
MIM_L_D1: .long 0x03e80209
SCR_L_D0: .long 0x3
SCR_L_D1: .long 0x2
SCR_L_D2: .long 0x2
SCR_L_D3: .long 0x4
SCR_L_D4: .long 0x4
SCR_L_D5: .long 0x0
STR_L_D: .long 0x000f0000
SDR_L_D: .long 0x00000400
EMRS_D: .long 0x0
MRS1_D: .long 0x0
MRS2_D: .long 0x0
MIM_U_A: .long MIM_1
MIM_L_A: .long MIM_2
SCR_U_A: .long SCR_1
SCR_L_A: .long SCR_2
STR_U_A: .long STR_1
STR_L_A: .long STR_2
SDR_U_A: .long SDR_1
SDR_L_A: .long SDR_2
EMRS_A: .long 0xFEC02000
MRS1_A: .long 0xFEC00B08
MRS2_A: .long 0xFEC00308
MIM_U_D: .long 0x00004000
MIM_L_D0: .long 0x03e80009
MIM_L_D1: .long 0x03e80209
SCR_L_D0: .long 0x3
SCR_L_D1: .long 0x2
SCR_L_D2: .long 0x2
SCR_L_D3: .long 0x4
SCR_L_D4: .long 0x4
SCR_L_D5: .long 0x0
STR_L_D: .long 0x000f0000
SDR_L_D: .long 0x00000400
EMRS_D: .long 0x0
MRS1_D: .long 0x0
MRS2_D: .long 0x0
/* Cache Controller */
CCR_A: .long CCR
MMUCR_A: .long MMUCR
RWTCNT_A: .long WTCNT
CCR_A: .long CCR
MMUCR_A: .long MMUCR
RWTCNT_A: .long WTCNT
CCR_D: .long 0x0000090b
CCR_D_2: .long 0x00000103
MMUCR_D: .long 0x00000004
MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
CCR_D: .long 0x0000090b
CCR_D_2: .long 0x00000103
MMUCR_D: .long 0x00000004
MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
/* local Bus State Controller */
MMSELR_A: .long MMSELR
BCR_A: .long BCR
CS0BCR_A: .long CS0BCR
CS1BCR_A: .long CS1BCR
CS2BCR_A: .long CS2BCR
CS4BCR_A: .long CS4BCR
CS5BCR_A: .long CS5BCR
CS6BCR_A: .long CS6BCR
CS0WCR_A: .long CS0WCR
CS1WCR_A: .long CS1WCR
CS2WCR_A: .long CS2WCR
CS4WCR_A: .long CS4WCR
CS5WCR_A: .long CS5WCR
CS6WCR_A: .long CS6WCR
CS5PCR_A: .long CS5PCR
CS6PCR_A: .long CS6PCR
MMSELR_A: .long MMSELR
BCR_A: .long BCR
CS0BCR_A: .long CS0BCR
CS1BCR_A: .long CS1BCR
CS2BCR_A: .long CS2BCR
CS4BCR_A: .long CS4BCR
CS5BCR_A: .long CS5BCR
CS6BCR_A: .long CS6BCR
CS0WCR_A: .long CS0WCR
CS1WCR_A: .long CS1WCR
CS2WCR_A: .long CS2WCR
CS4WCR_A: .long CS4WCR
CS5WCR_A: .long CS5WCR
CS6WCR_A: .long CS6WCR
CS5PCR_A: .long CS5PCR
CS6PCR_A: .long CS6PCR
MMSELR_D: .long 0xA5A50003
BCR_D: .long 0x00000000
@ -425,5 +425,5 @@ CS6WCR_D: .long 0x77777703
CS5PCR_D: .long 0x77000000
CS6PCR_D: .long 0x77000000
REPEAT0_R3: .long 0x00002000
REPEAT0_R1: .long 0x0000200
REPEAT0_R3: .long 0x00002000
REPEAT0_R1: .long 0x0000200

214
board/renesas/rsk7203/lowlevel_init.S
Unescape View File

@ -29,153 +29,153 @@
lowlevel_init:
/* Cache setting */
mov.l CCR1_A ,r1
mov.l CCR1_D ,r0
mov.l r0,@r1
mov.l CCR1_A, r1
mov.l CCR1_D, r0
mov.l r0, @r1
/* ConfigurePortPins */
mov.l PECRL3_A, r1
mov.l PECRL3_D, r0
mov.w r0,@r1
mov.l PECRL3_A, r1
mov.l PECRL3_D, r0
mov.w r0, @r1
mov.l PCCRL4_A, r1
mov.l PCCRL4_D0, r0
mov.w r0,@r1
mov.l PCCRL4_A, r1
mov.l PCCRL4_D0, r0
mov.w r0, @r1
mov.l PECRL4_A, r1
mov.l PECRL4_D0, r0
mov.w r0,@r1
mov.l PECRL4_A, r1
mov.l PECRL4_D0, r0
mov.w r0, @r1
mov.l PEIORL_A, r1
mov.l PEIORL_D0, r0
mov.w r0,@r1
mov.l PEIORL_A, r1
mov.l PEIORL_D0, r0
mov.w r0, @r1
mov.l PCIORL_A, r1
mov.l PCIORL_D, r0
mov.w r0,@r1
mov.l PCIORL_A, r1
mov.l PCIORL_D, r0
mov.w r0, @r1
mov.l PFCRH2_A, r1
mov.l PFCRH2_D, r0
mov.w r0,@r1
mov.l PFCRH2_A, r1
mov.l PFCRH2_D, r0
mov.w r0, @r1
mov.l PFCRH3_A, r1
mov.l PFCRH3_D, r0
mov.w r0,@r1
mov.l PFCRH3_A, r1
mov.l PFCRH3_D, r0
mov.w r0, @r1
mov.l PFCRH1_A, r1
mov.l PFCRH1_D, r0
mov.w r0,@r1
mov.l PFCRH1_A, r1
mov.l PFCRH1_D, r0
mov.w r0, @r1
mov.l PFIORH_A, r1
mov.l PFIORH_D, r0
mov.w r0,@r1
mov.l PFIORH_A, r1
mov.l PFIORH_D, r0
mov.w r0, @r1
mov.l PECRL1_A, r1
mov.l PECRL1_D0, r0
mov.w r0,@r1
mov.l PECRL1_A, r1
mov.l PECRL1_D0, r0
mov.w r0, @r1
mov.l PEIORL_A, r1
mov.l PEIORL_D1, r0
mov.w r0,@r1
mov.l PEIORL_A, r1
mov.l PEIORL_D1, r0
mov.w r0, @r1
/* Configure Operating Frequency */
mov.l WTCSR_A ,r1
mov.l WTCSR_D0 ,r0
mov.w r0,@r1
mov.l WTCSR_A, r1
mov.l WTCSR_D0, r0
mov.w r0, @r1
mov.l WTCSR_A ,r1
mov.l WTCSR_D1 ,r0
mov.w r0,@r1
mov.l WTCSR_A, r1
mov.l WTCSR_D1, r0
mov.w r0, @r1
mov.l WTCNT_A ,r1
mov.l WTCNT_D ,r0
mov.w r0,@r1
mov.l WTCNT_A, r1
mov.l WTCNT_D, r0
mov.w r0, @r1
/* Set clock mode*/
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.w r0,@r1
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.w r0, @r1
/* Configure Bus And Memory */
init_bsc_cs0:
mov.l PCCRL4_A,r1
mov.l PCCRL4_D1,r0
mov.w r0,@r1
mov.l PCCRL4_A, r1
mov.l PCCRL4_D1, r0
mov.w r0, @r1
mov.l PECRL1_A,r1
mov.l PECRL1_D1,r0
mov.w r0,@r1
mov.l PECRL1_A, r1
mov.l PECRL1_D1, r0
mov.w r0, @r1
mov.l CMNCR_A,r1
mov.l CMNCR_D,r0
mov.l r0,@r1
mov.l CMNCR_A, r1
mov.l CMNCR_D, r0
mov.l r0, @r1
mov.l SC0BCR_A,r1
mov.l SC0BCR_D,r0
mov.l r0,@r1
mov.l SC0BCR_A, r1
mov.l SC0BCR_D, r0
mov.l r0, @r1
mov.l CS0WCR_A,r1
mov.l CS0WCR_D,r0
mov.l r0,@r1
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
init_bsc_cs1:
mov.l PECRL4_A,r1
mov.l PECRL4_D1,r0
mov.w r0,@r1
mov.l PECRL4_A, r1
mov.l PECRL4_D1, r0
mov.w r0, @r1
mov.l CS1WCR_A,r1
mov.l CS1WCR_D,r0
mov.l r0,@r1
mov.l CS1WCR_A, r1
mov.l CS1WCR_D, r0
mov.l r0, @r1
init_sdram:
mov.l PCCRL2_A,r1
mov.l PCCRL2_D,r0
mov.w r0,@r1
mov.l PCCRL2_A, r1
mov.l PCCRL2_D, r0
mov.w r0, @r1
mov.l PCCRL4_A,r1
mov.l PCCRL4_D2,r0
mov.w r0,@r1
mov.l PCCRL4_A, r1
mov.l PCCRL4_D2, r0
mov.w r0, @r1
mov.l PCCRL1_A,r1
mov.l PCCRL1_D,r0
mov.w r0,@r1
mov.l PCCRL1_A, r1
mov.l PCCRL1_D, r0
mov.w r0, @r1
mov.l PCCRL3_A,r1
mov.l PCCRL3_D,r0
mov.w r0,@r1
mov.l PCCRL3_A, r1
mov.l PCCRL3_D, r0
mov.w r0, @r1
mov.l CS3BCR_A,r1
mov.l CS3BCR_D,r0
mov.l r0,@r1
mov.l CS3BCR_A, r1
mov.l CS3BCR_D, r0
mov.l r0, @r1
mov.l CS3WCR_A,r1
mov.l CS3WCR_D,r0
mov.l r0,@r1
mov.l CS3WCR_A, r1
mov.l CS3WCR_D, r0
mov.l r0, @r1
mov.l SDCR_A,r1
mov.l SDCR_D,r0
mov.l r0,@r1
mov.l SDCR_A, r1
mov.l SDCR_D, r0
mov.l r0, @r1
mov.l RTCOR_A,r1
mov.l RTCOR_D,r0
mov.l r0,@r1
mov.l RTCOR_A, r1
mov.l RTCOR_D, r0
mov.l r0, @r1
mov.l RTCSR_A,r1
mov.l RTCSR_D,r0
mov.l r0,@r1
mov.l RTCSR_A, r1
mov.l RTCSR_D, r0
mov.l r0, @r1
/* wait 200us */
mov.l REPEAT_D,r3
mov #0,r2
mov.l REPEAT_D, r3
mov #0, r2
repeat0:
add #1,r2
cmp/hs r3,r2
bf repeat0
add #1, r2
cmp/hs r3, r2
bf repeat0
nop
mov.l SDRAM_MODE, r1
mov #0,r0
mov.l r0, @r1
mov.l SDRAM_MODE, r1
mov #0, r0
mov.l r0, @r1
nop
rts
@ -208,8 +208,8 @@ PECRL1_D0: .long 0x00000033
WTCSR_A: .long 0xFFFE0000
WTCSR_D0: .long 0x0000A518
WTCSR_D1: .long 0x0000A51D
WTCSR_D0: .long 0x0000A518
WTCSR_D1: .long 0x0000A51D
WTCNT_A: .long 0xFFFE0002
WTCNT_D: .long 0x00005A84
FRQCR_A: .long 0xFFFE0010
@ -259,7 +259,7 @@ STBCR4_A: .long 0xFFFE040C
STBCR4_D: .long 0x00000008
STBCR5_A: .long 0xFFFE0410
STBCR5_D: .long 0x00000000
STBCR6_A: .long 0xFFFE0414
STBCR6_A: .long 0xFFFE0414
STBCR6_D: .long 0x00000002
SDRAM_MODE: .long 0xFFFC5040
REPEAT_D: .long 0x00009C40

162
board/renesas/sh7763rdp/lowlevel_init.S
Unescape View File

@ -33,17 +33,17 @@
lowlevel_init:
mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */
mov.l WDTCSR_D, r0
mov.l r0, @r1
mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */
mov.l WDTCSR_D, r0
mov.l r0, @r1
mov.l WDTST_A, r1 /* Watchdog Stop Time Register */
mov.l WDTST_D, r0
mov.l r0, @r1
mov.l WDTST_A, r1 /* Watchdog Stop Time Register */
mov.l WDTST_D, r0
mov.l r0, @r1
mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */
mov.l WDTBST_D, r0
mov.l r0, @r1
mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */
mov.l WDTBST_D, r0
mov.l r0, @r1
mov.l CCR_A, r1 /* Address of Cache Control Register */
mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */
@ -61,107 +61,107 @@ lowlevel_init:
mov.l MSTPCR1_D, r0
mov.l r0, @r1
mov.l RAMCR_A,r1
mov.l RAMCR_D,r0
mov.l RAMCR_A, r1
mov.l RAMCR_D, r0
mov.l r0, @r1
mov.l MMSELR_A,r1
mov.l MMSELR_D,r0
mov.l MMSELR_A, r1
mov.l MMSELR_D, r0
synco
mov.l r0, @r1
mov.l @r1,r2 /* execute two reads after setting MMSELR*/
mov.l @r1,r2
mov.l @r1, r2 /* execute two reads after setting MMSELR*/
mov.l @r1, r2
synco
/* issue memory read */
mov.l DDRSD_START_A,r1 /* memory address to read*/
mov.l @r1,r0
mov.l DDRSD_START_A, r1 /* memory address to read*/
mov.l @r1, r0
synco
mov.l MIM8_A,r1
mov.l MIM8_D,r0
mov.l r0,@r1
mov.l MIM8_A, r1
mov.l MIM8_D, r0
mov.l r0, @r1
mov.l MIMC_A,r1
mov.l MIMC_D1,r0
mov.l r0,@r1
mov.l MIMC_A, r1
mov.l MIMC_D1, r0
mov.l r0, @r1
mov.l STRC_A,r1
mov.l STRC_D,r0
mov.l r0,@r1
mov.l STRC_A, r1
mov.l STRC_D, r0
mov.l r0, @r1
mov.l SDR4_A,r1
mov.l SDR4_D,r0
mov.l r0,@r1
mov.l SDR4_A, r1
mov.l SDR4_D, r0
mov.l r0, @r1
mov.l MIMC_A,r1
mov.l MIMC_D2,r0
mov.l r0,@r1
mov.l MIMC_A, r1
mov.l MIMC_D2, r0
mov.l r0, @r1
nop
nop
nop
mov.l SCR4_A,r1
mov.l SCR4_D3,r0
mov.l r0,@r1
mov.l SCR4_A, r1
mov.l SCR4_D3, r0
mov.l r0, @r1
mov.l SCR4_A,r1
mov.l SCR4_D2,r0
mov.l r0,@r1
mov.l SCR4_A, r1
mov.l SCR4_D2, r0
mov.l r0, @r1
mov.l SDMR02000_A,r1
mov.l SDMR02000_D,r0
mov.l r0,@r1
mov.l SDMR02000_A, r1
mov.l SDMR02000_D, r0
mov.l r0, @r1
mov.l SDMR00B08_A,r1
mov.l SDMR00B08_D,r0
mov.l r0,@r1
mov.l SDMR00B08_A, r1
mov.l SDMR00B08_D, r0
mov.l r0, @r1
mov.l SCR4_A,r1
mov.l SCR4_D2,r0
mov.l r0,@r1
mov.l SCR4_A, r1
mov.l SCR4_D2, r0
mov.l r0, @r1
mov.l SCR4_A,r1
mov.l SCR4_D4,r0
mov.l r0,@r1
mov.l SCR4_A, r1
mov.l SCR4_D4, r0
mov.l r0, @r1
nop
nop
nop
nop
mov.l SCR4_A,r1
mov.l SCR4_D4,r0
mov.l r0,@r1
mov.l SCR4_A, r1
mov.l SCR4_D4, r0
mov.l r0, @r1
nop
nop
nop
nop
mov.l SDMR00308_A,r1
mov.l SDMR00308_D,r0
mov.l r0,@r1
mov.l SDMR00308_A, r1
mov.l SDMR00308_D, r0
mov.l r0, @r1
mov.l MIMC_A,r1
mov.l MIMC_D3,r0
mov.l r0,@r1
mov.l MIMC_A, r1
mov.l MIMC_D3, r0
mov.l r0, @r1
mov.l SCR4_A,r1
mov.l SCR4_D1,r0
mov.l DELAY60_D,r3
mov.l SCR4_A, r1
mov.l SCR4_D1, r0
mov.l DELAY60_D, r3
delay_loop_60:
mov.l r0,@r1
mov.l r0, @r1
dt r3
bf delay_loop_60
nop
mov.l CCR_A, r1 /* Address of Cache Control Register */
mov.l CCR_CACHE_D_2, r0
mov.l r0, @r1
mov.l CCR_A, r1 /* Address of Cache Control Register */
mov.l CCR_CACHE_D_2, r0
mov.l r0, @r1
bsc_init:
mov.l BCR_A, r1
@ -172,9 +172,9 @@ bsc_init:
mov.l CS0BCR_D, r0
mov.l r0, @r1
mov.l CS1BCR_A,r1
mov.l CS1BCR_D,r0
mov.l r0,@r1
mov.l CS1BCR_A, r1
mov.l CS1BCR_D, r0
mov.l r0, @r1
mov.l CS2BCR_A, r1
mov.l CS2BCR_D, r0
@ -224,27 +224,27 @@ bsc_init:
mov.l CS6PCR_D, r0
mov.l r0, @r1
mov.l DELAY200_D,r3
mov.l DELAY200_D, r3
delay_loop_200:
dt r3
bf delay_loop_200
nop
mov.l PSEL0_A,r1
mov.l PSEL0_D,r0
mov.w r0,@r1
mov.l PSEL0_A, r1
mov.l PSEL0_D, r0
mov.w r0, @r1
mov.l PSEL1_A,r1
mov.l PSEL1_D,r0
mov.w r0,@r1
mov.l PSEL1_A, r1
mov.l PSEL1_D, r0
mov.w r0, @r1
mov.l ICR0_A,r1
mov.l ICR0_D,r0
mov.l r0,@r1
mov.l ICR0_A, r1
mov.l ICR0_D, r0
mov.l r0, @r1
stc sr, r0 /* BL bit off(init=ON) */
mov.l SR_MASK_D, r1
mov.l SR_MASK_D, r1
and r1, r0
ldc r0, sr
@ -321,7 +321,7 @@ CS4BCR_D: .long 0x77777670
CS5BCR_D: .long 0x77777670
CS6BCR_D: .long 0x77777670
CS0WCR_D: .long 0x7777770F
CS1WCR_D: .long 0x22000002
CS1WCR_D: .long 0x22000002
CS2WCR_D: .long 0x7777770F
CS4WCR_D: .long 0x7777770F
CS5WCR_D: .long 0x7777770F

2
board/renesas/sh7785lcr/lowlevel_init.S
Unescape View File

@ -305,7 +305,7 @@ CS4WCR_D: .long 0x00101012
CS_USB_BCR_D: .long 0x11111200
CS_USB_WCR_D: .long 0x00020004
/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
CS_SD_BCR_D: .long 0x00000300
CS_SD_WCR_D: .long 0x00030108

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