sh: lowlevel_init coding style cleanup

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

board/mpr2/lowlevel_init.S

@@ -112,21 +112,27 @@ WTCSR_D:	.long	0xA507		/* divide by 4096 */
 /*
  * Spansion S29GL256N11 @ 48 MHz
  */
-CS0BCR_D:	.long	0x12490400  /* 1 idle cycle inserted, normal space, 16 bit */
-CS0WCR_D:	.long	0x00000340  /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+/* 1 idle cycle inserted, normal space, 16 bit */
+CS0BCR_D:	.long	0x12490400
+/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+CS0WCR_D:	.long	0x00000340
 
 /*
  * Samsung K4S511632B-UL75 @ 48 MHz
  * Micron MT48LC32M16A2-75 @ 48 MHz
  */
-CS3BCR_D:	.long	0x10004400  /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
-CS3WCR_D:	.long	0x00000091  /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
-SDCR_D1:	.long	0x00000012  /* no refresh, 13 rows, 10 cols, NO bank active mode */
+/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
+CS3BCR_D:	.long	0x10004400
+/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
+CS3WCR_D:	.long	0x00000091
+/* no refresh, 13 rows, 10 cols, NO bank active mode */
+SDCR_D1:	.long	0x00000012
 SDCR_D2:	.long	0x00000812	/* refresh */
 RTCSR_D:	.long	0xA55A0008	/* 1/4, once */
 RTCNT_D:	.long	0xA55A005D	/* count 93 */
 RTCOR_D:	.long	0xa55a005d	/* count 93 */
-SDMR3_D:	.long	0x440       /* mode register CL2, burst read and SINGLE WRITE */
+/* mode register CL2, burst read and SINGLE WRITE */
+SDMR3_D:	.long	0x440
 
 /*
  * Registers

board/ms7750se/lowlevel_init.S

@@ -44,7 +44,7 @@
 					   A2: 1-3 A1: 1-3 A0: 0-1 */
 #define RTCOR_D_VALUE	0xA50D		/* Write code A5, data 0D (~15us?) */
 #define SDMR3_ADDRESS	0xFF940088	/* SDMR3 address on 32-bit bus */
-#define MCR_D1_VALUE	0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
+#define MCR_D1_VALUE	0x100901B4	/* SDRAM 32-bit, CAS/RAS Refresh, .. */
 #define MCR_D2_VALUE	0x500901B4	/* Same w/MRSET now 1 (mode reg cmd) */
 #else /* CONFIG_CPU_SH7751 */
 #define BCR2_D_VALUE	0x2E3C		/* Area 1-6 width: 32/32/64/16/32/16 */
@@ -55,7 +55,7 @@
 					   A2: 1-3 A1: 1-3 A0: 0-1 */
 #define RTCOR_D_VALUE	0xA510		/* Write code A5, data 10 (~15us?) */
 #define SDMR3_ADDRESS	0xFF940110	/* SDMR3 address on 64-bit bus */
-#define MCR_D1_VALUE	0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
+#define MCR_D1_VALUE	0x8801001C	/* SDRAM 64-bit, CAS/RAS Refresh, .. */
 #define MCR_D2_VALUE	0xC801001C	/* Same w/MRSET now 1 (mode reg cmd) */
 #endif /* CONFIG_CPU_SH7751 */