Qemu emulates the Galileo GT64120 System Controller which provides a CPU bus to PCI bus bridge. The patch adds driver for this bridge and enables PCI support for the emulated Malta board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>master
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/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
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* |
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* Based on the Linux implementation. |
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* Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. |
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* Authors: Carsten Langgaard <carstenl@mips.com> |
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* Maciej W. Rozycki <macro@mips.com> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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* by the Free Software Foundation. |
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*/ |
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#include <common.h> |
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#include <gt64120.h> |
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#include <pci.h> |
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#include <pci_gt64120.h> |
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#include <asm/io.h> |
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#define PCI_ACCESS_READ 0 |
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#define PCI_ACCESS_WRITE 1 |
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struct gt64120_regs { |
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u8 unused_000[0xc18]; |
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u32 intrcause; |
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u8 unused_c1c[0x0dc]; |
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u32 pci0_cfgaddr; |
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u32 pci0_cfgdata; |
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}; |
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struct gt64120_pci_controller { |
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struct pci_controller hose; |
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struct gt64120_regs *regs; |
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}; |
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static inline struct gt64120_pci_controller * |
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hose_to_gt64120(struct pci_controller *hose) |
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{ |
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return container_of(hose, struct gt64120_pci_controller, hose); |
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} |
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#define GT_INTRCAUSE_ABORT_BITS \ |
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(GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT) |
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static int gt_config_access(struct gt64120_pci_controller *gt, |
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unsigned char access_type, pci_dev_t bdf, |
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int where, u32 *data) |
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{ |
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unsigned int bus = PCI_BUS(bdf); |
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unsigned int dev = PCI_DEV(bdf); |
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unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf); |
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u32 intr; |
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u32 addr; |
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u32 val; |
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if (bus == 0 && dev >= 31) { |
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/* Because of a bug in the galileo (for slot 31). */ |
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return -1; |
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} |
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if (access_type == PCI_ACCESS_WRITE) |
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debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n", |
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data); |
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/* Clear cause register bits */ |
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writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause); |
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addr = GT_PCI0_CFGADDR_CONFIGEN_BIT; |
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addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF; |
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addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF; |
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addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF; |
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/* Setup address */ |
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writel(addr, >->regs->pci0_cfgaddr); |
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if (access_type == PCI_ACCESS_WRITE) { |
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if (bus == 0 && dev == 0) { |
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/*
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* The Galileo system controller is acting |
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* differently than other devices. |
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*/ |
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val = *data; |
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} else { |
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val = cpu_to_le32(*data); |
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} |
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writel(val, >->regs->pci0_cfgdata); |
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} else { |
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val = readl(>->regs->pci0_cfgdata); |
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if (bus == 0 && dev == 0) { |
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/*
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* The Galileo system controller is acting |
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* differently than other devices. |
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*/ |
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*data = val; |
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} else { |
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*data = le32_to_cpu(val); |
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} |
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} |
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/* Check for master or target abort */ |
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intr = readl(>->regs->intrcause); |
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if (intr & GT_INTRCAUSE_ABORT_BITS) { |
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/* Error occurred, clear abort bits */ |
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writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause); |
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return -1; |
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} |
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if (access_type == PCI_ACCESS_READ) |
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debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n", |
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data); |
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return 0; |
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} |
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static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev, |
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int where, u32 *value) |
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{ |
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struct gt64120_pci_controller *gt = hose_to_gt64120(hose); |
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*value = 0xffffffff; |
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return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value); |
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} |
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static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev, |
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int where, u32 value) |
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{ |
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struct gt64120_pci_controller *gt = hose_to_gt64120(hose); |
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u32 data = value; |
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return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data); |
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} |
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void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys, |
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unsigned long sys_size, unsigned long mem_bus, |
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unsigned long mem_phys, unsigned long mem_size, |
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unsigned long io_bus, unsigned long io_phys, |
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unsigned long io_size) |
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{ |
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static struct gt64120_pci_controller global_gt; |
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struct gt64120_pci_controller *gt; |
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struct pci_controller *hose; |
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gt = &global_gt; |
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gt->regs = regs; |
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hose = >->hose; |
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hose->first_busno = 0; |
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hose->last_busno = 0; |
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/* System memory space */ |
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pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size, |
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
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/* PCI memory space */ |
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pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size, |
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PCI_REGION_MEM); |
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/* PCI I/O space */ |
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pci_set_region(&hose->regions[2], io_bus, io_phys, io_size, |
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PCI_REGION_IO); |
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hose->region_count = 3; |
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pci_set_ops(hose, |
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pci_hose_read_config_byte_via_dword, |
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pci_hose_read_config_word_via_dword, |
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gt_read_config_dword, |
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pci_hose_write_config_byte_via_dword, |
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pci_hose_write_config_word_via_dword, |
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gt_write_config_dword); |
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pci_register_hose(hose); |
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hose->last_busno = pci_hose_scan(hose); |
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} |
@ -0,0 +1,19 @@ |
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/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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* by the Free Software Foundation. |
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*/ |
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#ifndef _PCI_GT64120_H |
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#define _PCI_GT64120_H |
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void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys, |
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unsigned long sys_size, unsigned long mem_bus, |
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unsigned long mem_phys, unsigned long mem_size, |
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unsigned long io_bus, unsigned long io_phys, |
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unsigned long io_size); |
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#endif /* _PCI_GT64120_H */ |
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