The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
instruction which means "Invalidate Both Caches" when in fact the intent
is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7,
c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate
Both Caches" instruction to insure that memory is consistent with any
dirty cache lines.
Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
used.
Signed-off-by: George G. Davis <gdavis@mvista.com>
all arm init the IRQ stack the same way
so unify it in lib_arm/interrupts.c and then call arch specific interrupt init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
add support for the TI OMAP2420 processor and its H4 reference
board
* Patch by Christian Pellegrin, 24 Sep 2004:
Added support for NE2000 compatible (DP8390, DP83902) NICs.
ARM memory layout fixes: the abort-stack is now set up in the
correct RAM area, and the BSS is zeroed out as it should be.
Furthermore, the magic variables 'armboot_end' and 'armboot_end_data'
of the linker scripts are replaced by '__bss_start' and '_end',
resp., which is a further step to eliminate unnecessary differences
between the implementation of the CPU architectures.
Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c
* Patch by Anders Larsen, 17 Sep 2003:
Bring ARM memory layout in sync with the documentation:
stack and malloc-heap are now located _below_ the U-Boot code
George G. Davis
Peter Tyser
Jean-Christophe PLAGNIOL-VILLARD
Detlev Zundel
Sascha Hauer
Wolfgang Denk
Wolfgang Denk
wdenk