@ -90,8 +90,8 @@
# define DMADone (1<<8) # define DMADone (1<<8)
# define DownComplete (1<<9) # define DownComplete (1<<9)
# define UpComplete (1<<10) # define UpComplete (1<<10)
# define DMAInProgress (1<<11) /* DMA controller is still busy.*/ # define DMAInProgress (1<<11) /* DMA controller is still busy.*/
# define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ # define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
/* Polling Registers */ /* Polling Registers */
@ -100,17 +100,17 @@
/* Register window 0 offets */ /* Register window 0 offets */
# define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ # define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
# define Wn0EepromData 12 /* Window 0: EEPROM results register. */ # define Wn0EepromData 12 /* Window 0: EEPROM results register. */
# define IntrStatus 0x0E /* Valid in all windows. */ # define IntrStatus 0x0E /* Valid in all windows. */
/* Register window 0 EEPROM bits */ /* Register window 0 EEPROM bits */
# define EEPROM_Read 0x80 # define EEPROM_Read 0x80
# define EEPROM_WRITE 0x40 # define EEPROM_WRITE 0x40
# define EEPROM_ERASE 0xC0 # define EEPROM_ERASE 0xC0
# define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ # define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
# define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ # define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
/* EEPROM locations. */ /* EEPROM locations. */
@ -135,7 +135,7 @@
# define RxStatus 0x18 # define RxStatus 0x18
# define Timer 0x1A # define Timer 0x1A
# define TxStatus 0x1B # define TxStatus 0x1B
# define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ # define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
/* Register Window 2 */ /* Register Window 2 */
@ -143,23 +143,23 @@
/* Register Window 3: MAC/config bits */ /* Register Window 3: MAC/config bits */
# define Wn3_Config 0 /* Internal Configuration */ # define Wn3_Config 0 /* Internal Configuration */
# define Wn3_MAC_Ctrl 6 # define Wn3_MAC_Ctrl 6
# define Wn3_Options 8 # define Wn3_Options 8
# define BFEXT(value, offset, bitcount) \ # define BFEXT(value, offset, bitcount) \
( ( ( ( unsigned long ) ( value ) ) > > ( offset ) ) & ( ( 1 < < ( bitcount ) ) - 1 ) ) ( ( ( ( unsigned long ) ( value ) ) > > ( offset ) ) & ( ( 1 < < ( bitcount ) ) - 1 ) )
# define BFINS(lhs, rhs, offset, bitcount) \ # define BFINS(lhs, rhs, offset, bitcount) \
( ( ( lhs ) & ~ ( ( ( ( 1 < < ( bitcount ) ) - 1 ) ) < < ( offset ) ) ) | \
( ( ( lhs ) & ~ ( ( ( ( 1 < < ( bitcount ) ) - 1 ) ) < < ( offset ) ) ) | \
( ( ( rhs ) & ( ( 1 < < ( bitcount ) ) - 1 ) ) < < ( offset ) ) ) ( ( ( rhs ) & ( ( 1 < < ( bitcount ) ) - 1 ) ) < < ( offset ) ) )
# define RAM_SIZE(v) BFEXT(v, 0, 3) # define RAM_SIZE(v) BFEXT(v, 0, 3)
# define RAM_WIDTH(v) BFEXT(v, 3, 1) # define RAM_WIDTH(v) BFEXT(v, 3, 1)
# define RAM_SPEED(v) BFEXT(v, 4, 2) # define RAM_SPEED(v) BFEXT(v, 4, 2)
# define ROM_SIZE(v) BFEXT(v, 6, 2) # define ROM_SIZE(v) BFEXT(v, 6, 2)
# define RAM_SPLIT(v) BFEXT(v, 16, 2) # define RAM_SPLIT(v) BFEXT(v, 16, 2)
# define XCVR(v) BFEXT(v, 20, 4) # define XCVR(v) BFEXT(v, 20, 4)
# define AUTOSELECT(v) BFEXT(v, 24, 1) # define AUTOSELECT(v) BFEXT(v, 24, 1)
/* Register Window 4: Xcvr/media bits */ /* Register Window 4: Xcvr/media bits */
@ -186,20 +186,20 @@
# define DownListPtr 0x24 # define DownListPtr 0x24
# define FragAddr 0x28 # define FragAddr 0x28
# define FragLen 0x2c # define FragLen 0x2c
# define TxFreeThreshold 0x2f # define TxFreeThreshold 0x2f
# define UpPktStatus 0x30 # define UpPktStatus 0x30
# define UpListPtr 0x38 # define UpListPtr 0x38
/* The Rx and Tx descriptor lists. */ /* The Rx and Tx descriptor lists. */
# define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ # define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
# define DN_COMPLETE 0x00010000 /* This packet has been downloaded */ # define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
struct rx_desc_3com { struct rx_desc_3com {
u32 next ; /* Last entry points to 0 */ u32 next ; /* Last entry points to 0 */
u32 status ; /* FSH -> Frame Start Header */ u32 status ; /* FSH -> Frame Start Header */
u32 addr ; /* Up to 63 addr/len pairs possible */ u32 addr ; /* Up to 63 addr/len pairs possible */
u32 length ; /* Set LAST_FRAG to indicate last pair */ u32 length ; /* Set LAST_FRAG to indicate last pair */
} ; } ;
/* Values for the Rx status entry. */ /* Values for the Rx status entry. */
@ -214,8 +214,8 @@ struct rx_desc_3com {
# define UDPChksumValid (1<<31) # define UDPChksumValid (1<<31)
struct tx_desc_3com { struct tx_desc_3com {
u32 next ; /* Last entry points to 0 */ u32 next ; /* Last entry points to 0 */
u32 status ; /* bits 0:12 length, others see below */ u32 status ; /* bits 0:12 length, others see below */
u32 addr ; u32 addr ;
u32 length ; u32 length ;
} ; } ;
@ -227,7 +227,7 @@ struct tx_desc_3com {
# define AddIPChksum 0x02000000 # define AddIPChksum 0x02000000
# define AddTCPChksum 0x04000000 # define AddTCPChksum 0x04000000
# define AddUDPChksum 0x08000000 # define AddUDPChksum 0x08000000
# define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */ # define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */
/* XCVR Types */ /* XCVR Types */
@ -240,19 +240,19 @@ struct tx_desc_3com {
# define XCVR_MII 6 # define XCVR_MII 6
# define XCVR_NWAY 8 # define XCVR_NWAY 8
# define XCVR_ExtMII 9 # define XCVR_ExtMII 9
# define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */ # define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
struct descriptor { /* A generic descriptor. */ struct descriptor { /* A generic descriptor. */
u32 next ; /* Last entry points to 0 */ u32 next ; /* Last entry points to 0 */
u32 status ; /* FSH -> Frame Start Header */ u32 status ; /* FSH -> Frame Start Header */
u32 addr ; /* Up to 63 addr/len pairs possible */ u32 addr ; /* Up to 63 addr/len pairs possible */
u32 length ; /* Set LAST_FRAG to indicate last pair */ u32 length ; /* Set LAST_FRAG to indicate last pair */
} ; } ;
/* Misc. definitions */ /* Misc. definitions */
# define NUM_RX_DESC PKTBUFSRX * 10 # define NUM_RX_DESC PKTBUFSRX * 10
# define NUM_TX_DESC 1 /* Number of TX descriptors */ # define NUM_TX_DESC 1 /* Number of TX descriptors */
# define TOUT_LOOP 1000000 # define TOUT_LOOP 1000000
@ -266,17 +266,17 @@ struct descriptor { /* A generic descriptor. */
# undef ETH_DEBUG # undef ETH_DEBUG
# ifdef ETH_DEBUG # ifdef ETH_DEBUG
# define PRINTF(fmt,args...) printf (fmt ,##args) # define PRINTF(fmt,args...) printf (fmt ,##args)
# else # else
# define PRINTF(fmt,args...) # define PRINTF(fmt,args...)
# endif # endif
static struct rx_desc_3com * rx_ring ; /* RX descriptor ring */ static struct rx_desc_3com * rx_ring ; /* RX descriptor ring */
static struct tx_desc_3com * tx_ring ; /* TX descriptor ring */ static struct tx_desc_3com * tx_ring ; /* TX descriptor ring */
static u8 rx_buffer [ NUM_RX_DESC ] [ PKTSIZE_ALIGN ] ; /* storage for the incoming messages */ static u8 rx_buffer [ NUM_RX_DESC ] [ PKTSIZE_ALIGN ] ; /* storage for the incoming messages */
static int rx_next = 0 ; /* RX descriptor ring pointer */ static int rx_next = 0 ; /* RX descriptor ring pointer */
static int tx_next = 0 ; /* TX descriptor ring pointer */ static int tx_next = 0 ; /* TX descriptor ring pointer */
static int tx_threshold ; static int tx_threshold ;
static void init_rx_ring ( struct eth_device * dev ) ; static void init_rx_ring ( struct eth_device * dev ) ;
@ -369,171 +369,163 @@ static int issue_and_wait(struct eth_device* dev, int command)
return 0 ; return 0 ;
} }
/* Determine network media type and set up 3com accordingly */ /* Determine network media type and set up 3com accordingly */
/* I think I'm going to start with something known first like 10baseT */ /* I think I'm going to start with something known first like 10baseT */
static int auto_negotiate ( struct eth_device * dev ) static int auto_negotiate ( struct eth_device * dev )
{ {
int i ; int i ;
EL3WINDOW ( dev , 1 ) ; EL3WINDOW ( dev , 1 ) ;
/* Wait for Auto negotiation to complete */ /* Wait for Auto negotiation to complete */
for ( i = 0 ; i < = 1000 ; i + + ) for ( i = 0 ; i < = 1000 ; i + + ) {
{ if ( ETH_INW ( dev , 2 ) & 0x04 )
if ( ETH_INW ( dev , 2 ) & 0x04 ) break ;
break ; udelay ( 100 ) ;
udelay ( 100 ) ;
if ( i = = 1000 ) if ( i = = 1000 ) {
{ PRINTF ( " Error: Auto negotiation failed \n " ) ;
PRINTF ( " Error: Auto negotiation failed \n " ) ; return 0 ;
return 0 ; }
} }
}
return 1 ; return 1 ;
} }
void eth_interrupt ( struct eth_device * dev ) void eth_interrupt ( struct eth_device * dev )
{ {
u16 status = ETH_STATUS ( dev ) ; u16 status = ETH_STATUS ( dev ) ;
printf ( " eth0: status = 0x%04x \n " , status ) ; printf ( " eth0: status = 0x%04x \n " , status ) ;
if ( ! ( status & IntLatch ) ) if ( ! ( status & IntLatch ) )
return ; return ;
if ( status & ( 1 < < 6 ) ) {
ETH_CMD ( dev , AckIntr | ( 1 < < 6 ) ) ;
printf ( " Acknowledged Interrupt command \n " ) ;
}
if ( status & DownComplete ) {
ETH_CMD ( dev , AckIntr | DownComplete ) ;
printf ( " Acknowledged DownComplete \n " ) ;
}
if ( status & UpComplete ) {
ETH_CMD ( dev , AckIntr | UpComplete ) ;
printf ( " Acknowledged UpComplete \n " ) ;
}
if ( status & ( 1 < < 6 ) ) ETH_CMD ( dev , AckIntr | IntLatch ) ;
{ printf ( " Acknowledged IntLatch \n " ) ;
ETH_CMD ( dev , AckIntr | ( 1 < < 6 ) ) ;
printf ( " Acknowledged Interrupt command \n " ) ;
}
if ( status & DownComplete )
{
ETH_CMD ( dev , AckIntr | DownComplete ) ;
printf ( " Acknowledged DownComplete \n " ) ;
}
if ( status & UpComplete )
{
ETH_CMD ( dev , AckIntr | UpComplete ) ;
printf ( " Acknowledged UpComplete \n " ) ;
}
ETH_CMD ( dev , AckIntr | IntLatch ) ;
printf ( " Acknowledged IntLatch \n " ) ;
} }
int eth_3com_initialize ( bd_t * bis ) int eth_3com_initialize ( bd_t * bis )
{ {
u32 eth_iobase = 0 , status ; u32 eth_iobase = 0 , status ;
int card_number = 0 , ret ; int card_number = 0 , ret ;
struct eth_device * dev ; struct eth_device * dev ;
pci_dev_t devno ; pci_dev_t devno ;
char * s ; char * s ;
s = getenv ( " 3com_base " ) ; s = getenv ( " 3com_base " ) ;
/* Find ethernet controller on the PCI bus */ /* Find ethernet controller on the PCI bus */
if ( ( devno = pci_find_device ( PCI_VENDOR_ID_3COM , PCI_DEVICE_ID_3COM_3C905C , 0 ) ) < 0 ) if ( ( devno =
{ pci_find_device ( PCI_VENDOR_ID_3COM , PCI_DEVICE_ID_3COM_3C905C ,
PRINTF ( " Error: Cannot find the ethernet device on the PCI bus \n " ) ; 0 ) ) < 0 ) {
PRINTF ( " Error: Cannot find the ethernet device on the PCI bus \n " ) ;
goto Done ; goto Done ;
} }
if ( s ) if ( s ) {
{ unsigned long base = atoi ( s ) ;
unsigned long base = atoi ( s ) ;
pci_write_config_dword ( devno , PCI_BASE_ADDRESS_0 , base | 0x01 ) ; pci_write_config_dword ( devno , PCI_BASE_ADDRESS_0 ,
base | 0x01 ) ;
} }
ret = pci_read_config_dword ( devno , PCI_BASE_ADDRESS_0 , & eth_iobase ) ; ret = pci_read_config_dword ( devno , PCI_BASE_ADDRESS_0 , & eth_iobase ) ;
eth_iobase & = ~ 0xf ; eth_iobase & = ~ 0xf ;
PRINTF ( " eth: 3Com Found at Address: 0x%x \n " , eth_iobase ) ; PRINTF ( " eth: 3Com Found at Address: 0x%x \n " , eth_iobase ) ;
pci_write_config_dword ( devno , PCI_COMMAND , PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER ) ; pci_write_config_dword ( devno , PCI_COMMAND ,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER ) ;
/* Check if I/O accesses and Bus Mastering are enabled */ /* Check if I/O accesses and Bus Mastering are enabled */
ret = pci_read_config_dword ( devno , PCI_COMMAND , & status ) ; ret = pci_read_config_dword ( devno , PCI_COMMAND , & status ) ;
if ( ! ( status & PCI_COMMAND_IO ) ) if ( ! ( status & PCI_COMMAND_IO ) ) {
{ printf ( " Error: Cannot enable IO access. \n " ) ;
printf ( " Error: Cannot enable IO access. \n " ) ;
goto Done ; goto Done ;
} }
if ( ! ( status & PCI_COMMAND_MEMORY ) ) if ( ! ( status & PCI_COMMAND_MEMORY ) ) {
{ printf ( " Error: Cannot enable MEMORY access. \n " ) ;
printf ( " Error: Cannot enable MEMORY access. \n " ) ;
goto Done ; goto Done ;
} }
if ( ! ( status & PCI_COMMAND_MASTER ) ) if ( ! ( status & PCI_COMMAND_MASTER ) ) {
{ printf ( " Error: Cannot enable Bus Mastering. \n " ) ;
printf ( " Error: Cannot enable Bus Mastering. \n " ) ;
goto Done ; goto Done ;
} }
dev = ( struct eth_device * ) malloc ( sizeof ( * dev ) ) ; /*struct eth_device)); */ dev = ( struct eth_device * ) malloc ( sizeof ( * dev ) ) ; /*struct eth_device)); */
sprintf ( dev - > name , " 3Com 3c920c#%d " , card_number ) ; sprintf ( dev - > name , " 3Com 3c920c#%d " , card_number ) ;
dev - > iobase = eth_iobase ; dev - > iobase = eth_iobase ;
dev - > priv = ( void * ) devno ; dev - > priv = ( void * ) devno ;
dev - > init = eth_3com_init ; dev - > init = eth_3com_init ;
dev - > halt = eth_3com_halt ; dev - > halt = eth_3com_halt ;
dev - > send = eth_3com_send ; dev - > send = eth_3com_send ;
dev - > recv = eth_3com_recv ; dev - > recv = eth_3com_recv ;
eth_register ( dev ) ; eth_register ( dev ) ;
/* { */ /* { */
/* char interrupt; */ /* char interrupt; */
/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */ /* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */ /* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */ /* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
/* irq_install_handler(interrupt, eth_interrupt, dev); */ /* irq_install_handler(interrupt, eth_interrupt, dev); */
/* } */ /* } */
card_number + + ; card_number + + ;
/* Set the latency timer for value */ /* Set the latency timer for value */
s = getenv ( " 3com_latency " ) ; s = getenv ( " 3com_latency " ) ;
if ( s ) if ( s ) {
{ ret = pci_write_config_byte ( devno , PCI_LATENCY_TIMER ,
ret = pci_write_config_byte ( devno , PCI_LATENCY_TIMER , ( unsigned char ) atoi ( s ) ) ; ( unsigned char ) atoi ( s ) ) ;
} } else
else ret = pci_write_config_byte ( devno , PCI_LATENCY_TIMER , 0x0a ) ; ret = pci_write_config_byte ( devno , PCI_LATENCY_TIMER , 0x0a ) ;
read_hw_addr ( dev , bis ) ; /* get the MAC address from Window 2*/ read_hw_addr ( dev , bis ) ; /* get the MAC address from Window 2 */
/* Reset the ethernet controller */ /* Reset the ethernet controller */
PRINTF ( " Issuing reset command.... \n " ) ; PRINTF ( " Issuing reset command.... \n " ) ;
if ( ! issue_and_wait ( dev , TotalReset ) ) if ( ! issue_and_wait ( dev , TotalReset ) ) {
{ printf ( " Error: Cannot reset ethernet controller. \n " ) ;
printf ( " Error: Cannot reset ethernet controller. \n " ) ;
goto Done ; goto Done ;
} } else
else
PRINTF ( " Ethernet controller reset. \n " ) ; PRINTF ( " Ethernet controller reset. \n " ) ;
/* allocate memory for rx and tx rings */ /* allocate memory for rx and tx rings */
if ( ! ( rx_ring = memalign ( sizeof ( struct rx_desc_3com ) * NUM_RX_DESC , 16 ) ) ) if ( ! ( rx_ring = memalign ( sizeof ( struct rx_desc_3com ) * NUM_RX_DESC , 16 ) ) ) {
{
PRINTF ( " Cannot allocate memory for RX_RING..... \n " ) ; PRINTF ( " Cannot allocate memory for RX_RING..... \n " ) ;
goto Done ; goto Done ;
} }
if ( ! ( tx_ring = memalign ( sizeof ( struct tx_desc_3com ) * NUM_TX_DESC , 16 ) ) ) if ( ! ( tx_ring = memalign ( sizeof ( struct tx_desc_3com ) * NUM_TX_DESC , 16 ) ) ) {
{
PRINTF ( " Cannot allocate memory for TX_RING..... \n " ) ; PRINTF ( " Cannot allocate memory for TX_RING..... \n " ) ;
goto Done ; goto Done ;
} }
@ -543,219 +535,208 @@ Done:
} }
static int eth_3com_init ( struct eth_device * dev , bd_t * bis ) static int eth_3com_init ( struct eth_device * dev , bd_t * bis )
{ {
int i , status = 0 ; int i , status = 0 ;
int tx_cur , loop ; int tx_cur , loop ;
u16 status_enable , intr_enable ; u16 status_enable , intr_enable ;
struct descriptor * ias_cmd ; struct descriptor * ias_cmd ;
/* Determine what type of network the machine is connected to */ /* Determine what type of network the machine is connected to */
/* presently drops the connect to 10Mbps */ /* presently drops the connect to 10Mbps */
if ( ! auto_negotiate ( dev ) ) if ( ! auto_negotiate ( dev ) ) {
{ printf ( " Error: Cannot determine network media. \n " ) ;
printf ( " Error: Cannot determine network media. \n " ) ;
goto Done ; goto Done ;
} }
issue_and_wait ( dev , TxReset ) ; issue_and_wait ( dev , TxReset ) ;
issue_and_wait ( dev , RxReset | 0x04 ) ; issue_and_wait ( dev , RxReset | 0x04 ) ;
/* Switch to register set 7 for normal use. */ /* Switch to register set 7 for normal use. */
EL3WINDOW ( dev , 7 ) ; EL3WINDOW ( dev , 7 ) ;
/* Initialize Rx and Tx rings */ /* Initialize Rx and Tx rings */
init_rx_ring ( dev ) ; init_rx_ring ( dev ) ;
purge_tx_ring ( dev ) ; purge_tx_ring ( dev ) ;
ETH_CMD ( dev , SetRxFilter | RxStation | RxBroadcast | RxProm ) ; ETH_CMD ( dev , SetRxFilter | RxStation | RxBroadcast | RxProm ) ;
issue_and_wait ( dev , SetTxStart | 0x07ff ) ; issue_and_wait ( dev , SetTxStart | 0x07ff ) ;
/* Below sets which indication bits to be seen. */ /* Below sets which indication bits to be seen. */
status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | ( 1 < < 6 ) ; status_enable =
ETH_CMD ( dev , status_enable ) ; SetStatusEnb | HostError | DownComplete | UpComplete | ( 1 < <
6 ) ;
ETH_CMD ( dev , status_enable ) ;
/* Below sets no bits are to cause an interrupt since this is just polling */ /* Below sets no bits are to cause an interrupt since this is just polling */
intr_enable = SetIntrEnb ; intr_enable = SetIntrEnb ;
/* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */ /* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
ETH_CMD ( dev , intr_enable ) ; ETH_CMD ( dev , intr_enable ) ;
ETH_OUTB ( dev , 127 , UpPoll ) ; ETH_OUTB ( dev , 127 , UpPoll ) ;
/* Ack all pending events, and set active indicator mask */ /* Ack all pending events, and set active indicator mask */
ETH_CMD ( dev , AckIntr | IntLatch | TxAvailable | RxEarly | IntReq ) ; ETH_CMD ( dev , AckIntr | IntLatch | TxAvailable | RxEarly | IntReq ) ;
ETH_CMD ( dev , intr_enable ) ; ETH_CMD ( dev , intr_enable ) ;
/* Tell the adapter where the RX ring is located */ /* Tell the adapter where the RX ring is located */
issue_and_wait ( dev , UpStall ) ; /* Stall and set the UplistPtr */ issue_and_wait ( dev , UpStall ) ; /* Stall and set the UplistPtr */
ETH_OUTL ( dev , ( u32 ) & rx_ring [ rx_next ] , UpListPtr ) ; ETH_OUTL ( dev , ( u32 ) & rx_ring [ rx_next ] , UpListPtr ) ;
ETH_CMD ( dev , RxEnable ) ; /* Enable the receiver. */ ETH_CMD ( dev , RxEnable ) ; /* Enable the receiver. */
issue_and_wait ( dev , UpUnstall ) ; issue_and_wait ( dev , UpUnstall ) ;
/* Send the Individual Address Setup frame */ /* Send the Individual Address Setup frame */
tx_cur = tx_next ; tx_cur = tx_next ;
tx_next = ( ( tx_next + 1 ) % NUM_TX_DESC ) ; tx_next = ( ( tx_next + 1 ) % NUM_TX_DESC ) ;
ias_cmd = ( struct descriptor * ) & tx_ring [ tx_cur ] ; ias_cmd = ( struct descriptor * ) & tx_ring [ tx_cur ] ;
ias_cmd - > status = cpu_to_le32 ( 1 < < 31 ) ; /* set DnIndicate bit. */ ias_cmd - > status = cpu_to_le32 ( 1 < < 31 ) ; /* set DnIndicate bit. */
ias_cmd - > next = 0 ; ias_cmd - > next = 0 ;
ias_cmd - > addr = cpu_to_le32 ( ( u32 ) & bis - > bi_enetaddr [ 0 ] ) ; ias_cmd - > addr = cpu_to_le32 ( ( u32 ) & bis - > bi_enetaddr [ 0 ] ) ;
ias_cmd - > length = cpu_to_le32 ( 6 | LAST_FRAG ) ; ias_cmd - > length = cpu_to_le32 ( 6 | LAST_FRAG ) ;
/* Tell the adapter where the TX ring is located */ /* Tell the adapter where the TX ring is located */
ETH_CMD ( dev , TxEnable ) ; /* Enable transmitter. */ ETH_CMD ( dev , TxEnable ) ; /* Enable transmitter. */
issue_and_wait ( dev , DownStall ) ; /* Stall and set the DownListPtr. */ issue_and_wait ( dev , DownStall ) ; /* Stall and set the DownListPtr. */
ETH_OUTL ( dev , ( u32 ) & tx_ring [ tx_cur ] , DownListPtr ) ; ETH_OUTL ( dev , ( u32 ) & tx_ring [ tx_cur ] , DownListPtr ) ;
issue_and_wait ( dev , DownUnstall ) ; issue_and_wait ( dev , DownUnstall ) ;
for ( i = 0 ; ! ( ETH_STATUS ( dev ) & DownComplete ) ; i + + ) for ( i = 0 ; ! ( ETH_STATUS ( dev ) & DownComplete ) ; i + + ) {
{ if ( i > = TOUT_LOOP ) {
if ( i > = TOUT_LOOP ) PRINTF ( " TX Ring status (Init): 0x%4x \n " ,
{ le32_to_cpu ( tx_ring [ tx_cur ] . status ) ) ;
PRINTF ( " TX Ring status (Init): 0x%4x \n " , le32_to_cpu ( tx_ring [ tx_cur ] . status ) ) ; PRINTF ( " ETH_STATUS: 0x%x \n " , ETH_STATUS ( dev ) ) ;
PRINTF ( " ETH_STATUS: 0x%x \n " , ETH_STATUS ( dev ) ) ;
goto Done ; goto Done ;
} }
} }
if ( ETH_STATUS ( dev ) & DownComplete ) /* If DownLoad Complete ACK the bit */ if ( ETH_STATUS ( dev ) & DownComplete ) { /* If DownLoad Complete ACK the bit */
{ ETH_CMD ( dev , AckIntr | DownComplete ) ; /* acknowledge the indication bit */
ETH_CMD ( dev , AckIntr | DownComplete ) ; /* acknowledge the indication bit */ issue_and_wait ( dev , DownStall ) ; /* stall and clear DownListPtr */
issue_and_wait ( dev , DownStall ) ; /* stall and clear DownListPtr */ ETH_OUTL ( dev , 0 , DownListPtr ) ;
ETH_OUTL ( dev , 0 , DownListPtr ) ; issue_and_wait ( dev , DownUnstall ) ;
issue_and_wait ( dev , DownUnstall ) ;
} }
status = 1 ; status = 1 ;
Done : Done :
return status ; return status ;
} }
int eth_3com_send ( struct eth_device * dev , volatile void * packet , int length ) int eth_3com_send ( struct eth_device * dev , volatile void * packet , int length )
{ {
int i , status = 0 ; int i , status = 0 ;
int tx_cur ; int tx_cur ;
if ( length < = 0 ) if ( length < = 0 ) {
{ PRINTF ( " eth: bad packet size: %d \n " , length ) ;
PRINTF ( " eth: bad packet size: %d \n " , length ) ;
goto Done ; goto Done ;
} }
tx_cur = tx_next ; tx_cur = tx_next ;
tx_next = ( tx_next + 1 ) % NUM_TX_DESC ; tx_next = ( tx_next + 1 ) % NUM_TX_DESC ;
tx_ring [ tx_cur ] . status = cpu_to_le32 ( 1 < < 31 ) ; /* set DnIndicate bit */ tx_ring [ tx_cur ] . status = cpu_to_le32 ( 1 < < 31 ) ; /* set DnIndicate bit */
tx_ring [ tx_cur ] . next = 0 ; tx_ring [ tx_cur ] . next = 0 ;
tx_ring [ tx_cur ] . addr = cpu_to_le32 ( ( ( u32 ) packet ) ) ; tx_ring [ tx_cur ] . addr = cpu_to_le32 ( ( ( u32 ) packet ) ) ;
tx_ring [ tx_cur ] . length = cpu_to_le32 ( length | LAST_FRAG ) ; tx_ring [ tx_cur ] . length = cpu_to_le32 ( length | LAST_FRAG ) ;
/* Send the packet */ /* Send the packet */
issue_and_wait ( dev , DownStall ) ; /* stall and set the DownListPtr */ issue_and_wait ( dev , DownStall ) ; /* stall and set the DownListPtr */
ETH_OUTL ( dev , ( u32 ) & tx_ring [ tx_cur ] , DownListPtr ) ; ETH_OUTL ( dev , ( u32 ) & tx_ring [ tx_cur ] , DownListPtr ) ;
issue_and_wait ( dev , DownUnstall ) ; issue_and_wait ( dev , DownUnstall ) ;
for ( i = 0 ; ! ( ETH_STATUS ( dev ) & DownComplete ) ; i + + ) for ( i = 0 ; ! ( ETH_STATUS ( dev ) & DownComplete ) ; i + + ) {
{ if ( i > = TOUT_LOOP ) {
if ( i > = TOUT_LOOP ) PRINTF ( " TX Ring status (send): 0x%4x \n " ,
{ le32_to_cpu ( tx_ring [ tx_cur ] . status ) ) ;
PRINTF ( " TX Ring status (send): 0x%4x \n " , le32_to_cpu ( tx_ring [ tx_cur ] . status ) ) ;
goto Done ; goto Done ;
} }
} }
if ( ETH_STATUS ( dev ) & DownComplete ) /* If DownLoad Complete ACK the bit */ if ( ETH_STATUS ( dev ) & DownComplete ) { /* If DownLoad Complete ACK the bit */
{ ETH_CMD ( dev , AckIntr | DownComplete ) ; /* acknowledge the indication bit */
ETH_CMD ( dev , AckIntr | DownComplete ) ; /* acknowledge the indication bit */ issue_and_wait ( dev , DownStall ) ; /* stall and clear DownListPtr */
issue_and_wait ( dev , DownStall ) ; /* stall and clear DownListPtr */ ETH_OUTL ( dev , 0 , DownListPtr ) ;
ETH_OUTL ( dev , 0 , DownListPtr ) ; issue_and_wait ( dev , DownUnstall ) ;
issue_and_wait ( dev , DownUnstall ) ;
} }
status = 1 ; status = 1 ;
Done : Done :
return status ; return status ;
} }
void PrintPacket ( uchar * packet , int length ) void PrintPacket ( uchar * packet , int length )
{ {
int loop ; int loop ;
uchar * ptr ; uchar * ptr ;
printf ( " Printing packet of length %x. \n \n " , length ) ; printf ( " Printing packet of length %x. \n \n " , length ) ;
ptr = packet ; ptr = packet ;
for ( loop = 1 ; loop < = length ; loop + + ) for ( loop = 1 ; loop < = length ; loop + + ) {
{
printf ( " %2x " , * ptr + + ) ; printf ( " %2x " , * ptr + + ) ;
if ( ( loop % 40 ) = = 0 ) if ( ( loop % 40 ) = = 0 )
printf ( " \n " ) ; printf ( " \n " ) ;
} }
} }
int eth_3com_recv ( struct eth_device * dev ) int eth_3com_recv ( struct eth_device * dev )
{ {
u16 stat = 0 ; u16 stat = 0 ;
u32 status ; u32 status ;
int rx_prev , length = 0 ; int rx_prev , length = 0 ;
while ( ! ( ETH_STATUS ( dev ) & UpComplete ) ) /* wait on receipt of packet */ while ( ! ( ETH_STATUS ( dev ) & UpComplete ) ) /* wait on receipt of packet */
; ;
status = le32_to_cpu ( rx_ring [ rx_next ] . status ) ; /* packet status */ status = le32_to_cpu ( rx_ring [ rx_next ] . status ) ; /* packet status */
while ( status & ( 1 < < 15 ) ) while ( status & ( 1 < < 15 ) ) {
{
/* A packet has been received */ /* A packet has been received */
if ( status & ( 1 < < 15 ) ) if ( status & ( 1 < < 15 ) ) {
{
/* A valid frame received */ /* A valid frame received */
length = le32_to_cpu ( rx_ring [ rx_next ] . status ) & 0x1fff ; /* length is in bits 0 - 12 */ length = le32_to_cpu ( rx_ring [ rx_next ] . status ) & 0x1fff ; /* length is in bits 0 - 12 */
/* Pass the packet up to the protocol layers */ /* Pass the packet up to the protocol layers */
NetReceive ( ( uchar * ) le32_to_cpu ( rx_ring [ rx_next ] . addr ) , length ) ; NetReceive ( ( uchar * )
rx_ring [ rx_next ] . status = 0 ; /* clear the status word */ le32_to_cpu ( rx_ring [ rx_next ] . addr ) ,
ETH_CMD ( dev , AckIntr | UpComplete ) ; length ) ;
issue_and_wait ( dev , UpUnstall ) ; rx_ring [ rx_next ] . status = 0 ; /* clear the status word */
} ETH_CMD ( dev , AckIntr | UpComplete ) ;
else issue_and_wait ( dev , UpUnstall ) ;
if ( stat & HostError ) } else if ( stat & HostError ) {
{
/* There was an error */ /* There was an error */
printf ( " Rx error status: 0x%4x \n " , stat ) ; printf ( " Rx error status: 0x%4x \n " , stat ) ;
init_rx_ring ( dev ) ; init_rx_ring ( dev ) ;
goto Done ; goto Done ;
} }
rx_prev = rx_next ; rx_prev = rx_next ;
rx_next = ( rx_next + 1 ) % NUM_RX_DESC ; rx_next = ( rx_next + 1 ) % NUM_RX_DESC ;
stat = ETH_STATUS ( dev ) ; /* register status */ stat = ETH_STATUS ( dev ) ; /* register status */
status = le32_to_cpu ( rx_ring [ rx_next ] . status ) ; /* packet status */ status = le32_to_cpu ( rx_ring [ rx_next ] . status ) ; /* packet status */
} }
Done : Done :
return length ; return length ;
} }
void eth_3com_halt ( struct eth_device * dev ) void eth_3com_halt ( struct eth_device * dev )
{ {
if ( ! ( dev - > iobase ) ) if ( ! ( dev - > iobase ) ) {
{
goto Done ; goto Done ;
} }
issue_and_wait ( dev , DownStall ) ; /* shut down transmit and receive */ issue_and_wait ( dev , DownStall ) ; /* shut down transmit and receive */
issue_and_wait ( dev , UpStall ) ; issue_and_wait ( dev , UpStall ) ;
issue_and_wait ( dev , RxDisable ) ; issue_and_wait ( dev , RxDisable ) ;
issue_and_wait ( dev , TxDisable ) ; issue_and_wait ( dev , TxDisable ) ;
/* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */ /* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */
/* free(rx_ring); */ /* free(rx_ring); */
@ -764,41 +745,41 @@ Done:
return ; return ;
} }
static void init_rx_ring ( struct eth_device * dev ) static void init_rx_ring ( struct eth_device * dev )
{ {
int i ; int i ;
PRINTF ( " Initializing rx_ring. rx_buffer = %p \n " , rx_buffer ) ; PRINTF ( " Initializing rx_ring. rx_buffer = %p \n " , rx_buffer ) ;
issue_and_wait ( dev , UpStall ) ; issue_and_wait ( dev , UpStall ) ;
for ( i = 0 ; i < NUM_RX_DESC ; i + + ) for ( i = 0 ; i < NUM_RX_DESC ; i + + ) {
{ rx_ring [ i ] . next =
rx_ring [ i ] . next = cpu_to_le32 ( ( ( u32 ) & rx_ring [ ( i + 1 ) % NUM_RX_DESC ] ) ) ; cpu_to_le32 ( ( ( u32 ) &
rx_ring [ i ] . status = 0 ; rx_ring [ ( i + 1 ) % NUM_RX_DESC ] ) ) ;
rx_ring [ i ] . addr = cpu_to_le32 ( ( ( u32 ) & rx_buffer [ i ] [ 0 ] ) ) ; rx_ring [ i ] . status = 0 ;
rx_ring [ i ] . length = cpu_to_le32 ( PKTSIZE_ALIGN | LAST_FRAG ) ; rx_ring [ i ] . addr = cpu_to_le32 ( ( ( u32 ) & rx_buffer [ i ] [ 0 ] ) ) ;
rx_ring [ i ] . length = cpu_to_le32 ( PKTSIZE_ALIGN | LAST_FRAG ) ;
} }
rx_next = 0 ; rx_next = 0 ;
} }
static void purge_tx_ring ( struct eth_device * dev ) static void purge_tx_ring ( struct eth_device * dev )
{ {
int i ; int i ;
PRINTF ( " Purging tx_ring. \n " ) ; PRINTF ( " Purging tx_ring. \n " ) ;
tx_next = 0 ; tx_next = 0 ;
for ( i = 0 ; i < NUM_TX_DESC ; i + + ) for ( i = 0 ; i < NUM_TX_DESC ; i + + ) {
{ tx_ring [ i ] . next = 0 ;
tx_ring [ i ] . next = 0 ; tx_ring [ i ] . status = 0 ;
tx_ring [ i ] . status = 0 ; tx_ring [ i ] . addr = 0 ;
tx_ring [ i ] . addr = 0 ; tx_ring [ i ] . length = 0 ;
tx_ring [ i ] . length = 0 ;
} }
} }
static void read_hw_addr ( struct eth_device * dev , bd_t * bis ) static void read_hw_addr ( struct eth_device * dev , bd_t * bis )
{ {
u8 hw_addr [ ETH_ALEN ] ; u8 hw_addr [ ETH_ALEN ] ;
unsigned int eeprom [ 0x40 ] ; unsigned int eeprom [ 0x40 ] ;
@ -807,77 +788,77 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
/* Read the station address from the EEPROM. */ /* Read the station address from the EEPROM. */
EL3WINDOW ( dev , 0 ) ; EL3WINDOW ( dev , 0 ) ;
for ( i = 0 ; i < 0x40 ; i + + ) for ( i = 0 ; i < 0x40 ; i + + ) {
{ ETH_OUTW ( dev , EEPROM_Read + i , Wn0EepromCmd ) ;
ETH_OUTW ( dev , EEPROM_Read + i , Wn0EepromCmd ) ;
/* Pause for at least 162 us. for the read to take place. */ /* Pause for at least 162 us. for the read to take place. */
for ( timer = 10 ; timer > = 0 ; timer - - ) for ( timer = 10 ; timer > = 0 ; timer - - ) {
{ udelay ( 162 ) ;
udelay ( 162 ) ; if ( ( ETH_INW ( dev , Wn0EepromCmd ) & 0x8000 ) = = 0 )
if ( ( ETH_INW ( dev , Wn0EepromCmd ) & 0x8000 ) = = 0 )
break ; break ;
} }
eeprom [ i ] = ETH_INW ( dev , Wn0EepromData ) ; eeprom [ i ] = ETH_INW ( dev , Wn0EepromData ) ;
} }
/* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */ /* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */
for ( i = 0 ; i < 0x21 ; i + + ) for ( i = 0 ; i < 0x21 ; i + + )
checksum ^ = eeprom [ i ] ; checksum ^ = eeprom [ i ] ;
checksum = ( checksum ^ ( checksum > > 8 ) ) & 0xff ; checksum = ( checksum ^ ( checksum > > 8 ) ) & 0xff ;
if ( checksum ! = 0xbb ) if ( checksum ! = 0xbb )
printf ( " *** INVALID EEPROM CHECKSUM %4.4x *** \n " , checksum ) ; printf ( " *** INVALID EEPROM CHECKSUM %4.4x *** \n " ,
checksum ) ;
for ( i = 0 , j = 0 ; i < 3 ; i + + ) for ( i = 0 , j = 0 ; i < 3 ; i + + ) {
{ hw_addr [ j + + ] = ( u8 ) ( ( eeprom [ i + 10 ] > > 8 ) & 0xff ) ;
hw_addr [ j + + ] = ( u8 ) ( ( eeprom [ i + 10 ] > > 8 ) & 0xff ) ; hw_addr [ j + + ] = ( u8 ) ( eeprom [ i + 10 ] & 0xff ) ;
hw_addr [ j + + ] = ( u8 ) ( eeprom [ i + 10 ] & 0xff ) ;
} }
/* MAC Address is in window 2, write value from EEPROM to window 2 */ /* MAC Address is in window 2, write value from EEPROM to window 2 */
EL3WINDOW ( dev , 2 ) ; EL3WINDOW ( dev , 2 ) ;
for ( i = 0 ; i < 6 ; i + + ) for ( i = 0 ; i < 6 ; i + + )
ETH_OUTB ( dev , hw_addr [ i ] , i ) ; ETH_OUTB ( dev , hw_addr [ i ] , i ) ;
for ( j = 0 ; j < ETH_ALEN ; j + = 2 ) for ( j = 0 ; j < ETH_ALEN ; j + = 2 ) {
{ hw_addr [ j ] = ( u8 ) ( ETH_INW ( dev , j ) & 0xff ) ;
hw_addr [ j ] = ( u8 ) ( ETH_INW ( dev , j ) & 0xff ) ; hw_addr [ j + 1 ] = ( u8 ) ( ( ETH_INW ( dev , j ) > > 8 ) & 0xff ) ;
hw_addr [ j + 1 ] = ( u8 ) ( ( ETH_INW ( dev , j ) > > 8 ) & 0xff ) ;
} }
for ( i = 0 ; i < ETH_ALEN ; i + + ) for ( i = 0 ; i < ETH_ALEN ; i + + ) {
{ if ( hw_addr [ i ] ! = bis - > bi_enetaddr [ i ] ) {
if ( hw_addr [ i ] ! = bis - > bi_enetaddr [ i ] ) /* printf("Warning: HW address don't match:\n"); */
{ /* printf("Address in 3Com Window 2 is " */
/* printf("Warning: HW address don't match:\n"); */ /* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
/* printf("Address in 3Com Window 2 is " */ /* hw_addr[0], hw_addr[1], hw_addr[2], */
/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ /* hw_addr[3], hw_addr[4], hw_addr[5]); */
/* hw_addr[0], hw_addr[1], hw_addr[2], */ /* printf("Address used by U-Boot is " */
/* hw_addr[3], hw_addr[4], hw_addr[5]); */ /* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
/* printf("Address used by U-Boot is " */ /* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */
/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ /* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */
/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */ /* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */ /* goto Done; */
/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */ char buffer [ 256 ] ;
/* goto Done; */
char buffer [ 256 ] ; if ( bis - > bi_enetaddr [ 0 ] = = 0
if ( bis - > bi_enetaddr [ 0 ] = = 0 & & bis - > bi_enetaddr [ 1 ] = = 0 & & & & bis - > bi_enetaddr [ 1 ] = = 0
bis - > bi_enetaddr [ 2 ] = = 0 & & bis - > bi_enetaddr [ 3 ] = = 0 & & & & bis - > bi_enetaddr [ 2 ] = = 0
bis - > bi_enetaddr [ 4 ] = = 0 & & bis - > bi_enetaddr [ 5 ] = = 0 ) & & bis - > bi_enetaddr [ 3 ] = = 0
{ & & bis - > bi_enetaddr [ 4 ] = = 0
& & bis - > bi_enetaddr [ 5 ] = = 0 ) {
sprintf ( buffer , " %02X:%02X:%02X:%02X:%02X:%02X " ,
hw_addr [ 0 ] , hw_addr [ 1 ] , hw_addr [ 2 ] , sprintf ( buffer ,
hw_addr [ 3 ] , hw_addr [ 4 ] , hw_addr [ 5 ] ) ; " %02X:%02X:%02X:%02X:%02X:%02X " ,
setenv ( " ethaddr " , buffer ) ; hw_addr [ 0 ] , hw_addr [ 1 ] , hw_addr [ 2 ] ,
} hw_addr [ 3 ] , hw_addr [ 4 ] , hw_addr [ 5 ] ) ;
setenv ( " ethaddr " , buffer ) ;
}
} }
} }
for ( i = 0 ; i < ETH_ALEN ; i + + ) dev - > enetaddr [ i ] = hw_addr [ i ] ; for ( i = 0 ; i < ETH_ALEN ; i + + )
dev - > enetaddr [ i ] = hw_addr [ i ] ;
Done : Done :
return ; return ;
Wolfgang Denk
16 years ago