Mike Frysinger
16 years ago
parent
dfc91c3395
commit
76d21803dd
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/u-boot.lds |
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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COBJS-$(CONFIG_VIDEO) += video.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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$(obj)u-boot.lds: u-boot.lds.S |
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$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,79 @@ |
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/*
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* U-boot - main board file |
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* |
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* Copyright (c) 2005-2008 Analog Devices Inc. |
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* |
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* Licensed under the GPL-2 or later. |
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*/ |
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#include <common.h> |
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#include <config.h> |
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#include <command.h> |
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#include <asm/blackfin.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int checkboard(void) |
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{ |
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printf("Board: ADI BF548 EZ-Kit board\n"); |
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printf(" Support: http://blackfin.uclinux.org/\n"); |
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return 0; |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; |
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gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; |
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return gd->bd->bi_memsize; |
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} |
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int board_early_init_f(void) |
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{ |
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/* Port H: PH8 - PH13 == A4 - A9
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* address lines of the parallel asynchronous memory interface |
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*/ |
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/************************************************
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* configure GPIO * |
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* set port H function enable register * |
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* configure PH8-PH13 as peripheral (not GPIO) * |
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*************************************************/ |
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bfin_write_PORTH_FER(0x3F03); |
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/************************************************
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* set port H MUX to configure PH8-PH13 * |
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* 1st Function (MUX = 00) (bits 16-27 == 0) * |
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* Set to address signals A4-A9 * |
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*************************************************/ |
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bfin_write_PORTH_MUX(0); |
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/************************************************
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* set port H direction register * |
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* enable PH8-PH13 as outputs * |
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*************************************************/ |
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bfin_write_PORTH_DIR_SET(0x3F00); |
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/* Port I: PI0 - PH14 == A10 - A24
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* address lines of the parallel asynchronous memory interface |
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*/ |
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/************************************************
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* set port I function enable register * |
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* configure PI0-PI14 as peripheral (not GPIO) * |
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*************************************************/ |
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bfin_write_PORTI_FER(0x7fff); |
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/**************************************************
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* set PORT I MUX to configure PI14-PI0 as * |
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* 1st Function (MUX=00) - address signals A10-A24 * |
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***************************************************/ |
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bfin_write_PORTI_MUX(0); |
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/****************************************
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* set PORT I direction register * |
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* enable PI0 - PI14 as outputs * |
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*****************************************/ |
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bfin_write_PORTI_DIR_SET(0x7fff); |
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return 0; |
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} |
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@ -0,0 +1,37 @@ |
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# This is not actually used for Blackfin boards so do not change it
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#TEXT_BASE = do-not-use-me
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LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
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# Set some default LDR flags based on boot mode.
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LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
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LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
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LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
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LDR_FLAGS-BFIN_BOOT_UART := --dma 1
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LDR_FLAGS-BFIN_BOOT_NAND := --dma 6
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LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
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@ -0,0 +1,124 @@ |
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/* |
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* U-boot - u-boot.lds.S |
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* |
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* Copyright (c) 2005-2008 Analog Device Inc. |
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* |
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* (C) Copyright 2000-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <asm/blackfin.h> |
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#undef ALIGN |
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#undef ENTRY |
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#undef bfin |
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/* If we don't actually load anything into L1 data, this will avoid |
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* a syntax error. If we do actually load something into L1 data, |
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* we'll get a linker memory load error (which is what we'd want). |
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* This is here in the first place so we can quickly test building |
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* for different CPU's which may lack non-cache L1 data. |
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*/ |
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#ifndef L1_DATA_B_SRAM |
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# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE |
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# define L1_DATA_B_SRAM_SIZE 0 |
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#endif |
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OUTPUT_ARCH(bfin) |
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MEMORY |
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{ |
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ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
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l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE |
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l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
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} |
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ENTRY(_start) |
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SECTIONS |
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{ |
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.text : |
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{ |
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cpu/blackfin/start.o (.text .text.*) |
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__initcode_start = .;
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cpu/blackfin/initcode.o (.text .text.*) |
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__initcode_end = .;
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*(.text .text.*) |
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} >ram |
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.rodata : |
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{ |
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. = ALIGN(4);
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*(.rodata .rodata.*) |
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*(.rodata1) |
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*(.eh_frame) |
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. = ALIGN(4);
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} >ram |
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.data : |
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{ |
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. = ALIGN(256);
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*(.data .data.*) |
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*(.data1) |
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*(.sdata) |
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*(.sdata2) |
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*(.dynamic) |
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CONSTRUCTORS |
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} >ram |
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.u_boot_cmd : |
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{ |
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___u_boot_cmd_start = .;
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*(.u_boot_cmd) |
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___u_boot_cmd_end = .;
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} >ram |
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.text_l1 : |
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{ |
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. = ALIGN(4);
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__stext_l1 = .;
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*(.l1.text) |
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. = ALIGN(4);
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__etext_l1 = .;
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} >l1_code AT>ram |
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__stext_l1_lma = LOADADDR(.text_l1);
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.data_l1 : |
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{ |
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. = ALIGN(4);
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__sdata_l1 = .;
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*(.l1.data) |
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*(.l1.bss) |
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. = ALIGN(4);
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__edata_l1 = .;
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} >l1_data AT>ram |
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__sdata_l1_lma = LOADADDR(.data_l1);
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.bss : |
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{ |
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. = ALIGN(4);
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__bss_start = .;
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*(.sbss) *(.scommon) |
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*(.dynbss) |
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*(.bss .bss.*) |
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*(COMMON) |
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__bss_end = .;
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} >ram |
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} |
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@ -0,0 +1,327 @@ |
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/*
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* video.c - run splash screen on lcd |
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* |
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* Copyright (c) 2007-2008 Analog Devices Inc. |
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* |
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* Licensed under the GPL-2 or later. |
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*/ |
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#include <stdarg.h> |
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#include <common.h> |
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#include <config.h> |
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#include <malloc.h> |
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#include <asm/blackfin.h> |
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#include <asm/mach-common/bits/dma.h> |
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#include <i2c.h> |
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#include <linux/types.h> |
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#include <devices.h> |
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int gunzip(void *, int, unsigned char *, unsigned long *); |
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#define DMA_SIZE16 2 |
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#include <asm/mach-common/bits/eppi.h> |
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#include <asm/bfin_logo_230x230.h> |
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#define LCD_X_RES 480 /*Horizontal Resolution */ |
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#define LCD_Y_RES 272 /* Vertical Resolution */ |
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#define LCD_BPP 24 /* Bit Per Pixel */ |
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#define LCD_PIXEL_SIZE (LCD_BPP / 8) |
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#define DMA_BUS_SIZE 32 |
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#define ACTIVE_VIDEO_MEM_OFFSET 0 |
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/* -- Horizontal synchronizing --
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* |
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* Timing characteristics taken from the SHARP LQ043T1DG01 datasheet |
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* (LCY-W-06602A Page 9 of 22) |
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* |
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* Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz |
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* |
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* Period TH - 525 - Clock |
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* Pulse width THp - 41 - Clock |
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* Horizontal period THd - 480 - Clock |
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* Back porch THb - 2 - Clock |
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* Front porch THf - 2 - Clock |
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* |
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* -- Vertical synchronizing -- |
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* Period TV - 286 - Line |
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* Pulse width TVp - 10 - Line |
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* Vertical period TVd - 272 - Line |
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* Back porch TVb - 2 - Line |
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* Front porch TVf - 2 - Line |
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*/ |
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#define LCD_CLK (8*1000*1000) /* 8MHz */ |
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/* # active data to transfer after Horizontal Delay clock */ |
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#define EPPI_HCOUNT LCD_X_RES |
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/* # active lines to transfer after Vertical Delay clock */ |
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#define EPPI_VCOUNT LCD_Y_RES |
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/* Samples per Line = 480 (active data) + 45 (padding) */ |
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#define EPPI_LINE 525 |
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/* Lines per Frame = 272 (active data) + 14 (padding) */ |
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#define EPPI_FRAME 286 |
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/* FS1 (Hsync) Width (Typical)*/ |
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#define EPPI_FS1W_HBL 41 |
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/* FS1 (Hsync) Period (Typical) */ |
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#define EPPI_FS1P_AVPL EPPI_LINE |
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/* Horizontal Delay clock after assertion of Hsync (Typical) */ |
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#define EPPI_HDELAY 43 |
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/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */ |
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#define EPPI_FS2W_LVB (EPPI_LINE * 10) |
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/* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */ |
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#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME) |
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/* Vertical Delay after assertion of Vsync (2 Lines) */ |
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#define EPPI_VDELAY 12 |
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#define EPPI_CLIP 0xFF00FF00 |
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/* EPPI Control register configuration value for RGB out
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* - EPPI as Output |
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* GP 2 frame sync mode, |
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* Internal Clock generation disabled, Internal FS generation enabled, |
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* Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge, |
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* FS1 & FS2 are active high, |
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* DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) |
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* DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled |
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* Swapping Enabled, |
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* One (DMA) Channel Mode, |
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* RGB Formatting Enabled for RGB666 output, disabled for RGB888 output |
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* Regular watermark - when FIFO is 100% full, |
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* Urgent watermark - when FIFO is 75% full |
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*/ |
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#define EPPI_CONTROL (0x20136E2E) |
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static inline u16 get_eppi_clkdiv(u32 target_ppi_clk) |
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{ |
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u32 sclk = get_sclk(); |
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/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */ |
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return (((sclk / target_ppi_clk) / 2) - 1); |
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} |
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|
||||||
|
void Init_PPI(void) |
||||||
|
{ |
||||||
|
u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK); |
||||||
|
|
||||||
|
bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL); |
||||||
|
bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL); |
||||||
|
bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB); |
||||||
|
bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF); |
||||||
|
bfin_write_EPPI0_CLIP(EPPI_CLIP); |
||||||
|
|
||||||
|
bfin_write_EPPI0_FRAME(EPPI_FRAME); |
||||||
|
bfin_write_EPPI0_LINE(EPPI_LINE); |
||||||
|
|
||||||
|
bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT); |
||||||
|
bfin_write_EPPI0_HDELAY(EPPI_HDELAY); |
||||||
|
bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT); |
||||||
|
bfin_write_EPPI0_VDELAY(EPPI_VDELAY); |
||||||
|
|
||||||
|
bfin_write_EPPI0_CLKDIV(eppi_clkdiv); |
||||||
|
|
||||||
|
/*
|
||||||
|
* DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) |
||||||
|
* RGB Formatting Enabled for RGB666 output, disabled for RGB888 output |
||||||
|
*/ |
||||||
|
#if defined(CONFIG_VIDEO_RGB666) |
||||||
|
bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 | |
||||||
|
RGB_FMT_EN); |
||||||
|
#else |
||||||
|
bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) & |
||||||
|
~RGB_FMT_EN); |
||||||
|
#endif |
||||||
|
|
||||||
|
} |
||||||
|
|
||||||
|
#define DEB2_URGENT 0x2000 /* DEB2 Urgent */ |
||||||
|
|
||||||
|
void Init_DMA(void *dst) |
||||||
|
{ |
||||||
|
|
||||||
|
#if defined(CONFIG_DEB_DMA_URGENT) |
||||||
|
*pEBIU_DDRQUE |= DEB2_URGENT; |
||||||
|
#endif |
||||||
|
|
||||||
|
*pDMA12_START_ADDR = dst; |
||||||
|
|
||||||
|
/* X count */ |
||||||
|
*pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE; |
||||||
|
*pDMA12_X_MODIFY = DMA_BUS_SIZE / 8; |
||||||
|
|
||||||
|
/* Y count */ |
||||||
|
*pDMA12_Y_COUNT = LCD_Y_RES; |
||||||
|
*pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8; |
||||||
|
|
||||||
|
/* DMA Config */ |
||||||
|
*pDMA12_CONFIG = |
||||||
|
WDSIZE_32 | /* 32 bit DMA */ |
||||||
|
DMA2D | /* 2D DMA */ |
||||||
|
FLOW_AUTO; /* autobuffer mode */ |
||||||
|
} |
||||||
|
|
||||||
|
void Init_Ports(void) |
||||||
|
{ |
||||||
|
*pPORTF_MUX = 0x00000000; |
||||||
|
*pPORTF_FER |= 0xFFFF; /* PPI0..15 */ |
||||||
|
|
||||||
|
*pPORTG_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); |
||||||
|
*pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ |
||||||
|
|
||||||
|
#if !defined(CONFIG_VIDEO_RGB666) |
||||||
|
*pPORTD_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); |
||||||
|
*pPORTD_MUX |= (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); |
||||||
|
*pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ |
||||||
|
#endif |
||||||
|
|
||||||
|
*pPORTE_FER &= ~PE3; /* DISP */ |
||||||
|
*pPORTE_DIR_SET = PE3; |
||||||
|
*pPORTE_SET = PE3; |
||||||
|
|
||||||
|
} |
||||||
|
|
||||||
|
void EnableDMA(void) |
||||||
|
{ |
||||||
|
*pDMA12_CONFIG |= DMAEN; |
||||||
|
} |
||||||
|
|
||||||
|
void DisableDMA(void) |
||||||
|
{ |
||||||
|
*pDMA12_CONFIG &= ~DMAEN; |
||||||
|
} |
||||||
|
|
||||||
|
/* enable and disable PPI functions */ |
||||||
|
void EnablePPI(void) |
||||||
|
{ |
||||||
|
bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN); |
||||||
|
} |
||||||
|
|
||||||
|
void DisablePPI(void) |
||||||
|
{ |
||||||
|
bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN); |
||||||
|
} |
||||||
|
|
||||||
|
int video_init(void *dst) |
||||||
|
{ |
||||||
|
Init_Ports(); |
||||||
|
Init_DMA(dst); |
||||||
|
EnableDMA(); |
||||||
|
Init_PPI(); |
||||||
|
EnablePPI(); |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) |
||||||
|
{ |
||||||
|
if (dcache_status()) |
||||||
|
blackfin_dcache_flush_range(logo->data, logo->data + logo->size); |
||||||
|
|
||||||
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); |
||||||
|
|
||||||
|
/* Setup destination start address */ |
||||||
|
bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE) |
||||||
|
+ (y * LCD_X_RES * LCD_PIXEL_SIZE)); |
||||||
|
/* Setup destination xcount */ |
||||||
|
bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); |
||||||
|
/* Setup destination xmodify */ |
||||||
|
bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16); |
||||||
|
|
||||||
|
/* Setup destination ycount */ |
||||||
|
bfin_write_MDMA_D0_Y_COUNT(logo->height); |
||||||
|
/* Setup destination ymodify */ |
||||||
|
bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16); |
||||||
|
|
||||||
|
|
||||||
|
/* Setup Source start address */ |
||||||
|
bfin_write_MDMA_S0_START_ADDR(logo->data); |
||||||
|
/* Setup Source xcount */ |
||||||
|
bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); |
||||||
|
/* Setup Source xmodify */ |
||||||
|
bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16); |
||||||
|
|
||||||
|
/* Setup Source ycount */ |
||||||
|
bfin_write_MDMA_S0_Y_COUNT(logo->height); |
||||||
|
/* Setup Source ymodify */ |
||||||
|
bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16); |
||||||
|
|
||||||
|
|
||||||
|
/* Enable source DMA */ |
||||||
|
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D); |
||||||
|
SSYNC(); |
||||||
|
bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D); |
||||||
|
|
||||||
|
while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN); |
||||||
|
|
||||||
|
bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR); |
||||||
|
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR); |
||||||
|
|
||||||
|
} |
||||||
|
|
||||||
|
void video_putc(const char c) |
||||||
|
{ |
||||||
|
} |
||||||
|
|
||||||
|
void video_puts(const char *s) |
||||||
|
{ |
||||||
|
} |
||||||
|
|
||||||
|
int drv_video_init(void) |
||||||
|
{ |
||||||
|
int error, devices = 1; |
||||||
|
device_t videodev; |
||||||
|
|
||||||
|
u8 *dst; |
||||||
|
u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET; |
||||||
|
|
||||||
|
dst = malloc(fbmem_size); |
||||||
|
|
||||||
|
if (dst == NULL) { |
||||||
|
printf("Failed to alloc FB memory\n"); |
||||||
|
return -1; |
||||||
|
} |
||||||
|
|
||||||
|
#ifdef EASYLOGO_ENABLE_GZIP |
||||||
|
unsigned char *data = EASYLOGO_DECOMP_BUFFER; |
||||||
|
unsigned long src_len = EASYLOGO_ENABLE_GZIP; |
||||||
|
if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) { |
||||||
|
puts("Failed to decompress logo\n"); |
||||||
|
free(dst); |
||||||
|
return -1; |
||||||
|
} |
||||||
|
bfin_logo.data = data; |
||||||
|
#endif |
||||||
|
|
||||||
|
memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET); |
||||||
|
|
||||||
|
dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo, |
||||||
|
(LCD_X_RES - bfin_logo.width) / 2, |
||||||
|
(LCD_Y_RES - bfin_logo.height) / 2); |
||||||
|
|
||||||
|
video_init(dst); /* Video initialization */ |
||||||
|
|
||||||
|
memset(&videodev, 0, sizeof(videodev)); |
||||||
|
|
||||||
|
strcpy(videodev.name, "video"); |
||||||
|
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ |
||||||
|
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ |
||||||
|
videodev.putc = video_putc; /* 'putc' function */ |
||||||
|
videodev.puts = video_puts; /* 'puts' function */ |
||||||
|
|
||||||
|
error = device_register(&videodev); |
||||||
|
|
||||||
|
return (error == 0) ? devices : error; |
||||||
|
} |
||||||
@ -0,0 +1,211 @@ |
|||||||
|
/*
|
||||||
|
* U-boot - Configuration file for BF548 STAMP board |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __CONFIG_BF548_EZKIT_H__ |
||||||
|
#define __CONFIG_BF548_EZKIT_H__ |
||||||
|
|
||||||
|
#include <asm/blackfin-config-pre.h> |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Processor Settings |
||||||
|
*/ |
||||||
|
#define CONFIG_BFIN_CPU bf548-0.0 |
||||||
|
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clock Settings |
||||||
|
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
||||||
|
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
||||||
|
*/ |
||||||
|
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||||
|
#define CONFIG_CLKIN_HZ 25000000 |
||||||
|
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
||||||
|
/* 1 = CLKIN / 2 */ |
||||||
|
#define CONFIG_CLKIN_HALF 0 |
||||||
|
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
||||||
|
/* 1 = bypass PLL */ |
||||||
|
#define CONFIG_PLL_BYPASS 0 |
||||||
|
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
||||||
|
/* Values can range from 0-63 (where 0 means 64) */ |
||||||
|
#define CONFIG_VCO_MULT 21 |
||||||
|
/* CCLK_DIV controls the core clock divider */ |
||||||
|
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||||
|
#define CONFIG_CCLK_DIV 1 |
||||||
|
/* SCLK_DIV controls the system clock divider */ |
||||||
|
/* Values can range from 1-15 */ |
||||||
|
#define CONFIG_SCLK_DIV 4 |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Memory Settings |
||||||
|
*/ |
||||||
|
#define CONFIG_MEM_ADD_WDTH 10 |
||||||
|
#define CONFIG_MEM_SIZE 64 |
||||||
|
|
||||||
|
#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE |
||||||
|
#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 |
||||||
|
#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 |
||||||
|
|
||||||
|
/* Default EZ-Kit bank mapping:
|
||||||
|
* Async Bank 0 - 32MB Burst Flash |
||||||
|
* Async Bank 1 - Ethernet |
||||||
|
* Async Bank 2 - Nothing |
||||||
|
* Async Bank 3 - Nothing |
||||||
|
*/ |
||||||
|
#define CONFIG_EBIU_AMGCTL_VAL 0xFF |
||||||
|
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 |
||||||
|
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 |
||||||
|
#define CONFIG_EBIU_FCTL_VAL (BCLK_4) |
||||||
|
#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) |
||||||
|
|
||||||
|
#define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
||||||
|
#define CONFIG_SYS_MALLOC_LEN (768 * 1024) |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Network Settings |
||||||
|
*/ |
||||||
|
#define ADI_CMDS_NETWORK 1 |
||||||
|
#define CONFIG_DRIVER_SMC911X 1 |
||||||
|
#define CONFIG_DRIVER_SMC911X_BASE 0x24000000 |
||||||
|
#define CONFIG_DRIVER_SMC911X_16_BIT |
||||||
|
#define CONFIG_HOSTNAME bf548-ezkit |
||||||
|
/* Uncomment next line to use fixed MAC address */ |
||||||
|
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Flash Settings |
||||||
|
*/ |
||||||
|
#define CONFIG_FLASH_CFI_DRIVER |
||||||
|
#define CONFIG_SYS_FLASH_BASE 0x20000000 |
||||||
|
#define CONFIG_SYS_FLASH_CFI |
||||||
|
#define CONFIG_SYS_FLASH_PROTECTION |
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||||
|
#define CONFIG_SYS_MAX_FLASH_SECT 259 |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPI Settings |
||||||
|
*/ |
||||||
|
#define CONFIG_BFIN_SPI |
||||||
|
#define CONFIG_ENV_SPI_MAX_HZ 30000000 |
||||||
|
#define CONFIG_SF_DEFAULT_HZ 30000000 |
||||||
|
#define CONFIG_SPI_FLASH |
||||||
|
#define CONFIG_SPI_FLASH_STMICRO |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Env Storage Settings |
||||||
|
*/ |
||||||
|
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
||||||
|
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||||
|
#define CONFIG_ENV_OFFSET 0x10000 |
||||||
|
#define CONFIG_ENV_SIZE 0x2000 |
||||||
|
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||||
|
#define ENV_IS_EMBEDDED_CUSTOM |
||||||
|
#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
||||||
|
#define CONFIG_ENV_IS_IN_NAND |
||||||
|
#define CONFIG_ENV_OFFSET 0x40000 |
||||||
|
#define CONFIG_ENV_SIZE 0x20000 |
||||||
|
#else |
||||||
|
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||||
|
#define CONFIG_ENV_ADDR 0x20002000 |
||||||
|
#define CONFIG_ENV_OFFSET 0x2000 |
||||||
|
#define CONFIG_ENV_SIZE 0x2000 |
||||||
|
#define CONFIG_ENV_SECT_SIZE (128 * 1024) |
||||||
|
#define ENV_IS_EMBEDDED_CUSTOM |
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* NAND Settings |
||||||
|
*/ |
||||||
|
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 |
||||||
|
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
||||||
|
# define CONFIG_BFIN_NFC_BOOTROM_ECC |
||||||
|
#endif |
||||||
|
#define CONFIG_DRIVER_NAND_BFIN |
||||||
|
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ |
||||||
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||||
|
#define NAND_MAX_CHIPS 1 |
||||||
|
#define CONFIG_CMD_NAND |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C Settings |
||||||
|
*/ |
||||||
|
#define CONFIG_BFIN_TWI_I2C 1 |
||||||
|
#define CONFIG_HARD_I2C 1 |
||||||
|
#define CONFIG_SYS_I2C_SPEED 50000 |
||||||
|
#define CONFIG_SYS_I2C_SLAVE 0 |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SATA |
||||||
|
*/ |
||||||
|
#if !defined(__ADSPBF544__) |
||||||
|
#define CONFIG_LIBATA |
||||||
|
#define CONFIG_SYS_SATA_MAX_DEVICE 1 |
||||||
|
#define CONFIG_LBA48 |
||||||
|
#define CONFIG_PATA_BFIN |
||||||
|
#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800 |
||||||
|
#define CONFIG_BFIN_ATA_MODE XFER_PIO_4 |
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDH Settings |
||||||
|
*/ |
||||||
|
#if !defined(__ADSPBF544__) |
||||||
|
#define CONFIG_MMC |
||||||
|
#define CONFIG_BFIN_SDH |
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* USB Settings |
||||||
|
*/ |
||||||
|
#if !defined(__ADSPBF544__) |
||||||
|
#define CONFIG_USB |
||||||
|
#define CONFIG_MUSB_HCD |
||||||
|
#define CONFIG_USB_BLACKFIN |
||||||
|
#define CONFIG_USB_STORAGE |
||||||
|
#define CONFIG_MUSB_TIMEOUT 100000 |
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Misc Settings |
||||||
|
*/ |
||||||
|
#define CONFIG_BOARD_EARLY_INIT_F |
||||||
|
#define CONFIG_RTC_BFIN |
||||||
|
#define CONFIG_UART_CONSOLE 1 |
||||||
|
|
||||||
|
#ifndef __ADSPBF542__ |
||||||
|
/* Don't waste time transferring a logo over the UART */ |
||||||
|
# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) |
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|
# define CONFIG_VIDEO |
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|
# endif |
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|
# define CONFIG_DEB_DMA_URGENT |
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|
#endif |
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|
|
||||||
|
/* Define if want to do post memory test */ |
||||||
|
#undef CONFIG_POST |
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|
#ifdef CONFIG_POST |
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|
#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ |
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|
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ |
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|
#endif |
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|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Pull in common ADI header for remaining command/environment setup |
||||||
|
*/ |
||||||
|
#include <configs/bfin_adi_common.h> |
||||||
|
|
||||||
|
#include <asm/blackfin-config-post.h> |
||||||
|
|
||||||
|
#endif |
||||||
Loading…
Reference in new issue