Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

ppc4xx: remove HH405 board

Browse Source 
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
master
Matthias Fuchs 10 years ago committed by Tom Rini
parent 7ac9d47a22
commit 843125daeb
14 changed files with 1 additions and 21529 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 4
      arch/powerpc/cpu/ppc4xx/Kconfig
  2. 12
      board/esd/hh405/Kconfig
  3. 6
      board/esd/hh405/MAINTAINERS
  4. 11
      board/esd/hh405/Makefile
  5. 85
      board/esd/hh405/flash.c
  6. 5034
      board/esd/hh405/fpgadata.c
  7. 895
      board/esd/hh405/hh405.c
  8. 5087
      board/esd/hh405/logo_1024_768_8bpp.c
  9. 454
      board/esd/hh405/logo_320_240_4bpp.c
  10. 1042
      board/esd/hh405/logo_320_240_8bpp.c
  11. 8417
      board/esd/hh405/logo_640_480_24bpp.c
  12. 3
      configs/HH405_defconfig
  13. 1
      doc/README.scrapyard
  14. 479
      include/configs/HH405.h

4
arch/powerpc/cpu/ppc4xx/Kconfig
Unescape View File

@ -125,9 +125,6 @@ config TARGET_CPCI405AB
config TARGET_CPCI405DT config TARGET_CPCI405DT
bool "Support CPCI405DT" bool "Support CPCI405DT"
config TARGET_HH405
bool "Support HH405"
config TARGET_HUB405 config TARGET_HUB405
bool "Support HUB405" bool "Support HUB405"
@ -235,7 +232,6 @@ source "board/csb472/Kconfig"
source "board/dave/PPChameleonEVB/Kconfig" source "board/dave/PPChameleonEVB/Kconfig"
source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig" source "board/esd/cpci405/Kconfig"
source "board/esd/hh405/Kconfig"
source "board/esd/hub405/Kconfig" source "board/esd/hub405/Kconfig"
source "board/esd/ocrtc/Kconfig" source "board/esd/ocrtc/Kconfig"
source "board/esd/pci405/Kconfig" source "board/esd/pci405/Kconfig"

12
board/esd/hh405/Kconfig
Unescape View File

@ -1,12 +0,0 @@
if TARGET_HH405
config SYS_BOARD
default "hh405"
config SYS_VENDOR
default "esd"
config SYS_CONFIG_NAME
default "HH405"
endif

6
board/esd/hh405/MAINTAINERS
Unescape View File

@ -1,6 +0,0 @@
HH405 BOARD
M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
S: Maintained
F: board/esd/hh405/
F: include/configs/HH405.h
F: configs/HH405_defconfig

11
board/esd/hh405/Makefile
Unescape View File

@ -1,11 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = hh405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
../common/auto_update.o

85
board/esd/hh405/flash.c
Unescape View File

@ -1,85 +0,0 @@
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
/*
* include common flash code (for esd boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
static void flash_get_offsets (ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0;
int i;
uint pbcr;
unsigned long base_b0;
int size_val = 0;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
flash_info[0].size = size_b0;
return (size_b0);
}

5034
board/esd/hh405/fpgadata.c
View File

File diff suppressed because it is too large Load Diff

895
board/esd/hh405/hh405.c
Unescape View File

@ -1,895 +0,0 @@
/*
* (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006-2007
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#include <pci.h>
#include <sm501.h>
DECLARE_GLOBAL_DATA_PTR;
/* FPGA internal regs */
#define FPGA_CTRL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
#define FPGA_STATUS ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
#define FPGA_CTR ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
#define FPGA_BL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
/* FPGA Control Reg */
#define FPGA_CTRL_REV0 0x0001
#define FPGA_CTRL_REV1 0x0002
#define FPGA_CTRL_VGA0_BL 0x0004
#define FPGA_CTRL_VGA0_BL_MODE 0x0008
#define FPGA_CTRL_CF_RESET 0x0040
#define FPGA_CTRL_PS2_PWR 0x0080
#define FPGA_CTRL_CF_PWRN 0x0100 /* low active */
#define FPGA_CTRL_CF_BUS_EN 0x0200
#define FPGA_CTRL_LCD_CLK 0x7000 /* mask for lcd clock */
#define FPGA_CTRL_OW_ENABLE 0x8000
#define FPGA_STATUS_CF_DETECT 0x8000
#ifdef CONFIG_VIDEO_SM501
#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
(((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
#ifdef CONFIG_VIDEO_SM501_8BPP
#error CONFIG_VIDEO_SM501_8BPP not supported.
#endif /* CONFIG_VIDEO_SM501_8BPP */
#ifdef CONFIG_VIDEO_SM501_16BPP
#define BPP 16
/*
* 800x600 display B084SN03: PCLK = 40MHz
* => 2*PCLK = 80MHz
* 336/4 = 84MHz
* => PCLK = 84MHz
*/
static const SMI_REGS init_regs_800x600 [] =
{
#if 1 /* test-only */
{0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
#else
{0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
#endif
{0x00004, SWAP32(0x00000000)},
/* clocks for pm1... */
{0x00048, SWAP32(0x00021807)},
{0x0004C, SWAP32(0x221a0a01)},
{0x00054, SWAP32(0x00000001)},
/* clocks for pm0... */
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x221a0a01)},
{0x00054, SWAP32(0x00000000)},
/* GPIO */
{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
{0x80020, SWAP32(0x02580320)}, /* panel plane br location */
{0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
{0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
{0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
{0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
{0x80200, SWAP32(0x00010000)}, /* crt display control */
{0, 0}
};
/*
* 1024x768 display G150XG02: PCLK = 65MHz
* => 2*PCLK = 130MHz
* 288/2 = 144MHz
* => PCLK = 72MHz
*/
static const SMI_REGS init_regs_1024x768 [] =
{
{0x00004, SWAP32(0x00000000)},
/* clocks for pm1... */
{0x00048, SWAP32(0x00021807)},
{0x0004C, SWAP32(0x011a0a01)},
{0x00054, SWAP32(0x00000001)},
/* clocks for pm0... */
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x011a0a01)},
{0x00054, SWAP32(0x00000000)},
/* GPIO */
{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
{0x80020, SWAP32(0x03000400)}, /* panel plane br location */
{0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
{0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
{0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
{0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
{0x80200, SWAP32(0x00010000)}, /* crt display control */
{0, 0}
};
#endif /* CONFIG_VIDEO_SM501_16BPP */
#ifdef CONFIG_VIDEO_SM501_32BPP
#define BPP 32
/*
* 800x600 display B084SN03: PCLK = 40MHz
* => 2*PCLK = 80MHz
* 336/4 = 84MHz
* => PCLK = 84MHz
*/
static const SMI_REGS init_regs_800x600 [] =
{
#if 0 /* test-only */
{0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
#else
{0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
#endif
{0x00004, SWAP32(0x00000000)},
/* clocks for pm1... */
{0x00048, SWAP32(0x00021807)},
{0x0004C, SWAP32(0x221a0a01)},
{0x00054, SWAP32(0x00000001)},
/* clocks for pm0... */
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x221a0a01)},
{0x00054, SWAP32(0x00000000)},
/* GPIO */
{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
{0x80020, SWAP32(0x02580320)}, /* panel plane br location */
{0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
{0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
{0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
{0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
{0x80200, SWAP32(0x00010000)}, /* crt display control */
{0, 0}
};
/*
* 1024x768 display G150XG02: PCLK = 65MHz
* => 2*PCLK = 130MHz
* 288/2 = 144MHz
* => PCLK = 72MHz
*/
static const SMI_REGS init_regs_1024x768 [] =
{
{0x00004, SWAP32(0x00000000)},
/* clocks for pm1... */
{0x00048, SWAP32(0x00021807)},
{0x0004C, SWAP32(0x011a0a01)},
{0x00054, SWAP32(0x00000001)},
/* clocks for pm0... */
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x011a0a01)},
{0x00054, SWAP32(0x00000000)},
/* GPIO */
{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
{0x80020, SWAP32(0x03000400)}, /* panel plane br location */
{0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
{0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
{0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
{0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
{0x80200, SWAP32(0x00010000)}, /* crt display control */
{0, 0}
};
#endif /* CONFIG_VIDEO_SM501_32BPP */
#endif /* CONFIG_VIDEO_SM501 */
#if 0
#define FPGA_DEBUG
#endif
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};
/*
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp_320[] =
{
#include "logo_320_240_4bpp.c"
};
unsigned char logo_bmp_320_8bpp[] =
{
#include "logo_320_240_8bpp.c"
};
unsigned char logo_bmp_640[] =
{
#include "logo_640_480_24bpp.c"
};
unsigned char logo_bmp_1024[] =
{
#include "logo_1024_768_8bpp.c"
};
/*
* include common lcd code (for esd boards)
*/
#include "../common/lcd.c"
#include "../common/s1d13704_320_240_4bpp.h"
#include "../common/s1d13705_320_240_8bpp.h"
#include "../common/s1d13806_640_480_16bpp.h"
#include "../common/s1d13806_1024_768_8bpp.h"
/*
* include common auto-update code (for esd boards)
*/
#include "../common/auto_update.h"
au_image_t au_image[] = {
{"hh405/preinst.img", 0, -1, AU_SCRIPT},
{"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
{"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
{"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
{"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
{"hh405/postinst.img", 0, 0, AU_SCRIPT},
};
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
/*
* Get version of HH405 board from GPIO's
*/
int board_revision(void)
{
unsigned long osrh_reg;
unsigned long isr1h_reg;
unsigned long tcr_reg;
unsigned long value;
/*
* Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
*/
osrh_reg = in_be32((void *)GPIO0_OSRH);
isr1h_reg = in_be32((void *)GPIO0_ISR1H);
tcr_reg = in_be32((void *)GPIO0_TCR);
out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
udelay(1000); /* wait some time before reading input */
value = in_be32((void *)GPIO0_IR) & 0x80400000; /* get config bits */
/*
* Restore GPIO settings
*/
out_be32((void *)GPIO0_OSRH, osrh_reg); /* output select */
out_be32((void *)GPIO0_ISR1H, isr1h_reg); /* input select */
out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
if (value & 0x80000000) {
/* Revision 1.0 or 1.1 detected */
return 1;
} else {
if (value & 0x00400000) {
/* unused */
return 3;
} else {
return 2;
}
}
}
int board_early_init_f (void)
{
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}
int cf_enable(void)
{
int i;
if (gd->board_type >= 2) {
if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
for (i=0; i<300; i++)
udelay(1000);
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
for (i=0; i<20; i++)
udelay(1000);
}
} else {
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
}
}
return 0;
}
int misc_init_r (void)
{
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
char *str;
unsigned long contrast0 = 0xffffffff;
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
if (status != 0) {
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index+1]));
index += len+3;
}
putc ('\n');
/* delayed reboot */
for (i=20; i>0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++)
udelay(1000);
}
putc ('\n');
do_reset(NULL, 0, 0, NULL);
}
puts("FPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("%s ", &(dst[index+1]));
index += len+3;
}
putc ('\n');
free(dst);
/*
* Reset FPGA via FPGA_INIT pin
*/
/* setup FPGA_INIT as output */
out_be32((void *)GPIO0_TCR,
in_be32((void *)GPIO0_TCR) | FPGA_INIT);
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */
udelay(1000); /* wait 1ms */
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */
udelay(1000); /* wait 1ms */
/*
* Write Board revision into FPGA
*/
out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
/*
* Setup and enable EEPROM write protection
*/
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
/*
* Reset touch-screen controller
*/
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
udelay(1000);
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
/*
* Enable power on PS/2 interface (with reset)
*/
out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
for (i=0;i<500;i++)
udelay(1000);
out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
/*
* Get contrast value from environment variable
*/
str = getenv("contrast0");
if (str) {
contrast0 = simple_strtol(str, NULL, 16);
if (contrast0 > 255) {
printf("ERROR: contrast0 value too high (0x%lx)!\n",
contrast0);
contrast0 = 0xffffffff;
}
}
/*
* Init lcd interface and display logo
*/
str = getenv("bd_type");
if (strcmp(str, "ppc230") == 0) {
/*
* Switch backlight on
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
out_be16(FPGA_BL, 0x0000);
lcd_setup(1, 0);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_1024_768_8bpp,
sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
logo_bmp_1024, sizeof(logo_bmp_1024));
} else if (strcmp(str, "ppc220") == 0) {
/*
* Switch backlight on
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
out_be16(FPGA_BL, 0x0000);
lcd_setup(1, 0);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
logo_bmp_640, sizeof(logo_bmp_640));
} else if (strcmp(str, "ppc215") == 0) {
/*
* Set default display contrast voltage
*/
if (contrast0 == 0xffffffff) {
out_be16(FPGA_CTR, 0x0082);
} else {
out_be16(FPGA_CTR, contrast0);
}
out_be16(FPGA_BL, 0xffff);
/*
* Switch backlight on
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
FPGA_CTRL_VGA0_BL |
FPGA_CTRL_VGA0_BL_MODE);
/*
* Set lcd clock (small epson)
*/
out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
udelay(100); /* wait for 100 us */
lcd_setup(0, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13705_320_240_8bpp,
sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
} else if (strcmp(str, "ppc210") == 0) {
/*
* Set default display contrast voltage
*/
if (contrast0 == 0xffffffff) {
out_be16(FPGA_CTR, 0x0060);
} else {
out_be16(FPGA_CTR, contrast0);
}
out_be16(FPGA_BL, 0xffff);
/*
* Switch backlight on
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
FPGA_CTRL_VGA0_BL |
FPGA_CTRL_VGA0_BL_MODE);
/*
* Set lcd clock (small epson), enable 1-wire interface
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
LCD_CLK_08330 |
FPGA_CTRL_OW_ENABLE);
lcd_setup(0, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
#ifdef CONFIG_VIDEO_SM501
} else {
pci_dev_t devbusfn;
/*
* Is SM501 connected (ppc221/ppc231)?
*/
devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
if (devbusfn != -1) {
puts("VGA: SM501 with 8 MB ");
if (strcmp(str, "ppc221") == 0) {
printf("(800*600, %dbpp)\n", BPP);
out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
} else if (strcmp(str, "ppc231") == 0) {
printf("(1024*768, %dbpp)\n", BPP);
out_be16(FPGA_BL, 0x0000);
} else {
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
return 0;
}
} else {
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
return 0;
}
#endif /* CONFIG_VIDEO_SM501 */
}
cf_enable();
return (0);
}
/*
* Check Board Identity:
*/
int checkboard (void)
{
char str[64];
int i = getenv_f("serial#", str, sizeof(str));
puts ("Board: ");
if (i == -1) {
puts ("### No HW ID - assuming HH405");
} else {
puts(str);
}
if (getenv_f("bd_type", str, sizeof(str)) != -1) {
printf(" (%s", str);
} else {
puts(" (Missing bd_type!");
}
gd->board_type = board_revision();
printf(", Rev %ld.x)\n", gd->board_type);
return 0;
}
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
if (((gd->board_type >= 2) &&
(in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
(gd->board_type < 2)) {
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
cf_enable();
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) &
~FPGA_CTRL_CF_RESET);
} else { /* release RESET */
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
FPGA_CTRL_CF_RESET);
}
}
}
#endif /* CONFIG_IDE_RESET */
#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
* 0: disable write
* 1: enable write
* Returns: -1: wrong device address
* 0: dis-/en- able done
* 0/1: current state if <state> was -1.
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
} else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
state = (0 == (in_be32((void *)GPIO0_OR) &
CONFIG_SYS_EEPROM_WP));
break;
}
}
return state;
}
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int query = argc == 1;
int state = 0;
if (query) {
/* Query write access state. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
puts ("Query of write access state failed.\n");
} else {
printf ("Write access for device 0x%0x is %sabled.\n",
CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0) {
puts ("Setup of write access state failed.\n");
}
}
return state;
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"Enable / disable / query EEPROM write access",
""
);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
#ifdef CONFIG_VIDEO_SM501
#ifdef CONFIG_CONSOLE_EXTRA_INFO
/*
* Return text to be printed besides the logo.
*/
void video_get_info_str (int line_number, char *info)
{
char str[64];
char str2[64];
int i = getenv_f("serial#", str2, sizeof(str));
if (line_number == 1) {
sprintf(str, " Board: ");
if (i == -1) {
strcat(str, "### No HW ID - assuming HH405");
} else {
strcat(str, str2);
}
if (getenv_f("bd_type", str2, sizeof(str2)) != -1) {
strcat(str, " (");
strcat(str, str2);
} else {
strcat(str, " (Missing bd_type!");
}
sprintf(str2, ", Rev %ld.x)", gd->board_type);
strcat(str, str2);
strcpy(info, str);
} else {
info [0] = '\0';
}
}
#endif /* CONFIG_CONSOLE_EXTRA_INFO */
/*
* Returns SM501 register base address. First thing called in the driver.
*/
unsigned int board_video_init (void)
{
pci_dev_t devbusfn;
u32 addr;
/*
* Is SM501 connected (ppc221/ppc231)?
*/
devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
if (devbusfn != -1) {
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
return (addr & 0xfffffffe);
}
return 0;
}
/*
* Returns SM501 framebuffer address
*/
unsigned int board_video_get_fb (void)
{
pci_dev_t devbusfn;
u32 addr;
/*
* Is SM501 connected (ppc221/ppc231)?
*/
devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
if (devbusfn != -1) {
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
addr &= 0xfffffffe;
#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
#endif
return addr;
}
return 0;
}
/*
* Called after initializing the SM501 and before clearing the screen.
*/
void board_validate_screen (unsigned int base)
{
}
/*
* Return a pointer to the initialization sequence.
*/
const SMI_REGS *board_get_regs (void)
{
char *str;
str = getenv("bd_type");
if (strcmp(str, "ppc221") == 0) {
return init_regs_800x600;
} else {
return init_regs_1024x768;
}
}
int board_get_width (void)
{
char *str;
str = getenv("bd_type");
if (strcmp(str, "ppc221") == 0) {
return 800;
} else {
return 1024;
}
}
int board_get_height (void)
{
char *str;
str = getenv("bd_type");
if (strcmp(str, "ppc221") == 0) {
return 600;
} else {
return 768;
}
}
#endif /* CONFIG_VIDEO_SM501 */
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
#endif
}

5087
board/esd/hh405/logo_1024_768_8bpp.c
View File

File diff suppressed because it is too large Load Diff

454
board/esd/hh405/logo_320_240_4bpp.c
Unescape View File

@ -1,454 +0,0 @@
0x1f, 0x8b, 0x08, 0x08, 0x9c, 0x03, 0x94, 0x3f,
0x00, 0x03, 0x48, 0x6f, 0x6c, 0x7a, 0x48, 0x65,
0x72, 0x5f, 0x4c, 0x6f, 0x67, 0x6f, 0x5f, 0x33,
0x32, 0x30, 0x78, 0x32, 0x34, 0x30, 0x5f, 0x6d,
0x69, 0x74, 0x74, 0x65, 0x5f, 0x31, 0x36, 0x67,
0x2e, 0x62, 0x6d, 0x70, 0x00, 0xed, 0x9c, 0xfd,
0x6b, 0x1b, 0x47, 0x1a, 0xc7, 0x9f, 0xae, 0xa2,
0xe8, 0x8c, 0x4b, 0x42, 0xff, 0x03, 0xb1, 0x26,
0x2f, 0x26, 0xa5, 0x67, 0x2c, 0x52, 0xd7, 0xf8,
0xb8, 0x1e, 0xb1, 0xfb, 0x62, 0xc2, 0x81, 0xa9,
0xa3, 0xe6, 0x42, 0x43, 0x02, 0x21, 0xf1, 0x35,
0x57, 0x38, 0x4c, 0x8a, 0xbd, 0x71, 0x1d, 0xe2,
0xa3, 0x70, 0x89, 0x4c, 0x8f, 0x62, 0xdc, 0x4b,
0xed, 0x8d, 0x84, 0xfd, 0xd3, 0x71, 0x77, 0x0e,
0x94, 0x90, 0x50, 0x7c, 0x3a, 0x09, 0x29, 0xb4,
0xe4, 0x87, 0x9c, 0x85, 0xfc, 0x17, 0x14, 0x42,
0x8a, 0x31, 0xc5, 0x62, 0xd7, 0xb4, 0x04, 0x63,
0x24, 0x76, 0xee, 0x79, 0x66, 0x66, 0x57, 0x2b,
0xeb, 0xd5, 0x24, 0x75, 0x0b, 0x9d, 0x2f, 0x28,
0xfb, 0x36, 0x3b, 0xf3, 0xd9, 0x67, 0xe6, 0x79,
0x66, 0x76, 0x66, 0x9d, 0x13, 0xbf, 0x1f, 0xff,
0x1c, 0xb8, 0xc6, 0xf1, 0x77, 0x14, 0x7f, 0xbf,
0x7b, 0x01, 0x60, 0x13, 0xb7, 0x2f, 0xc0, 0x3e,
0x70, 0x15, 0x6b, 0x17, 0x3f, 0xbf, 0x5e, 0x7a,
0xe9, 0x25, 0xd0, 0x75, 0x1d, 0x22, 0x91, 0x08,
0x0c, 0x0c, 0x0c, 0x40, 0x34, 0x1a, 0x85, 0x91,
0x91, 0x11, 0x30, 0x0c, 0x03, 0x62, 0xb1, 0x18,
0x98, 0xa6, 0x09, 0x4b, 0x4b, 0x4b, 0x90, 0x4a,
0xa5, 0x20, 0x97, 0xcb, 0xc1, 0x37, 0xdf, 0x7c,
0x03, 0x96, 0x65, 0x01, 0x63, 0x8c, 0x7e, 0x4a,
0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
0x4a, 0x4a, 0x4a, 0x4a, 0xbf, 0x6c, 0x95, 0x72,
0xf9, 0x9f, 0x1a, 0xa1, 0xa1, 0xbe, 0x87, 0xd0,
0x4f, 0x8d, 0xd0, 0x50, 0x9b, 0x8a, 0xef, 0x99,
0xa4, 0xf8, 0xb8, 0x9c, 0xdd, 0xdf, 0xe1, 0xd8,
0xb4, 0x21, 0x3e, 0xb1, 0x87, 0xb2, 0xaa, 0x53,
0xd9, 0x55, 0xa7, 0x76, 0xc8, 0xb2, 0x5b, 0x48,
0xe9, 0xd8, 0x56, 0xd3, 0x8c, 0x2a, 0xf5, 0x34,
0x0c, 0x10, 0xc8, 0x72, 0xbe, 0xfb, 0x00, 0xbf,
0xa1, 0x3c, 0x70, 0x0b, 0x93, 0xec, 0x07, 0x9d,
0x6b, 0x75, 0x5b, 0x3f, 0xc6, 0x9c, 0xaf, 0x00,
0x12, 0xf7, 0xf4, 0x29, 0xa7, 0x5b, 0xb7, 0xd9,
0x6c, 0x47, 0x96, 0x6d, 0x77, 0x77, 0x32, 0xf6,
0xad, 0x7e, 0x8e, 0x15, 0xaf, 0x80, 0xb6, 0x3a,
0x7b, 0x88, 0x3d, 0x04, 0x71, 0xf3, 0xc6, 0x10,
0x40, 0x90, 0xe9, 0x3a, 0xe6, 0xf8, 0x8e, 0x3e,
0xc5, 0x66, 0x71, 0xe7, 0x89, 0xfe, 0x3a, 0x63,
0x9f, 0xe9, 0xbf, 0xc6, 0x47, 0xc0, 0x8b, 0x81,
0x38, 0x2b, 0xe9, 0x47, 0xb0, 0x14, 0xbd, 0xa3,
0x25, 0x52, 0xfa, 0x93, 0x1d, 0x02, 0xdc, 0x84,
0x20, 0xee, 0x68, 0x98, 0xef, 0x53, 0xfe, 0x67,
0x3a, 0x18, 0x70, 0xb8, 0xec, 0x2d, 0x68, 0x67,
0x5b, 0xf4, 0x10, 0x33, 0x30, 0xe5, 0xe0, 0x31,
0x9b, 0xd1, 0x16, 0xd9, 0x76, 0xb8, 0x8d, 0xb1,
0x27, 0x70, 0x0e, 0x7f, 0x00, 0x47, 0x46, 0x83,
0xec, 0x01, 0xdd, 0x7c, 0x9d, 0xb1, 0x2e, 0x20,
0x3e, 0x00, 0xcc, 0x67, 0x08, 0xce, 0xb3, 0x19,
0x58, 0xc4, 0x9c, 0x11, 0x6d, 0x16, 0x0e, 0x32,
0xe7, 0x0a, 0x2f, 0x8b, 0x95, 0x20, 0x68, 0x33,
0x07, 0xb4, 0x16, 0xf9, 0x0e, 0x75, 0x03, 0x1c,
0x20, 0x4e, 0x2d, 0x1a, 0xc6, 0xbc, 0xb1, 0x88,
0x4e, 0x73, 0x8c, 0xf3, 0x91, 0xfd, 0xec, 0x6d,
0xe4, 0xdb, 0x84, 0x80, 0x89, 0x25, 0x2f, 0x56,
0xf1, 0x39, 0x43, 0xd0, 0x33, 0x07, 0xd8, 0x34,
0x1e, 0xf7, 0x24, 0x47, 0xf1, 0x66, 0x7c, 0xb6,
0xd0, 0x87, 0x15, 0x7c, 0x59, 0xf6, 0xd8, 0xe5,
0x2b, 0x02, 0x4c, 0xcc, 0x0d, 0x69, 0xc4, 0xc7,
0x5a, 0xe7, 0xeb, 0x4d, 0x27, 0xc3, 0xf0, 0x22,
0xf1, 0xf5, 0x59, 0x33, 0xa0, 0x61, 0x2e, 0x58,
0x7e, 0x61, 0x88, 0xfd, 0x80, 0xb9, 0x99, 0xa6,
0xc9, 0xf9, 0x1e, 0x40, 0x1f, 0xbb, 0x5f, 0x93,
0xaf, 0x0b, 0x32, 0xf8, 0x0b, 0xb1, 0xb5, 0x3c,
0xde, 0xa0, 0xb1, 0xaf, 0x20, 0x30, 0x55, 0x34,
0xed, 0xda, 0x7c, 0x6b, 0x64, 0xb7, 0xf5, 0x8e,
0xdd, 0xf1, 0x15, 0x31, 0xd5, 0xd7, 0x10, 0xb2,
0x91, 0x8f, 0x8a, 0x00, 0xcc, 0xa5, 0x1d, 0xef,
0x2e, 0xb0, 0x62, 0x17, 0xbc, 0x4c, 0x09, 0x88,
0xef, 0x2e, 0x16, 0x83, 0x6c, 0x8b, 0xac, 0x8a,
0x2f, 0x0c, 0x96, 0xbd, 0x4e, 0xae, 0x45, 0x09,
0xc1, 0x19, 0xc5, 0x27, 0x45, 0x27, 0xa8, 0xcd,
0x77, 0x17, 0xae, 0x3b, 0xcc, 0xd9, 0xd8, 0x1d,
0x9f, 0x40, 0x08, 0xac, 0x6e, 0xe2, 0xd3, 0xb3,
0x52, 0x17, 0xac, 0x8e, 0x52, 0x76, 0xa4, 0xef,
0x09, 0x46, 0xf0, 0x3d, 0x80, 0x29, 0xaa, 0xf7,
0x6c, 0x2d, 0xfb, 0x61, 0x53, 0xea, 0xe2, 0xa1,
0x89, 0x1e, 0x2e, 0x8c, 0x4c, 0xa8, 0x1d, 0x7c,
0x07, 0x05, 0xdf, 0x90, 0xfc, 0xfb, 0xb1, 0x12,
0x85, 0xb2, 0xdd, 0xf0, 0x6d, 0x71, 0xbe, 0x00,
0xde, 0x34, 0x04, 0xd9, 0x51, 0x78, 0xdd, 0xe2,
0x61, 0x60, 0x9b, 0x0c, 0x26, 0xf8, 0x1e, 0x63,
0xfd, 0x62, 0xf6, 0xd5, 0x7c, 0x74, 0x12, 0xc9,
0x89, 0xaf, 0x70, 0x17, 0x9f, 0x10, 0xe8, 0x41,
0xea, 0xf0, 0x61, 0x85, 0x60, 0xbe, 0x8e, 0x6d,
0xef, 0x9a, 0x0f, 0x5b, 0xb6, 0x2d, 0xe2, 0x33,
0xfa, 0xdb, 0x90, 0xf0, 0xdb, 0x73, 0x0c, 0x63,
0x86, 0x26, 0xf9, 0xc8, 0x7f, 0x23, 0xc0, 0xf9,
0x58, 0x25, 0xdf, 0x63, 0x74, 0xab, 0x48, 0x18,
0xeb, 0xf7, 0x1d, 0xbc, 0xe7, 0x98, 0x00, 0xab,
0xe2, 0x13, 0xf5, 0xbb, 0x1d, 0x16, 0x39, 0x4f,
0xb9, 0xf5, 0xdb, 0x2a, 0xde, 0x32, 0x70, 0x17,
0xad, 0xe2, 0x73, 0x78, 0x31, 0xc4, 0xe7, 0xdc,
0xe5, 0xe7, 0x6a, 0xd8, 0xaf, 0xc8, 0x93, 0x87,
0xc8, 0xd8, 0x10, 0xca, 0xd4, 0xe1, 0x93, 0xf6,
0x93, 0x7c, 0x8b, 0xbb, 0x6b, 0x7f, 0x5b, 0x14,
0xb2, 0xce, 0x33, 0x5e, 0xbf, 0x16, 0xaf, 0xdf,
0xdf, 0x5a, 0xd6, 0x77, 0xbc, 0x9e, 0xbe, 0x86,
0xe0, 0x2a, 0xe7, 0x63, 0x8e, 0x95, 0x5b, 0xa1,
0xaa, 0xe4, 0x7c, 0x78, 0x6d, 0x1b, 0x2d, 0x6e,
0x7d, 0x4b, 0x0f, 0xc1, 0xac, 0x95, 0xd4, 0x50,
0x08, 0xdb, 0x7e, 0xe0, 0xba, 0xcd, 0xca, 0xf5,
0x3b, 0x45, 0xed, 0xd5, 0xc7, 0x37, 0x03, 0x07,
0x4b, 0x43, 0xf4, 0x77, 0x8c, 0x8f, 0x21, 0x5b,
0x22, 0xb4, 0x96, 0xf9, 0xee, 0x8a, 0xb0, 0xbc,
0x49, 0x55, 0x87, 0x4d, 0x64, 0x75, 0x06, 0x5e,
0xa1, 0x16, 0xb9, 0xc8, 0xab, 0x96, 0xa3, 0xb4,
0x8b, 0x84, 0x5e, 0xfb, 0x43, 0x2c, 0xf2, 0x28,
0x6e, 0x3f, 0x92, 0xc3, 0xf9, 0x8e, 0x51, 0x71,
0x5d, 0xf0, 0xba, 0xe0, 0x3b, 0xcf, 0xb8, 0xaf,
0x08, 0xbe, 0x03, 0xd4, 0x84, 0x0e, 0xa2, 0x73,
0xe3, 0xa5, 0x07, 0x80, 0xed, 0x0f, 0x56, 0x5b,
0x8f, 0x2f, 0x64, 0xf5, 0x04, 0xef, 0x47, 0x6c,
0x8c, 0x2d, 0x60, 0x3f, 0xa4, 0xec, 0xee, 0x63,
0x0e, 0xbc, 0x9c, 0x03, 0x82, 0x8f, 0xb2, 0x0a,
0xc3, 0xaa, 0xe4, 0x7b, 0x19, 0xf9, 0xb1, 0x92,
0xc9, 0xab, 0xa9, 0xb7, 0x75, 0xb0, 0xb2, 0x67,
0x84, 0xe1, 0x46, 0xe9, 0x66, 0x7e, 0x9f, 0xcd,
0x8d, 0x48, 0x7c, 0x9b, 0xd0, 0x46, 0x0f, 0x47,
0xf1, 0x25, 0xc3, 0x9c, 0x19, 0x40, 0xff, 0xc5,
0x2b, 0x25, 0x08, 0xb4, 0xda, 0xbf, 0xf5, 0xd8,
0x62, 0x1b, 0x9c, 0x18, 0xc2, 0x46, 0xeb, 0x74,
0x69, 0xd7, 0x1e, 0xe1, 0x76, 0x3b, 0x1a, 0x1d,
0xee, 0xc2, 0x6a, 0xe4, 0x7c, 0x57, 0x4e, 0xe7,
0x6e, 0xe1, 0xbe, 0xe4, 0x03, 0xea, 0x4c, 0x42,
0x26, 0xc0, 0x02, 0xdb, 0xd2, 0x26, 0xb1, 0xe2,
0x0f, 0x60, 0x60, 0x0e, 0x26, 0x96, 0xcf, 0xb2,
0x6f, 0x01, 0x7a, 0xe7, 0xce, 0x22, 0x9a, 0x76,
0x66, 0x8c, 0xac, 0x24, 0xec, 0x07, 0x3d, 0xb7,
0x00, 0x0d, 0xbb, 0x05, 0xc1, 0xdc, 0x3d, 0xde,
0xbf, 0x61, 0x51, 0x5d, 0x44, 0xdd, 0x82, 0x1e,
0x43, 0x20, 0x23, 0x38, 0x35, 0xd1, 0xd2, 0xc9,
0x9b, 0xbb, 0xb1, 0x05, 0x6f, 0xf1, 0xc6, 0x1c,
0x14, 0xf6, 0x1b, 0x85, 0xe3, 0x80, 0x19, 0x4a,
0xbe, 0x30, 0x26, 0xd5, 0x00, 0x0d, 0x9f, 0x21,
0x43, 0x0e, 0x03, 0xda, 0x06, 0x83, 0xdf, 0xa1,
0xae, 0x17, 0xb9, 0x9b, 0x84, 0xdb, 0x91, 0x8f,
0x92, 0x04, 0x6c, 0x97, 0x8f, 0xbb, 0x2d, 0x71,
0x1d, 0xc7, 0xce, 0x13, 0xb7, 0x1a, 0x15, 0xd6,
0xd7, 0x12, 0xdf, 0x03, 0x19, 0x8e, 0x37, 0xa1,
0x13, 0x8d, 0x82, 0x1d, 0x10, 0x0f, 0x26, 0x98,
0xad, 0xe4, 0xe3, 0xf6, 0xc3, 0x5a, 0x41, 0xa2,
0xf3, 0x92, 0x2f, 0xb4, 0x8e, 0x07, 0x0b, 0x33,
0x3c, 0x35, 0x0f, 0x1a, 0x21, 0x6c, 0x0c, 0x14,
0x5f, 0xf0, 0x41, 0x3e, 0x03, 0x7a, 0x0e, 0x00,
0x1a, 0x03, 0x65, 0xe8, 0xb9, 0x16, 0x91, 0xef,
0x74, 0x58, 0xd0, 0x7c, 0x49, 0x69, 0x2d, 0xe4,
0x6b, 0xc3, 0x9b, 0x5b, 0x74, 0x0f, 0x97, 0x6f,
0xcb, 0xb8, 0xf6, 0xdd, 0x3b, 0x87, 0xa6, 0x70,
0xcf, 0x59, 0xeb, 0xee, 0x98, 0xb4, 0xd8, 0xb6,
0x41, 0x9a, 0x60, 0x45, 0x63, 0x12, 0x87, 0x4d,
0x63, 0xdd, 0x91, 0x04, 0xf7, 0x4f, 0x9b, 0x2d,
0x4f, 0xd8, 0x63, 0x1d, 0x7d, 0xf6, 0xf6, 0x70,
0x07, 0x02, 0x38, 0x1b, 0x51, 0xfd, 0x38, 0x8e,
0x5b, 0x58, 0x61, 0x58, 0xef, 0xa1, 0xed, 0x97,
0xdd, 0xc7, 0x27, 0x31, 0x59, 0xe6, 0xbe, 0x7e,
0x1a, 0x8f, 0x96, 0x8d, 0x55, 0xb6, 0x6e, 0x2c,
0x2c, 0x77, 0x1f, 0xa7, 0x21, 0xa5, 0x3d, 0xa6,
0x1f, 0x5f, 0xc0, 0xad, 0x31, 0x59, 0xfc, 0x50,
0xbf, 0xd6, 0x1a, 0x1f, 0xf7, 0x7e, 0xa9, 0x62,
0x5a, 0x6c, 0x93, 0xa9, 0xea, 0x74, 0xfc, 0x9c,
0x23, 0xba, 0x3c, 0x56, 0x8a, 0x67, 0x91, 0x59,
0xa4, 0x2e, 0xa5, 0x56, 0xc5, 0xcd, 0xa9, 0x2c,
0x3f, 0x4c, 0x66, 0xc9, 0x35, 0xb2, 0xee, 0x69,
0xc6, 0x47, 0xac, 0xa9, 0x2c, 0x1f, 0xb6, 0xf2,
0xfb, 0x48, 0x76, 0xb1, 0x46, 0x11, 0x75, 0xf8,
0xda, 0x1c, 0x7b, 0x25, 0xdb, 0x5a, 0x62, 0xde,
0x7f, 0xb4, 0x20, 0x19, 0xa6, 0x9f, 0x87, 0x70,
0x14, 0xd0, 0x31, 0x2c, 0x7a, 0xf5, 0xda, 0x2a,
0x9a, 0x09, 0x6f, 0xdf, 0xb5, 0x5f, 0x33, 0x79,
0x7c, 0x49, 0x73, 0xb5, 0x61, 0xc2, 0xe6, 0xc2,
0xa8, 0x09, 0x20, 0xa2, 0x6a, 0x6d, 0x79, 0xf1,
0x59, 0x14, 0xbc, 0x3b, 0xbe, 0x51, 0x1e, 0xe7,
0x9f, 0x49, 0x3f, 0x70, 0xbe, 0xfa, 0xc5, 0x6e,
0xf9, 0xf8, 0x76, 0x6d, 0xbf, 0x99, 0x67, 0xe7,
0x73, 0x96, 0x87, 0x8f, 0x4f, 0x34, 0xa8, 0x05,
0xbf, 0xfd, 0x70, 0x38, 0xba, 0xe7, 0xf6, 0x6b,
0x2a, 0x9f, 0xf3, 0x38, 0x63, 0xd1, 0x96, 0xf8,
0xa2, 0x51, 0xf9, 0xc0, 0x85, 0xdc, 0x2e, 0x5f,
0x27, 0x9f, 0x51, 0xcd, 0x5f, 0x83, 0xb9, 0xac,
0xea, 0x17, 0x68, 0x25, 0x25, 0x25, 0xa5, 0x5f,
0x9e, 0xf6, 0x36, 0x42, 0x3f, 0x77, 0xd5, 0x9e,
0x51, 0x75, 0x0a, 0x49, 0xe3, 0x47, 0xd7, 0x55,
0xb3, 0xb9, 0xe2, 0x59, 0xab, 0xba, 0x53, 0x2a,
0xde, 0x82, 0x3d, 0x92, 0x3e, 0x10, 0x69, 0xa6,
0xee, 0x23, 0xf1, 0x1d, 0x80, 0xc5, 0xa1, 0xbd,
0xc2, 0x23, 0xc0, 0xa6, 0x8a, 0x44, 0xae, 0x55,
0xe0, 0xf1, 0x19, 0x8d, 0x3d, 0x93, 0xf6, 0xe6,
0x48, 0x63, 0x5d, 0x42, 0xc2, 0x41, 0xff, 0xb4,
0xf9, 0x95, 0xbd, 0xc4, 0x03, 0x38, 0x6c, 0x18,
0x7f, 0x6c, 0xd0, 0x48, 0x47, 0x46, 0x2e, 0x0e,
0xf4, 0xeb, 0x9f, 0x96, 0xf9, 0xd6, 0xf7, 0x16,
0x0f, 0xb4, 0xf7, 0x63, 0x8d, 0x74, 0x13, 0x09,
0x07, 0x22, 0x9d, 0xde, 0x88, 0xac, 0xa8, 0xef,
0x31, 0x1f, 0xec, 0x6f, 0xc8, 0x87, 0x32, 0x46,
0x06, 0xfa, 0x5f, 0x76, 0x0d, 0xf8, 0xf5, 0x9e,
0xf3, 0x35, 0x31, 0x20, 0x6a, 0xfc, 0x52, 0xff,
0xab, 0x72, 0xc4, 0xed, 0xe8, 0xe1, 0xbd, 0xe6,
0x6b, 0x6e, 0xc0, 0x98, 0x71, 0xb1, 0x5f, 0xce,
0x7a, 0xaf, 0x77, 0xef, 0x3d, 0x9f, 0x76, 0xb9,
0x19, 0xdf, 0xcd, 0xf1, 0x8b, 0xaf, 0xf1, 0x16,
0xb8, 0x1d, 0xe9, 0x6e, 0x94, 0x53, 0xcf, 0x84,
0x11, 0xfe, 0x31, 0x00, 0xe7, 0x9b, 0x03, 0xf6,
0x0f, 0x12, 0xdf, 0x53, 0x1f, 0x1f, 0xfd, 0x2f,
0x73, 0x74, 0x33, 0x6e, 0x25, 0x54, 0x67, 0x96,
0xb1, 0xe5, 0x2e, 0xef, 0xaa, 0xce, 0xaf, 0x68,
0xba, 0xee, 0xed, 0xbb, 0xe5, 0xc9, 0x03, 0xff,
0xd6, 0x4d, 0xe1, 0x65, 0xe7, 0xbf, 0xa1, 0x69,
0x05, 0xc7, 0xc6, 0xfb, 0x5f, 0x25, 0x0f, 0x59,
0x1b, 0xf6, 0xf8, 0xda, 0x32, 0x16, 0x2d, 0xd8,
0x41, 0x5b, 0x9a, 0x66, 0x85, 0x49, 0x21, 0xee,
0x43, 0xeb, 0x3c, 0xd7, 0x5e, 0xbc, 0x4a, 0x7a,
0x02, 0x67, 0xf2, 0x96, 0xd4, 0x9a, 0x7b, 0x6b,
0x2f, 0x9e, 0x7a, 0x40, 0xcf, 0xb3, 0x60, 0x59,
0x5b, 0x88, 0x34, 0xe9, 0xa6, 0x98, 0x11, 0xd9,
0xd2, 0x74, 0x5c, 0x27, 0x1e, 0x6e, 0xba, 0x37,
0x34, 0xad, 0xe0, 0xd8, 0x8d, 0x8b, 0x27, 0xc8,
0x3b, 0x6e, 0x95, 0xf9, 0xda, 0xb3, 0xf4, 0xfe,
0x4c, 0x19, 0xca, 0x55, 0xc2, 0x3e, 0xe9, 0xe2,
0x7c, 0xca, 0xb7, 0x37, 0x2b, 0x0e, 0xbe, 0x87,
0x5e, 0x2f, 0x74, 0x3e, 0x2d, 0xf3, 0x31, 0x3e,
0xed, 0x18, 0x5a, 0xa0, 0xf9, 0x05, 0xd0, 0xbc,
0xb9, 0x32, 0xe2, 0xcb, 0x8a, 0x39, 0xed, 0x84,
0x38, 0x14, 0x6a, 0xee, 0x21, 0xb1, 0xf1, 0x81,
0x4f, 0xb1, 0xe8, 0xb1, 0x53, 0x7a, 0x5d, 0xbe,
0x45, 0x46, 0x6f, 0xae, 0xb6, 0xc8, 0xb6, 0x37,
0xe3, 0xf1, 0x49, 0xc7, 0xb7, 0xec, 0x2d, 0xf7,
0xd6, 0xd7, 0x7c, 0x7c, 0xdb, 0x64, 0xbf, 0x6a,
0x3e, 0x2d, 0xed, 0xce, 0xed, 0x90, 0xf6, 0xb5,
0xc0, 0x77, 0xea, 0x24, 0x3e, 0xec, 0x78, 0x99,
0x8f, 0x32, 0x9a, 0xf1, 0xf1, 0x75, 0x62, 0x21,
0x85, 0x54, 0x3c, 0xed, 0xf0, 0x49, 0x51, 0xce,
0xb7, 0x92, 0x4a, 0xdd, 0x13, 0x7b, 0x56, 0x0a,
0xf5, 0xa5, 0x7b, 0xeb, 0x91, 0x4a, 0x3e, 0x78,
0x8f, 0x66, 0xc9, 0x31, 0x71, 0xaa, 0xcc, 0x17,
0xca, 0x33, 0xe6, 0x3d, 0x4f, 0x2b, 0x0d, 0xf0,
0xc6, 0xc8, 0x80, 0x5d, 0x9b, 0x2f, 0xcd, 0x67,
0xd9, 0x00, 0xcb, 0x72, 0xb6, 0x71, 0x44, 0x96,
0xe1, 0xcb, 0x31, 0x3d, 0x44, 0x95, 0x34, 0xcd,
0x59, 0xe8, 0xa1, 0x79, 0x48, 0x8b, 0xc6, 0x6a,
0xb7, 0x1a, 0xf1, 0x95, 0x30, 0xb1, 0x39, 0x2a,
0xb2, 0xc5, 0xb6, 0xd9, 0x6e, 0x33, 0x77, 0x09,
0xb9, 0x35, 0xbe, 0x9b, 0x23, 0xfd, 0xd8, 0xf6,
0x8d, 0x53, 0xe1, 0x7a, 0x7c, 0x18, 0x7f, 0x9c,
0xa4, 0x11, 0x33, 0x13, 0xb6, 0xb3, 0x56, 0xc1,
0xc7, 0x87, 0x67, 0x54, 0xfa, 0x5f, 0x77, 0xf2,
0xed, 0xf7, 0xf1, 0x15, 0x2a, 0xf9, 0x5e, 0xb4,
0x65, 0xab, 0x11, 0x6a, 0xee, 0x20, 0xe8, 0xc1,
0x36, 0x4b, 0xce, 0xf9, 0xf8, 0x32, 0xb4, 0xec,
0x84, 0x46, 0x48, 0xf3, 0x49, 0xb6, 0x10, 0xf2,
0xad, 0x63, 0x6c, 0x39, 0x1d, 0xe7, 0x6b, 0xa9,
0x47, 0xf0, 0xaa, 0xf0, 0xd7, 0x80, 0x99, 0xb1,
0x7d, 0x35, 0xc5, 0x9b, 0x7b, 0x46, 0xf0, 0x05,
0x91, 0xaf, 0x88, 0xdb, 0x93, 0x7c, 0x6a, 0xba,
0xfc, 0xd8, 0x78, 0xed, 0x15, 0xc6, 0x31, 0xbd,
0x27, 0x6a, 0xc1, 0x80, 0x17, 0x17, 0x1c, 0x73,
0x07, 0x1f, 0x4d, 0xb3, 0xff, 0x4a, 0xf0, 0xd1,
0xfa, 0x0f, 0x95, 0x19, 0x98, 0xc8, 0xd0, 0x5a,
0x0c, 0xf1, 0x49, 0x7f, 0x9d, 0x88, 0x5b, 0x4e,
0xe5, 0x98, 0x2c, 0x98, 0x17, 0xc6, 0x09, 0x66,
0x04, 0x5f, 0x5f, 0x35, 0xdf, 0x39, 0xbf, 0xfb,
0xe2, 0x13, 0x4d, 0xb7, 0xc0, 0xf7, 0xe7, 0x9a,
0x7c, 0xed, 0x16, 0x27, 0xc1, 0x31, 0xac, 0xc3,
0x43, 0x73, 0x5b, 0x82, 0xec, 0x7a, 0xe4, 0x0b,
0xaf, 0x7d, 0x07, 0xd1, 0x80, 0x4e, 0x05, 0x5f,
0x48, 0x56, 0x1e, 0xd9, 0xbc, 0x24, 0xf9, 0xdc,
0x7c, 0x89, 0xef, 0x09, 0x2d, 0xdc, 0x95, 0x4f,
0xa1, 0xb4, 0xe6, 0xf6, 0x8b, 0x8d, 0x9c, 0x2c,
0x99, 0x73, 0xd1, 0xb2, 0x7f, 0x64, 0x68, 0x05,
0x50, 0xb4, 0xe4, 0xa7, 0x10, 0x48, 0x08, 0x53,
0x60, 0xa1, 0x09, 0x9b, 0x3d, 0xe4, 0x55, 0x27,
0xf9, 0x34, 0x03, 0xcf, 0x54, 0xbc, 0x12, 0xd0,
0x52, 0xe7, 0xa6, 0xe4, 0x74, 0x6a, 0xf2, 0xb5,
0xd9, 0x6e, 0x76, 0xbb, 0xe0, 0xeb, 0x2b, 0xc5,
0xe7, 0x2e, 0xf9, 0xfa, 0x0f, 0xc6, 0x36, 0xb0,
0x4d, 0xd3, 0x8a, 0xc4, 0x16, 0x04, 0xd3, 0x72,
0xaa, 0x17, 0x02, 0x9f, 0xd0, 0xda, 0x74, 0x50,
0x36, 0x7d, 0x52, 0x0f, 0x56, 0xf9, 0xb6, 0x57,
0xd2, 0x19, 0x93, 0xcf, 0x98, 0x93, 0xab, 0xc7,
0x25, 0xdf, 0x31, 0x4b, 0x38, 0x90, 0xf9, 0x19,
0x5f, 0x65, 0x65, 0x6b, 0x3a, 0x35, 0xbf, 0xfb,
0xfe, 0x47, 0x6a, 0x81, 0x6f, 0x7c, 0xb0, 0x94,
0xfa, 0xcf, 0x58, 0x05, 0x9f, 0xf7, 0x4a, 0xc2,
0xbd, 0x44, 0xc4, 0x03, 0x8a, 0xb6, 0xa5, 0x0a,
0x3e, 0x6d, 0x22, 0x61, 0x39, 0xae, 0x7d, 0xb4,
0x1d, 0x0b, 0x2b, 0x2e, 0x1f, 0xd7, 0x9a, 0xe0,
0x73, 0x28, 0xca, 0x3b, 0xbb, 0xe7, 0x2b, 0xa6,
0x92, 0x8d, 0xf8, 0x64, 0x3c, 0x78, 0x8f, 0x56,
0x67, 0xfd, 0x7c, 0xd0, 0x1b, 0x77, 0xec, 0x2b,
0xbb, 0xe0, 0x13, 0x17, 0x36, 0x86, 0x76, 0xc9,
0x77, 0x79, 0x23, 0x95, 0x34, 0x3c, 0xbe, 0xd0,
0x17, 0x8c, 0x7f, 0x70, 0xe4, 0x58, 0x44, 0x12,
0x8a, 0x7b, 0x7c, 0x7d, 0xc4, 0x17, 0xf0, 0xf3,
0x05, 0x27, 0xd2, 0x9e, 0x87, 0x68, 0x93, 0xf2,
0x23, 0x25, 0xc7, 0xe2, 0x9d, 0x21, 0x9d, 0x6f,
0xcb, 0xcb, 0xe3, 0x2d, 0x11, 0x73, 0x28, 0x5b,
0xca, 0xb5, 0x6b, 0x57, 0x7c, 0xc6, 0xe5, 0x52,
0x2a, 0x79, 0x33, 0xe2, 0xf1, 0x51, 0x46, 0x05,
0xec, 0x94, 0xf2, 0x3b, 0xf8, 0xce, 0x52, 0xb4,
0x08, 0x2c, 0xd8, 0xbe, 0x06, 0xde, 0x63, 0x5a,
0x6c, 0xd4, 0xe5, 0x13, 0xb7, 0xf0, 0x2e, 0x2f,
0x63, 0x7b, 0x7c, 0x4e, 0x11, 0x8f, 0x1f, 0x4a,
0x3e, 0xca, 0xd6, 0x12, 0xe3, 0x84, 0xd6, 0xf9,
0x6e, 0x5e, 0x2e, 0xa5, 0x57, 0xe6, 0x87, 0xc3,
0x7e, 0xbe, 0x47, 0xa2, 0x95, 0x17, 0xc3, 0xc1,
0xdb, 0xb6, 0x1b, 0xef, 0xae, 0x93, 0xeb, 0x55,
0xf2, 0x05, 0xe7, 0xd2, 0x76, 0x49, 0x56, 0xd7,
0x1f, 0xa8, 0x0f, 0x24, 0xf7, 0x94, 0x0e, 0xe2,
0xf2, 0x3d, 0x12, 0x3d, 0x20, 0xe7, 0x23, 0xbf,
0x4b, 0xf8, 0x06, 0x3c, 0xad, 0xf1, 0x7d, 0xe0,
0xa4, 0x57, 0xcc, 0x61, 0xdd, 0xc7, 0xe7, 0xd0,
0x2c, 0x0c, 0xf1, 0x75, 0x05, 0x4d, 0x5b, 0xc6,
0x13, 0x8d, 0x77, 0x0a, 0x5a, 0x05, 0x9f, 0x46,
0x89, 0xa4, 0x35, 0x4e, 0xe3, 0x2d, 0x69, 0x5b,
0xdc, 0xfa, 0x49, 0x99, 0xaf, 0xb0, 0x8c, 0xc7,
0x63, 0x82, 0xcf, 0x79, 0x64, 0x18, 0x57, 0xe3,
0xbe, 0x06, 0xd2, 0x52, 0x7c, 0xe1, 0x7c, 0xc9,
0x31, 0x3f, 0x1f, 0x11, 0x04, 0x38, 0x5f, 0xc0,
0xcc, 0xb3, 0x12, 0x37, 0x2d, 0x85, 0xd6, 0x2d,
0xd0, 0x12, 0x36, 0x0f, 0xbd, 0x52, 0x87, 0xcc,
0xbc, 0x0c, 0x3f, 0xbc, 0xb4, 0xb4, 0x7c, 0x98,
0xf7, 0xca, 0x7c, 0xb3, 0xf2, 0xda, 0x3e, 0x6a,
0xb8, 0x98, 0x51, 0x47, 0xc2, 0x1f, 0x01, 0x91,
0x6f, 0x7a, 0xde, 0x6c, 0x02, 0xf8, 0x01, 0x4b,
0x17, 0x52, 0x63, 0x11, 0x59, 0xc1, 0x6e, 0xe7,
0xa9, 0x21, 0x1f, 0xd6, 0xdd, 0x60, 0x5a, 0xb6,
0x17, 0xfa, 0x82, 0x60, 0x96, 0xf3, 0xf9, 0x3b,
0x8d, 0x78, 0xde, 0xdf, 0x5f, 0x25, 0xaa, 0xf9,
0xdc, 0x8b, 0x01, 0xc9, 0x07, 0x79, 0xbe, 0xde,
0xe4, 0x52, 0xc7, 0x3e, 0xd7, 0xbb, 0xb5, 0xcb,
0x8d, 0xdf, 0x43, 0xae, 0xb3, 0x5c, 0x21, 0x35,
0xe7, 0xe7, 0x2b, 0x49, 0x3e, 0x67, 0x08, 0x63,
0x08, 0xe3, 0x5f, 0xcb, 0xd1, 0x7a, 0x35, 0x1e,
0xc2, 0x0e, 0xbe, 0xb3, 0x16, 0x73, 0x57, 0xea,
0x7d, 0x7c, 0xb2, 0xe3, 0xa5, 0x50, 0xe5, 0xfa,
0x02, 0x6f, 0xb8, 0x54, 0x84, 0xed, 0xe7, 0xdb,
0x3f, 0x3d, 0x7b, 0x24, 0x76, 0xe1, 0x68, 0x63,
0xfb, 0x7d, 0xca, 0x0a, 0x56, 0xce, 0x8c, 0xca,
0x37, 0x4c, 0xde, 0x50, 0xb8, 0x69, 0x6c, 0x1a,
0xe9, 0x06, 0xb1, 0x06, 0x69, 0xe0, 0x77, 0x86,
0x5c, 0x13, 0xcf, 0x5e, 0xf3, 0xf5, 0xf9, 0x20,
0x96, 0xe3, 0x4b, 0x5e, 0x40, 0x4b, 0xd8, 0xa2,
0x6d, 0xc9, 0x8e, 0x8d, 0xf8, 0xee, 0xf9, 0xf9,
0x30, 0xb0, 0x1c, 0x62, 0xcc, 0xd7, 0x40, 0xde,
0xbe, 0x81, 0x6c, 0x23, 0x17, 0x1a, 0xc0, 0x99,
0xf3, 0xb1, 0x3c, 0xf2, 0x15, 0x92, 0x6e, 0x05,
0x7b, 0x7c, 0xe8, 0xb9, 0x14, 0x3c, 0xae, 0x62,
0xa3, 0x2a, 0x1a, 0xa7, 0xe9, 0xb1, 0xbf, 0xab,
0xe0, 0x8b, 0xe7, 0x50, 0x2b, 0x14, 0x72, 0x3d,
0x03, 0xde, 0xa9, 0xe6, 0x2b, 0xe0, 0x3b, 0x53,
0x6e, 0x05, 0xb8, 0x63, 0x61, 0x28, 0xcc, 0x53,
0xc8, 0x2e, 0xfb, 0xc7, 0xd5, 0x8f, 0x8f, 0xbe,
0x39, 0xaf, 0xff, 0xbd, 0xfe, 0x30, 0x70, 0xda,
0x34, 0x63, 0xd8, 0xce, 0x2c, 0x2b, 0x65, 0x48,
0x0f, 0xa6, 0x11, 0x01, 0xe7, 0xfb, 0x48, 0xf2,
0xc5, 0x99, 0x5c, 0x60, 0x73, 0x1e, 0x56, 0xf0,
0xa5, 0xbd, 0xbe, 0xc2, 0xe3, 0x8b, 0x57, 0xf3,
0xb9, 0x9d, 0x09, 0xf1, 0xb9, 0xf2, 0x5e, 0xf8,
0x20, 0x76, 0xe1, 0xed, 0x37, 0xcd, 0x7d, 0x9f,
0xbf, 0x5d, 0xdf, 0x7c, 0xa6, 0x79, 0x13, 0x0d,
0x9e, 0xb7, 0x56, 0x4c, 0x69, 0xc0, 0x80, 0xdb,
0xc2, 0x3e, 0x12, 0xaf, 0x44, 0xc1, 0xe9, 0x84,
0xc8, 0xd9, 0x79, 0x44, 0x71, 0x7f, 0xd2, 0xe3,
0x4b, 0xd4, 0xe4, 0xe3, 0xbe, 0x79, 0x6c, 0x95,
0x7f, 0xd2, 0xd9, 0x96, 0x2e, 0xf3, 0x41, 0xc2,
0xe5, 0x73, 0x0a, 0x5e, 0x7c, 0xd6, 0x62, 0x27,
0x62, 0x03, 0x17, 0xde, 0x32, 0x0f, 0xd7, 0x73,
0x10, 0xd3, 0xbc, 0xbd, 0x34, 0x8d, 0xb7, 0xe4,
0xb1, 0x82, 0x0d, 0xf1, 0x8e, 0x19, 0xc0, 0x61,
0xa7, 0x4d, 0x3b, 0x13, 0x79, 0xc7, 0x26, 0xef,
0x9b, 0x30, 0x33, 0x54, 0x29, 0x4e, 0x91, 0x37,
0xa5, 0xc9, 0xbc, 0xb8, 0x4a, 0x30, 0xf4, 0xc1,
0x1d, 0xfd, 0xbc, 0x01, 0x7b, 0x7c, 0xd5, 0xda,
0xa0, 0x6d, 0x27, 0x26, 0x22, 0xbe, 0x94, 0x4d,
0x9d, 0x9d, 0xc8, 0xef, 0x6f, 0x16, 0xef, 0x34,
0x2d, 0xab, 0x94, 0xf4, 0xda, 0xeb, 0xfe, 0xf9,
0xfe, 0xd8, 0x89, 0xee, 0xf0, 0x74, 0x3d, 0x3e,
0xb4, 0xde, 0xd2, 0x12, 0x05, 0x76, 0xac, 0x60,
0x34, 0x20, 0x07, 0xd4, 0xe8, 0xf3, 0x4d, 0xce,
0x87, 0xfd, 0x00, 0x75, 0x5e, 0x01, 0xc3, 0xa4,
0xa6, 0x96, 0xfa, 0x07, 0x37, 0xef, 0x19, 0x79,
0x15, 0xa0, 0x3c, 0x99, 0xed, 0x05, 0x18, 0x53,
0x5e, 0x6c, 0xc3, 0x2d, 0xff, 0x96, 0xc8, 0x95,
0xc8, 0x4e, 0xea, 0x2f, 0x5e, 0xf5, 0x0e, 0xc6,
0x2e, 0xbc, 0xff, 0x96, 0xf9, 0x71, 0xec, 0xe8,
0x7c, 0x6c, 0xc7, 0xfc, 0xb8, 0x68, 0x7a, 0xe6,
0xed, 0x3b, 0xa9, 0xa4, 0x2d, 0xf8, 0x72, 0xc9,
0xb9, 0xe1, 0x88, 0xee, 0xe3, 0x3b, 0x23, 0x5e,
0x6c, 0x00, 0x8e, 0x4e, 0x9b, 0xd8, 0x6f, 0x9a,
0x62, 0xa4, 0xf2, 0xec, 0x7c, 0x63, 0xe5, 0xe1,
0xc1, 0xc4, 0xf4, 0xc7, 0x83, 0x51, 0xe3, 0xc4,
0x8d, 0xc1, 0xf9, 0xe9, 0xda, 0xd3, 0xf8, 0x4b,
0xa9, 0x54, 0x92, 0x37, 0x0a, 0xb4, 0xfb, 0x4a,
0x72, 0x2e, 0x1a, 0xd1, 0xc3, 0xf4, 0x81, 0x12,
0xff, 0xa6, 0x09, 0xff, 0x91, 0x7d, 0x4a, 0x10,
0xf3, 0x36, 0x64, 0xae, 0x9a, 0xbc, 0x0a, 0x10,
0xf6, 0x8a, 0x09, 0x97, 0x77, 0x34, 0x37, 0x91,
0xd8, 0x96, 0xd3, 0xf8, 0x92, 0x7b, 0xda, 0x67,
0x9a, 0xff, 0xc4, 0xf8, 0x32, 0x7d, 0xe1, 0xdf,
0x75, 0xe9, 0x52, 0xff, 0xcd, 0xb8, 0x7c, 0x85,
0x95, 0x79, 0x23, 0x1a, 0xe9, 0xf6, 0xa6, 0x7d,
0x08, 0x4e, 0xcc, 0xea, 0x84, 0x03, 0x11, 0xf4,
0x1d, 0xbd, 0x4a, 0x6e, 0x91, 0xd5, 0x57, 0xe4,
0x75, 0x7f, 0x0a, 0x77, 0xb7, 0x3c, 0xaf, 0x04,
0x97, 0x6f, 0x9b, 0x4b, 0x57, 0xfe, 0x74, 0xe7,
0x5f, 0x87, 0x97, 0xb0, 0x99, 0xd5, 0x10, 0xbd,
0xfc, 0xa7, 0xa4, 0x73, 0x0a, 0x03, 0x8e, 0x9d,
0x8a, 0x44, 0xea, 0x95, 0xf6, 0xdc, 0xd5, 0x11,
0x5f, 0x4a, 0xdd, 0xb9, 0x7f, 0xd8, 0x38, 0x31,
0x78, 0xa7, 0x1e, 0x5c, 0x7a, 0x25, 0x23, 0xdd,
0x9e, 0xa6, 0x99, 0x56, 0x52, 0xa6, 0x71, 0x29,
0x1a, 0x8d, 0x9e, 0xda, 0xb1, 0x12, 0xf1, 0xc6,
0x40, 0x74, 0x20, 0xfa, 0x46, 0xf3, 0x15, 0x8b,
0x5d, 0xea, 0x24, 0x47, 0x48, 0xc6, 0x52, 0x75,
0x94, 0xcb, 0x61, 0x64, 0x77, 0x3f, 0x21, 0x71,
0x78, 0x0d, 0x23, 0xa0, 0x61, 0x8c, 0x10, 0x23,
0xca, 0x5b, 0x8a, 0x88, 0xbe, 0x1b, 0x8d, 0x5e,
0x92, 0x27, 0xbd, 0x2b, 0xb8, 0x79, 0x57, 0xae,
0x54, 0xb8, 0x2b, 0x16, 0xd1, 0x2a, 0xbd, 0xeb,
0xe6, 0x50, 0xb1, 0x2b, 0xee, 0x7f, 0x3f, 0x4d,
0x1d, 0xd0, 0xff, 0x72, 0xf5, 0x85, 0xdd, 0x5a,
0xda, 0x8b, 0xea, 0x18, 0xa8, 0x1c, 0x22, 0x4c,
0xd6, 0x6e, 0xab, 0xcf, 0x5f, 0x19, 0xab, 0xb9,
0x7c, 0xdf, 0xa1, 0x38, 0xc4, 0x67, 0xe5, 0xea,
0x19, 0xfb, 0xf9, 0xab, 0x05, 0xbc, 0x42, 0xa6,
0xcc, 0xc7, 0x24, 0x31, 0x75, 0xfa, 0x3f, 0x3e,
0x5c, 0x2e, 0x97, 0x6f, 0x48, 0x56, 0x65, 0x3e,
0xd9, 0x04, 0x7f, 0x4e, 0x2a, 0xec, 0xfc, 0xd3,
0xb6, 0x9f, 0x1b, 0x60, 0xf5, 0x12, 0x3b, 0x75,
0xf8, 0x96, 0xe8, 0xc8, 0x6d, 0xb7, 0x3f, 0x77,
0xc4, 0x38, 0xc0, 0xf2, 0x6f, 0x7c, 0xe7, 0x9d,
0xca, 0xf3, 0x4d, 0x2f, 0x57, 0xca, 0xa9, 0x95,
0xab, 0xd8, 0x54, 0xc1, 0xb9, 0x88, 0x75, 0x2e,
0x3c, 0x2f, 0x59, 0xf4, 0xed, 0x01, 0xfe, 0x53,
0x63, 0x81, 0x5c, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0xe9, 0x67, 0xac, 0xff, 0x03, 0xdc, 0x41, 0xd4,
0x19, 0x76, 0x96, 0x00, 0x00,

1042
board/esd/hh405/logo_320_240_8bpp.c
View File

File diff suppressed because it is too large Load Diff

8417
board/esd/hh405/logo_640_480_24bpp.c
View File

File diff suppressed because it is too large Load Diff

3
configs/HH405_defconfig
Unescape View File

@ -1,3 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_HH405=y

1
doc/README.scrapyard
Unescape View File

@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact Board Arch CPU Commit Removed Last known maintainer/contact
================================================================================================= =================================================================================================
HH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs@esd.eu> DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs@esd.eu>
DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu> DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
DP405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu> DP405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>

479
include/configs/HH405.h
Unescape View File

@ -1,479 +0,0 @@
/*
* (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_HH405 1 /* ...on a HH405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#undef CONFIG_BOOTARGS
#undef CONFIG_BOOTCOMMAND
#define CONFIG_PREBOOT "autoupd"
#define CONFIG_EXTRA_ENV_SETTINGS \
"pciconfighost=1\0" \
""
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#undef CONFIG_HAS_ETH1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
/*
* Video console
*/
#define CONFIG_VIDEO /* for sm501 video support */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#if 0
#define CONFIG_VIDEO_SM501_32BPP
#else
#define CONFIG_VIDEO_SM501_16BPP
#endif
#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
#endif /* CONFIG_VIDEO */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP
#endif
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
/*-----------------------------------------------------------------------
* RTC stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_RTC_DS1338
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*-----------------------------------------------------------------------
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#if 0 /* test-only */
#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
#endif
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFF80000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */
#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
# define CONFIG_SYS_RAMBOOT 1
#else
# undef CONFIG_SYS_RAMBOOT
#endif
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#if 0 /* test-only */
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#else
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
#endif
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
#define CONFIG_SYS_EEPROM_WREN 1
#if 1 /* test-only */
/* CAT24WC08/16... */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#else
/* CAT24WC32/64... */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
/* 32 byte page write mode using*/
/* last 5 bits of the address */
#endif
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
#define CAN_BA 0xF0000000 /* CAN Base Address */
#define LCD_BA 0xF1000000 /* Epson LCD Base Address */
#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
#define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
/* Memory Bank 4 (Epson LCD) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
#define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
/*-----------------------------------------------------------------------
* LCD Setup
*/
#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
/*-----------------------------------------------------------------------
* Universal Interrupt Controller (UIC) Setup
*/
/*
* define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
*/
#define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
/*-----------------------------------------------------------------------
* FPGA stuff
*/
#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
#define LCD_CLK_OFF 0x0000 /* Off */
#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
#define LCD_CLK_03135 0x2000 /* 3.135 MHz */
#define LCD_CLK_04165 0x3000 /* 4.165 MHz */
#define LCD_CLK_06250 0x4000 /* 6.250 MHz */
#define LCD_CLK_08330 0x5000 /* 8.330 MHz */
#define LCD_CLK_12500 0x6000 /* 12.50 MHz */
#define LCD_CLK_25000 0x7000 /* 25.00 MHz */
#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
* GPIO0[1-9] - Instruction trace outputs -> GPIO
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
* GPIO0[24-27] - UART0 control signal inputs/outputs
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CONFIG_SYS_GPIO0_OSRL 0x40000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
#define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */
#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#if 0
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
#endif
#if 0
#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
#endif
#if 1
#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
#endif
#endif /* __CONFIG_H */
Write Preview
Loading…
Cancel
Save