powerpc/t4qds: Add alternate serdes protocols to align with A-007186

A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
VCO. Only the protocols using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arch/powerpc/cpu/mpc85xx/t4240_serdes.c

@@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+	{27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{37, {NONE, NONE, QSGMII_FM1_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
 		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+	{6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -89,6 +124,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -97,34 +136,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{37, {NONE, NONE, QSGMII_FM2_B, NONE,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, XFI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		XFI_FM2_MAC10, XFI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -137,22 +208,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 };
 static const struct serdes_config serdes3_cfg_tbl[] = {
 	/* SerDes 3 */
+	{1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+	{3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
 	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+	{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
 	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
 	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
 	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+	{11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
 	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
 	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -161,13 +244,21 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
 	/* SerDes 4 */
+	{1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
 	{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+	{3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
 	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+	{5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
 	{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+	{11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
 	{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
+	{13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
 	{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+	{15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
 	{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
 	{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
 	{}
@@ -187,36 +278,66 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+	{27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+	{35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+	{37, {NONE, NONE, QSGMII_FM1_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
 		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{}
 };
 static const struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
+	{6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -225,34 +346,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		NONE, NONE} },
+	{27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{37, {NONE, NONE, QSGMII_FM2_B, NONE,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
 	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		NONE, NONE, NONE, NONE} },
+	{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
 	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, NONE, NONE} },
+	{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
 	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, NONE, NONE} },
+	{55, {NONE, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, NONE,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{56, {NONE, XFI_FM1_MAC10,
 		XFI_FM2_MAC10, NONE,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -265,22 +418,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 };
 static const struct serdes_config serdes3_cfg_tbl[] = {
 	/* SerDes 3 */
+	{1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+	{3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
 	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+	{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
 	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
 	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
 	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+	{11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
+	{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
+	{15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
+	{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -289,12 +454,19 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
 	/* SerDes 4 */
+	{3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
 	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+	{5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
 	{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+	{11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
 	{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+	{13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
 	{}

board/freescale/t4qds/eth.c

@@ -449,7 +449,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 		break;
+	case 27:
 	case 28:
+	case 35:
 	case 36:
 		/* SGMII in Slot1 and Slot2 */
 		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
@@ -465,6 +467,7 @@ int board_eth_init(bd_t *bis)
 						slot_qsgmii_phyaddr[1][2]);
 		}
 		break;
+	case 37:
 	case 38:
 		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
@@ -479,8 +482,11 @@ int board_eth_init(bd_t *bis)
 						slot_qsgmii_phyaddr[1][3]);
 		}
 		break;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
@@ -585,12 +591,17 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 		break;
+	case 6:
 	case 7:
+	case 12:
 	case 13:
 	case 14:
+	case 15:
 	case 16:
+	case 21:
 	case 22:
 	case 23:
+	case 24:
 	case 25:
 	case 26:
 		/* XAUI/HiGig in Slot3, SGMII in Slot4 */
@@ -600,7 +611,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
+	case 27:
 	case 28:
+	case 35:
 	case 36:
 		/* SGMII in Slot3 and Slot4 */
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -612,6 +625,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		break;
+	case 37:
 	case 38:
 		/* QSGMII in Slot3 and Slot4 */
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -623,8 +637,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
 		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
 		break;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		/* SGMII in Slot3 */
 		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
@@ -637,8 +654,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
+	case 49:
 	case 50:
+	case 51:
 	case 52:
+	case 53:
 	case 54:
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);

board/freescale/t4qds/t4240qds.c

@@ -354,14 +354,18 @@ int config_frontside_crossbar_vsc3316(void)
 			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 	switch (srds_prtcl_s1) {
+	case 37:
 	case 38:
 		/* swap first lane and third lane on slot1 */
 		vsc3316_fsm1_tx[0][1] = 14;
 		vsc3316_fsm1_tx[6][1] = 0;
 		vsc3316_fsm1_rx[1][1] = 2;
 		vsc3316_fsm1_rx[6][1] = 13;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		/* swap first lane and third lane on slot2 */
 		vsc3316_fsm1_tx[2][1] = 8;
@@ -382,17 +386,24 @@ int config_frontside_crossbar_vsc3316(void)
 				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 	switch (srds_prtcl_s2) {
+	case 37:
 	case 38:
 		/* swap first lane and third lane on slot3 */
 		vsc3316_fsm2_tx[2][1] = 11;
 		vsc3316_fsm2_tx[5][1] = 4;
 		vsc3316_fsm2_rx[2][1] = 9;
 		vsc3316_fsm2_rx[4][1] = 7;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
+	case 49:
 	case 50:
+	case 51:
 	case 52:
+	case 53:
 	case 54:
 		/* swap first lane and third lane on slot4 */
 		vsc3316_fsm2_tx[6][1] = 3;
@@ -425,6 +436,7 @@ int config_backside_crossbar_mux(void)
 	case 0:
 		/* SerDes3 is not enabled */
 		break;
+	case 1:
 	case 2:
 	case 9:
 	case 10:
@@ -434,13 +446,20 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD3MX_SLOT5;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 3:
 	case 4:
+	case 5:
 	case 6:
+	case 7:
 	case 8:
+	case 11:
 	case 12:
+	case 13:
 	case 14:
+	case 15:
 	case 16:
 	case 17:
+	case 18:
 	case 19:
 	case 20:
 		/* SD3(4:7) => SLOT6(0:3) */
@@ -462,6 +481,7 @@ int config_backside_crossbar_mux(void)
 	case 0:
 		/* SerDes4 is not enabled */
 		break;
+	case 1:
 	case 2:
 		/* 10b, SD4(0:7) => SLOT7(0:7) */
 		brdcfg = QIXIS_READ(brdcfg[12]);
@@ -469,8 +489,11 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD4MX_SLOT7;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 3:
 	case 4:
+	case 5:
 	case 6:
+	case 7:
 	case 8:
 		/* x1b, SD4(4:7) => SLOT8(0:3) */
 		brdcfg = QIXIS_READ(brdcfg[12]);
@@ -478,9 +501,13 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD4MX_SLOT8;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 9:
 	case 10:
+	case 11:
 	case 12:
+	case 13:
 	case 14:
+	case 15:
 	case 16:
 	case 18:
 		/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */

board/freescale/t4qds/t4_rcw.cfg

@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-#serdes protocol  1_28_6_12
+#serdes protocol  1_27_5_11
 16070019 18101916 00000000 00000000
-04383060 30548c00 ec020000 f5000000
+04362858 30548c00 ec020000 f5000000
 00000000 ee0000ee 00000000 000307fc
 00000000 00000000 00000000 00000028