This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>master
Masahiro Yamada
11 years ago
committed by
Tom Rini
parent
f017cd7f71
commit
acc2372db0
@ -1,9 +0,0 @@ |
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if TARGET_LWMON |
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config SYS_BOARD |
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default "lwmon" |
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config SYS_CONFIG_NAME |
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default "lwmon" |
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endif |
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@ -1,6 +0,0 @@ |
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LWMON BOARD |
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M: Wolfgang Denk <wd@denx.de> |
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S: Maintained |
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F: board/lwmon/ |
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F: include/configs/lwmon.h |
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F: configs/lwmon_defconfig |
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@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = lwmon.o flash.o pcmcia.o
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@ -1,126 +0,0 @@ |
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Tastaturabfrage: |
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Die Implementierung / Decodierung beruht auf den Angaben aus dem Do- |
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kument "PIC LWE-Tastatur" in der Fassung vom 9. 3. 2001, insbesonde- |
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re Tabelle 3 im Kapitel 4.3 Tastencodes. In U-Boot werden die vom |
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Keyboard-Controller gelesenen Daten hexadezimal codiert in der auto- |
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matisch angelegten Environment-Variablen "keybd" übergeben. Ist kei- |
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ne Taste gedrückt worden, steht dort: |
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keybd=000000000000000000 |
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Der decodierte Tastencode ("keybd") kann mit den "bootargs" an den |
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Linux-Kernel übergeben und dort z. B. in einem Device-Treiber oder |
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einer Applikation ausgewertet werden. |
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Sonderfunktionen beim Booten: |
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Es lassen sich eine oder mehrere (beliebig viele) Tasten oder Tasten- |
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kombinationen definieren, die Sonderfunktionen auslösen, wenn diese |
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Tasten beim Booten (Reset) gedrückt sind. |
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Wird eine eingestellte Taste bzw. Tastenkombination erkannt, so wird |
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in U-Boot noch vor dem Start des "Countdown" und somit vor jedem an- |
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deren Kommando der Inhalt einer dieser Taste bzw. Tastenkombination |
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zugeordneten Environment-Variablen ausführen. |
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Die Environment-Variable "magic_keys" wird als Liste von Zeichen ver- |
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standen, die als Suffix an den Namen "key_magic" angefügt werden und |
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so die Namen der Environment-Variablen definieren, mit denen die |
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Tasten (-kombinationen) festgelegt werden: |
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Ist "magic_keys" NICHT definiert, so wird nur die in der Environment- |
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Variablen "key_magic" codierte Tasten (-kombination) geprüft, und |
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ggf. der Inhalt der Environment-Variablen "key_cmd" ausgeführt (ge- |
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nauer: der Inhalt von "key_cmd" wird der Variablen "preboot" zugewie- |
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sen, die ausgeführt wird, unmittelbar bevor die interaktive Kommando- |
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interpretation beginnt). |
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Enthält "magic_keys" z. B. die Zeichenkette "0123CB*", so werden |
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nacheinander folgende Aktionen ausgeführt: |
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prüfe Tastencode ggf. führe aus Kommando |
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in Variable in Variable |
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----------------------------------- |
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key_magic0 ==> key_cmd0 |
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key_magic1 ==> key_cmd1 |
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key_magic2 ==> key_cmd2 |
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key_magic3 ==> key_cmd3 |
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key_magicC ==> key_cmdC |
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key_magicB ==> key_cmdB |
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key_magicA ==> key_cmdA |
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key_magic* ==> key_cmd* |
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Hinweis: sobald ein aktivierter Tastencode erkannt wurde, wird die |
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Bearbeitung abgebrochen; es wird daher höchstens eines der definier- |
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ten Kommandos ausgeführt, wobei die Priorität durch die Suchreihen- |
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folge festgelegt wird, also durch die Reihenfolge der Zeichen in der |
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Varuiablen "magic_keys". |
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Die Codierung der Tasten, die beim Booten gedrückt werden müssen, um |
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eine Funktion auszulösen, erfolgt nach der Tastaturtabelle. |
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Die Definitionen |
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=> setenv key_magic0 3a+3b |
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=> setenv key_cmd0 setenv bootdelay 30 |
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bedeuten dementsprechend, daß die Tasten mit den Codes 0x3A (Taste |
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"F1") und 0x3B (Taste "F2") gleichzeitig gedrückt werden müssen. Sie |
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können dort eine beliebige Tastenkombination eintragen (jeweils 2 |
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Zeichen für die Hex-Codes der Tasten, und '+' als Trennzeichen). |
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Wird die eingestellte Tastenkombination erkannt, so wird in U-Boot |
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noch vor dem Start des "Countdown" und somit vor jedem anderen Kom- |
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mando das angebene Kommando ausgeführt und somit ein langes Boot- |
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Delay eingetragen. |
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Praktisch könnten Sie also in U-Boot "bootdelay" auf 0 setzen und |
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somit stets ohne jede User-Interaktion automatisch booten, außer, |
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wenn die beiden Tasten "F1" und "F2" beim Booten gedrückt werden: |
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dann würde ein Boot-Delay von 30 Sekunden eingefügt. |
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Hinweis: dem Zeichen '#' kommt innerhalb von "magic_keys" eine beson- |
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dere Bedeutung zu: die dadurch definierte Key-Sequenz schaltet den |
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Monitor in den "Debug-Modus" - das bedeutet zunächst, daß alle weite- |
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ren Meldungen von U-Boot über das LCD-Display ausgegeben werden; |
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außerdem kann man durch das mit dieser Tastenkombination verknüpfte |
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Kommando z. B. die Linux-Bootmeldungen ebenfalls auf das LCD-Display |
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legen, so daß der Boot-Vorgang direkt und ohne weitere Hilfsmittel |
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analysiert werden kann. |
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Beispiel: |
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In U-Boot werden folgende Environment-Variablen gesetzt und abgespei- |
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chert: |
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(1) => setenv magic_keys 01234#X |
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(2) => setenv key_cmd# setenv addfb setenv bootargs \\${bootargs} console=tty0 console=ttyS1,\\${baudrate} |
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(3) => setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\${serverip}:\${rootpath} |
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(4) => setenv addip setenv bootargs \${bootargs} ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off panic=1 |
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(5) => setenv addfb setenv bootargs \${bootargs} console=ttyS1,\${baudrate} |
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(6) => setenv bootcmd bootp\;run nfsargs\;run addip\;run addfb\;bootm |
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Hierbei wird die Linux Commandline (in der Variablen "bootargs") im |
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Boot-Kommando "bootcmd" (6) schrittweise zusammengesetzt: zunächst |
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werden die für Root-Filesystem über NFS erforderlichen Optionen ge- |
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setzt ("run nfsargs", vgl. (3)), dann die Netzwerkkonfiguration an- |
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gefügt ("run addip", vgl. (4)), und schließlich die Systemconsole |
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definiert ("run addfb"). |
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Dabei wird im Normalfall die Definition (5) verwendt; wurde aller- |
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dings beim Reset die entsprechende Taste gedrückt gehalten, so wird |
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diese Definition bei der Ausführung des in (2) definierten Kommandos |
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überschrieben, so daß Linux die Bootmeldungen auch über das Frame- |
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buffer-Device (=LCD-Display) ausgibt. |
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Beachten Sie die Verdoppelung der '\'-Escapes in der Definition von |
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"key_cmd#" - diese ist erforderlich, weil der String _zweimal_ inter- |
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pretiert wird: das erste Mal bei der Eingabe von "key_cmd#", das |
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zweite Mal, wenn der String (als Inhalt von "preboot") ausgeführt |
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wird. |
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@ -1,632 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/* #define DEBUG */ |
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#include <common.h> |
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#include <mpc8xx.h> |
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#if defined(CONFIG_ENV_IS_IN_FLASH) |
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# ifndef CONFIG_ENV_ADDR |
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# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
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# endif |
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# ifndef CONFIG_ENV_SIZE |
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# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
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# endif |
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# ifndef CONFIG_ENV_SECT_SIZE |
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# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE |
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# endif |
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#endif |
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/*---------------------------------------------------------------------*/ |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_data (flash_info_t *info, ulong dest, ulong data); |
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#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
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static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len); |
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#endif |
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static void flash_get_offsets (ulong base, flash_info_t *info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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unsigned long size_b0, size_b1; |
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int i; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM); |
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0: " |
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"ID 0x%lx, Size = 0x%08lx = %ld MB\n", |
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flash_info[0].flash_id, |
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size_b0, size_b0<<20); |
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} |
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debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM); |
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size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); |
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debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); |
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if (size_b1 > size_b0) { |
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printf ("## ERROR: " |
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"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", |
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size_b1, size_b1<<20, |
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size_b0, size_b0<<20 |
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); |
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flash_info[0].flash_id = FLASH_UNKNOWN; |
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flash_info[1].flash_id = FLASH_UNKNOWN; |
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flash_info[0].sector_count = -1; |
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flash_info[1].sector_count = -1; |
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flash_info[0].size = 0; |
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flash_info[1].size = 0; |
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return (0); |
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} |
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debug ("## Before remap: " |
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"BR0: 0x%08x OR0: 0x%08x " |
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"BR1: 0x%08x OR1: 0x%08x\n", |
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memctl->memc_br0, memctl->memc_or0, |
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memctl->memc_br1, memctl->memc_or1); |
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/* Remap FLASH according to real size */ |
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memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH | |
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OR_CSNT_SAM | OR_ACS_DIV1; |
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memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V; |
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debug ("## BR0: 0x%08x OR0: 0x%08x\n", |
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memctl->memc_br0, memctl->memc_or0); |
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/* Re-do sizing to get full correct info */ |
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size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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flash_info[0].size = size_b0; |
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, |
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&flash_info[0]); |
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#endif |
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#ifdef CONFIG_ENV_IS_IN_FLASH |
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/* ENV protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, |
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&flash_info[0]); |
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#endif |
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if (size_b1) { |
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memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH | |
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OR_CSNT_SAM | OR_ACS_DIV1; |
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memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | |
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BR_PS_32 | BR_V; |
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debug ("## BR1: 0x%08x OR1: 0x%08x\n", |
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memctl->memc_br1, memctl->memc_or1); |
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/* Re-do sizing to get full correct info */ |
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size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), |
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&flash_info[1]); |
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flash_info[1].size = size_b1; |
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flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); |
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, |
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&flash_info[1]); |
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#endif |
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#ifdef CONFIG_ENV_IS_IN_FLASH |
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/* ENV protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, |
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&flash_info[1]); |
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#endif |
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} else { |
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memctl->memc_br1 = 0; /* invalidate bank */ |
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memctl->memc_or1 = 0; /* invalidate bank */ |
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debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", |
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memctl->memc_br1, memctl->memc_or1); |
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flash_info[1].flash_id = FLASH_UNKNOWN; |
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flash_info[1].sector_count = -1; |
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flash_info[1].size = 0; |
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} |
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debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); |
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return (size_b0 + size_b1); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base; |
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base += 0x00020000 * 2; /* 128k * 2 chips per bank */ |
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} |
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return; |
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default: |
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printf ("Don't know sector ofsets for flash type 0x%lx\n", |
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info->flash_id); |
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return; |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_AMD: printf ("AMD "); break; |
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case FLASH_MAN_FUJ: printf ("Fujitsu "); break; |
|
||||||
case FLASH_MAN_SST: printf ("SST "); break; |
|
||||||
case FLASH_MAN_STM: printf ("STM "); break; |
|
||||||
case FLASH_MAN_INTEL: printf ("Intel "); break; |
|
||||||
case FLASH_MAN_MT: printf ("MT "); break; |
|
||||||
default: printf ("Unknown Vendor "); break; |
|
||||||
} |
|
||||||
|
|
||||||
switch (info->flash_id & FLASH_TYPEMASK) { |
|
||||||
case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n"); |
|
||||||
break; |
|
||||||
case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n"); |
|
||||||
break; |
|
||||||
case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n"); |
|
||||||
break; |
|
||||||
default: printf ("Unknown Chip Type\n"); |
|
||||||
break; |
|
||||||
} |
|
||||||
|
|
||||||
if (info->size >= (1 << 20)) { |
|
||||||
i = 20; |
|
||||||
} else { |
|
||||||
i = 10; |
|
||||||
} |
|
||||||
printf (" Size: %ld %cB in %d Sectors\n", |
|
||||||
info->size >> i, |
|
||||||
(i == 20) ? 'M' : 'k', |
|
||||||
info->sector_count); |
|
||||||
|
|
||||||
printf (" Sector Start Addresses:"); |
|
||||||
for (i=0; i<info->sector_count; ++i) { |
|
||||||
if ((i % 5) == 0) |
|
||||||
printf ("\n "); |
|
||||||
printf (" %08lX%s", |
|
||||||
info->start[i], |
|
||||||
info->protect[i] ? " (RO)" : " " |
|
||||||
); |
|
||||||
} |
|
||||||
printf ("\n"); |
|
||||||
return; |
|
||||||
} |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* The following code cannot be run from FLASH! |
|
||||||
*/ |
|
||||||
|
|
||||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
|
||||||
{ |
|
||||||
ulong value; |
|
||||||
|
|
||||||
/* Read Manufacturer ID */ |
|
||||||
addr[0] = 0x00900090; |
|
||||||
value = addr[0]; |
|
||||||
|
|
||||||
debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); |
|
||||||
|
|
||||||
switch (value) { |
|
||||||
case AMD_MANUFACT: |
|
||||||
info->flash_id = FLASH_MAN_AMD; |
|
||||||
break; |
|
||||||
case FUJ_MANUFACT: |
|
||||||
info->flash_id = FLASH_MAN_FUJ; |
|
||||||
break; |
|
||||||
case SST_MANUFACT: |
|
||||||
info->flash_id = FLASH_MAN_SST; |
|
||||||
break; |
|
||||||
case STM_MANUFACT: |
|
||||||
info->flash_id = FLASH_MAN_STM; |
|
||||||
break; |
|
||||||
case INTEL_MANUFACT: |
|
||||||
info->flash_id = FLASH_MAN_INTEL; |
|
||||||
break; |
|
||||||
default: |
|
||||||
info->flash_id = FLASH_UNKNOWN; |
|
||||||
info->sector_count = 0; |
|
||||||
info->size = 0; |
|
||||||
addr[0] = 0x00FF00FF; /* restore read mode */ |
|
||||||
return (0); /* no or unknown flash */ |
|
||||||
} |
|
||||||
|
|
||||||
value = addr[1]; /* device ID */ |
|
||||||
|
|
||||||
debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); |
|
||||||
|
|
||||||
switch (value) { |
|
||||||
case INTEL_ID_28F320J3A: |
|
||||||
info->flash_id += FLASH_28F320J3A; |
|
||||||
info->sector_count = 32; |
|
||||||
info->size = 0x00400000 * 2; |
|
||||||
break; /* => 8 MB */ |
|
||||||
|
|
||||||
case INTEL_ID_28F640J3A: |
|
||||||
info->flash_id += FLASH_28F640J3A; |
|
||||||
info->sector_count = 64; |
|
||||||
info->size = 0x00800000 * 2; |
|
||||||
break; /* => 16 MB */ |
|
||||||
|
|
||||||
case INTEL_ID_28F128J3A: |
|
||||||
info->flash_id += FLASH_28F128J3A; |
|
||||||
info->sector_count = 128; |
|
||||||
info->size = 0x01000000 * 2; |
|
||||||
break; /* => 32 MB */ |
|
||||||
|
|
||||||
default: |
|
||||||
info->flash_id = FLASH_UNKNOWN; |
|
||||||
addr[0] = 0x00FF00FF; /* restore read mode */ |
|
||||||
return (0); /* => no or unknown flash */ |
|
||||||
|
|
||||||
} |
|
||||||
|
|
||||||
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { |
|
||||||
printf ("** ERROR: sector count %d > max (%d) **\n", |
|
||||||
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); |
|
||||||
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; |
|
||||||
} |
|
||||||
|
|
||||||
addr[0] = 0x00FF00FF; /* restore read mode */ |
|
||||||
|
|
||||||
return (info->size); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/ |
|
||||||
|
|
||||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
|
||||||
{ |
|
||||||
int flag, prot, sect; |
|
||||||
ulong start, now, last; |
|
||||||
|
|
||||||
debug ("flash_erase: first: %d last: %d\n", s_first, s_last); |
|
||||||
|
|
||||||
if ((s_first < 0) || (s_first > s_last)) { |
|
||||||
if (info->flash_id == FLASH_UNKNOWN) { |
|
||||||
printf ("- missing\n"); |
|
||||||
} else { |
|
||||||
printf ("- no sectors to erase\n"); |
|
||||||
} |
|
||||||
return 1; |
|
||||||
} |
|
||||||
|
|
||||||
if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { |
|
||||||
printf ("Can erase only Intel flash types - aborted\n"); |
|
||||||
return 1; |
|
||||||
} |
|
||||||
|
|
||||||
prot = 0; |
|
||||||
for (sect=s_first; sect<=s_last; ++sect) { |
|
||||||
if (info->protect[sect]) { |
|
||||||
prot++; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
if (prot) { |
|
||||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
|
||||||
prot); |
|
||||||
} else { |
|
||||||
printf ("\n"); |
|
||||||
} |
|
||||||
|
|
||||||
start = get_timer (0); |
|
||||||
last = start; |
|
||||||
/* Start erase on unprotected sectors */ |
|
||||||
for (sect = s_first; sect<=s_last; sect++) { |
|
||||||
if (info->protect[sect] == 0) { /* not protected */ |
|
||||||
vu_long *addr = (vu_long *)(info->start[sect]); |
|
||||||
unsigned long status; |
|
||||||
|
|
||||||
/* Disable interrupts which might cause a timeout here */ |
|
||||||
flag = disable_interrupts(); |
|
||||||
|
|
||||||
*addr = 0x00600060; /* clear lock bit setup */ |
|
||||||
*addr = 0x00D000D0; /* clear lock bit confirm */ |
|
||||||
|
|
||||||
udelay (1000); |
|
||||||
/* This takes awfully long - up to 50 ms and more */ |
|
||||||
while (((status = *addr) & 0x00800080) != 0x00800080) { |
|
||||||
if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
|
||||||
printf ("Timeout\n"); |
|
||||||
*addr = 0x00FF00FF; /* reset to read mode */ |
|
||||||
return 1; |
|
||||||
} |
|
||||||
|
|
||||||
/* show that we're waiting */ |
|
||||||
if ((now - last) > 1000) { /* every second */ |
|
||||||
putc ('.'); |
|
||||||
last = now; |
|
||||||
} |
|
||||||
udelay (1000); /* to trigger the watchdog */ |
|
||||||
} |
|
||||||
|
|
||||||
*addr = 0x00500050; /* clear status register */ |
|
||||||
*addr = 0x00200020; /* erase setup */ |
|
||||||
*addr = 0x00D000D0; /* erase confirm */ |
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */ |
|
||||||
if (flag) |
|
||||||
enable_interrupts(); |
|
||||||
|
|
||||||
/* wait at least 80us - let's wait 1 ms */ |
|
||||||
udelay (1000); |
|
||||||
|
|
||||||
while (((status = *addr) & 0x00800080) != 0x00800080) { |
|
||||||
if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
|
||||||
printf ("Timeout\n"); |
|
||||||
*addr = 0x00B000B0; /* suspend erase */ |
|
||||||
*addr = 0x00FF00FF; /* reset to read mode */ |
|
||||||
return 1; |
|
||||||
} |
|
||||||
|
|
||||||
/* show that we're waiting */ |
|
||||||
if ((now - last) > 1000) { /* every second */ |
|
||||||
putc ('.'); |
|
||||||
last = now; |
|
||||||
} |
|
||||||
udelay (1000); /* to trigger the watchdog */ |
|
||||||
} |
|
||||||
|
|
||||||
*addr = 0x00FF00FF; /* reset to read mode */ |
|
||||||
} |
|
||||||
} |
|
||||||
printf (" done\n"); |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Copy memory to flash, returns: |
|
||||||
* 0 - OK |
|
||||||
* 1 - write timeout |
|
||||||
* 2 - Flash not erased |
|
||||||
* 4 - Flash not identified |
|
||||||
*/ |
|
||||||
|
|
||||||
#define FLASH_WIDTH 4 /* flash bus width in bytes */ |
|
||||||
|
|
||||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
|
||||||
{ |
|
||||||
ulong cp, wp, data; |
|
||||||
int i, l, rc; |
|
||||||
|
|
||||||
if (info->flash_id == FLASH_UNKNOWN) { |
|
||||||
return 4; |
|
||||||
} |
|
||||||
|
|
||||||
wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned start bytes |
|
||||||
*/ |
|
||||||
if ((l = addr - wp) != 0) { |
|
||||||
data = 0; |
|
||||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *)cp); |
|
||||||
} |
|
||||||
for (; i<FLASH_WIDTH && cnt>0; ++i) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
--cnt; |
|
||||||
++cp; |
|
||||||
} |
|
||||||
for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *)cp); |
|
||||||
} |
|
||||||
|
|
||||||
if ((rc = write_data(info, wp, data)) != 0) { |
|
||||||
return (rc); |
|
||||||
} |
|
||||||
wp += FLASH_WIDTH; |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle FLASH_WIDTH aligned part |
|
||||||
*/ |
|
||||||
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
|
||||||
while(cnt >= FLASH_WIDTH) { |
|
||||||
i = CONFIG_SYS_FLASH_BUFFER_SIZE > cnt ? |
|
||||||
(cnt & ~(FLASH_WIDTH - 1)) : CONFIG_SYS_FLASH_BUFFER_SIZE; |
|
||||||
if((rc = write_data_buf(info, wp, src,i)) != 0) |
|
||||||
return rc; |
|
||||||
wp += i; |
|
||||||
src += i; |
|
||||||
cnt -=i; |
|
||||||
} |
|
||||||
#else |
|
||||||
while (cnt >= FLASH_WIDTH) { |
|
||||||
data = 0; |
|
||||||
for (i=0; i<FLASH_WIDTH; ++i) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
} |
|
||||||
if ((rc = write_data(info, wp, data)) != 0) { |
|
||||||
return (rc); |
|
||||||
} |
|
||||||
wp += FLASH_WIDTH; |
|
||||||
cnt -= FLASH_WIDTH; |
|
||||||
} |
|
||||||
#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
|
||||||
|
|
||||||
if (cnt == 0) { |
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned tail bytes |
|
||||||
*/ |
|
||||||
data = 0; |
|
||||||
for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
--cnt; |
|
||||||
} |
|
||||||
for (; i<FLASH_WIDTH; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *)cp); |
|
||||||
} |
|
||||||
|
|
||||||
return (write_data(info, wp, data)); |
|
||||||
} |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Check flash status, returns: |
|
||||||
* 0 - OK |
|
||||||
* 1 - timeout |
|
||||||
*/ |
|
||||||
static int flash_status_check(vu_long *addr, ulong tout, char * prompt) |
|
||||||
{ |
|
||||||
ulong status; |
|
||||||
ulong start; |
|
||||||
|
|
||||||
/* Wait for command completion */ |
|
||||||
start = get_timer (0); |
|
||||||
while(((status = *addr) & 0x00800080) != 0x00800080) { |
|
||||||
if (get_timer(start) > tout) { |
|
||||||
printf("Flash %s timeout at address %p\n", prompt, addr); |
|
||||||
*addr = 0x00FF00FF; /* restore read mode */ |
|
||||||
return (1); |
|
||||||
} |
|
||||||
} |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Write a word to Flash, returns: |
|
||||||
* 0 - OK |
|
||||||
* 1 - write timeout |
|
||||||
* 2 - Flash not erased |
|
||||||
*/ |
|
||||||
static int write_data (flash_info_t *info, ulong dest, ulong data) |
|
||||||
{ |
|
||||||
vu_long *addr = (vu_long *)dest; |
|
||||||
int flag; |
|
||||||
|
|
||||||
/* Check if Flash is (sufficiently) erased */ |
|
||||||
if ((*addr & data) != data) { |
|
||||||
return (2); |
|
||||||
} |
|
||||||
/* Disable interrupts which might cause a timeout here */ |
|
||||||
flag = disable_interrupts(); |
|
||||||
|
|
||||||
*addr = 0x00400040; /* write setup */ |
|
||||||
*addr = data; |
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */ |
|
||||||
if (flag) |
|
||||||
enable_interrupts(); |
|
||||||
|
|
||||||
if (flash_status_check(addr, CONFIG_SYS_FLASH_WRITE_TOUT, "write") != 0) { |
|
||||||
return (1); |
|
||||||
} |
|
||||||
|
|
||||||
*addr = 0x00FF00FF; /* restore read mode */ |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Write a buffer to Flash, returns: |
|
||||||
* 0 - OK |
|
||||||
* 1 - write timeout |
|
||||||
*/ |
|
||||||
static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len) |
|
||||||
{ |
|
||||||
vu_long *addr = (vu_long *)dest; |
|
||||||
int sector; |
|
||||||
int cnt; |
|
||||||
int retcode; |
|
||||||
vu_long * src = (vu_long *)cp; |
|
||||||
vu_long * dst = (vu_long *)dest; |
|
||||||
|
|
||||||
/* find sector */ |
|
||||||
for(sector = info->sector_count - 1; sector >= 0; sector--) { |
|
||||||
if(dest >= info->start[sector]) |
|
||||||
break; |
|
||||||
} |
|
||||||
|
|
||||||
*addr = 0x00500050; /* clear status */ |
|
||||||
*addr = 0x00e800e8; /* write buffer */ |
|
||||||
|
|
||||||
if((retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT, |
|
||||||
"write to buffer")) == 0) { |
|
||||||
cnt = len / FLASH_WIDTH; |
|
||||||
*addr = (cnt-1) | ((cnt-1) << 16); |
|
||||||
while(cnt-- > 0) { |
|
||||||
*dst++ = *src++; |
|
||||||
} |
|
||||||
*addr = 0x00d000d0; /* write buffer confirm */ |
|
||||||
retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT, |
|
||||||
"buffer write"); |
|
||||||
} |
|
||||||
*addr = 0x00FF00FF; /* restore read mode */ |
|
||||||
*addr = 0x00500050; /* clear status */ |
|
||||||
return retcode; |
|
||||||
} |
|
||||||
#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/ |
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,234 +0,0 @@ |
|||||||
#include <common.h> |
|
||||||
#include <mpc8xx.h> |
|
||||||
#include <pcmcia.h> |
|
||||||
#include <i2c.h> |
|
||||||
|
|
||||||
#undef CONFIG_PCMCIA |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_PCMCIA) |
|
||||||
#define CONFIG_PCMCIA |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) |
|
||||||
#define CONFIG_PCMCIA |
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_PCMCIA |
|
||||||
|
|
||||||
#define PCMCIA_BOARD_MSG "LWMON" |
|
||||||
|
|
||||||
/* #define's for MAX1604 Power Switch */ |
|
||||||
#define MAX1604_OP_SUS 0x80 |
|
||||||
#define MAX1604_VCCBON 0x40 |
|
||||||
#define MAX1604_VCC_35 0x20 |
|
||||||
#define MAX1604_VCCBHIZ 0x10 |
|
||||||
#define MAX1604_VPPBON 0x08 |
|
||||||
#define MAX1604_VPPBPBPGM 0x04 |
|
||||||
#define MAX1604_VPPBHIZ 0x02 |
|
||||||
/* reserved 0x01 */ |
|
||||||
|
|
||||||
int pcmcia_hardware_enable(int slot) |
|
||||||
{ |
|
||||||
volatile pcmconf8xx_t *pcmp; |
|
||||||
volatile sysconf8xx_t *sysp; |
|
||||||
uint reg, mask; |
|
||||||
uchar val; |
|
||||||
|
|
||||||
|
|
||||||
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); |
|
||||||
|
|
||||||
/* Switch on PCMCIA port in PIC register 0x60 */ |
|
||||||
reg = pic_read (0x60); |
|
||||||
debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); |
|
||||||
reg &= ~0x10; |
|
||||||
/* reg |= 0x08; Vpp not needed */ |
|
||||||
pic_write (0x60, reg); |
|
||||||
#ifdef DEBUG |
|
||||||
reg = pic_read (0x60); |
|
||||||
printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); |
|
||||||
#endif |
|
||||||
udelay(10000); |
|
||||||
|
|
||||||
sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); |
|
||||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure SIUMCR to enable PCMCIA port B |
|
||||||
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead) |
|
||||||
*/ |
|
||||||
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ |
|
||||||
|
|
||||||
/* clear interrupt state, and disable interrupts */ |
|
||||||
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); |
|
||||||
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Disable interrupts, DMA, and PCMCIA buffers |
|
||||||
* (isolate the interface) and assert RESET signal |
|
||||||
*/ |
|
||||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
|
||||||
reg = 0; |
|
||||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
|
||||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
|
||||||
PCMCIA_PGCRX(_slot_) = reg; |
|
||||||
udelay(500); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Make sure there is a card in the slot, then configure the interface. |
|
||||||
*/ |
|
||||||
udelay(10000); |
|
||||||
debug ("[%d] %s: PIPR(%p)=0x%x\n", |
|
||||||
__LINE__,__FUNCTION__, |
|
||||||
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr); |
|
||||||
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { |
|
||||||
printf (" No Card found\n"); |
|
||||||
return (1); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* Power On. |
|
||||||
*/ |
|
||||||
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); |
|
||||||
reg = pcmp->pcmc_pipr; |
|
||||||
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", |
|
||||||
reg, |
|
||||||
(reg&PCMCIA_VS1(slot))?"n":"ff", |
|
||||||
(reg&PCMCIA_VS2(slot))?"n":"ff"); |
|
||||||
if ((reg & mask) == mask) { |
|
||||||
val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */ |
|
||||||
puts (" 5.0V card found: "); |
|
||||||
} else { |
|
||||||
val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */ |
|
||||||
puts (" 3.3V card found: "); |
|
||||||
} |
|
||||||
|
|
||||||
/* switch VCC on */ |
|
||||||
val |= MAX1604_OP_SUS | MAX1604_VCCBON; |
|
||||||
i2c_set_bus_num(0); |
|
||||||
i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); |
|
||||||
|
|
||||||
udelay(500000); |
|
||||||
|
|
||||||
debug ("Enable PCMCIA buffers and stop RESET\n"); |
|
||||||
reg = PCMCIA_PGCRX(_slot_); |
|
||||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ |
|
||||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ |
|
||||||
PCMCIA_PGCRX(_slot_) = reg; |
|
||||||
|
|
||||||
udelay(250000); /* some cards need >150 ms to come up :-( */ |
|
||||||
|
|
||||||
debug ("# hardware_enable done\n"); |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_PCMCIA) |
|
||||||
int pcmcia_hardware_disable(int slot) |
|
||||||
{ |
|
||||||
volatile immap_t *immap; |
|
||||||
volatile pcmconf8xx_t *pcmp; |
|
||||||
u_long reg; |
|
||||||
uchar val; |
|
||||||
|
|
||||||
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); |
|
||||||
|
|
||||||
immap = (immap_t *)CONFIG_SYS_IMMR; |
|
||||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); |
|
||||||
|
|
||||||
/* remove all power, put output in high impedance state */ |
|
||||||
val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; |
|
||||||
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
|
||||||
i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); |
|
||||||
|
|
||||||
/* Configure PCMCIA General Control Register */ |
|
||||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
|
||||||
reg = 0; |
|
||||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
|
||||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
|
||||||
PCMCIA_PGCRX(_slot_) = reg; |
|
||||||
|
|
||||||
/* Switch off PCMCIA port in PIC register 0x60 */ |
|
||||||
reg = pic_read (0x60); |
|
||||||
debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); |
|
||||||
reg |= 0x10; |
|
||||||
reg &= ~0x08; |
|
||||||
pic_write (0x60, reg); |
|
||||||
#ifdef DEBUG |
|
||||||
reg = pic_read (0x60); |
|
||||||
printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); |
|
||||||
#endif |
|
||||||
udelay(10000); |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
int pcmcia_voltage_set(int slot, int vcc, int vpp) |
|
||||||
{ |
|
||||||
volatile pcmconf8xx_t *pcmp; |
|
||||||
u_long reg; |
|
||||||
uchar val; |
|
||||||
|
|
||||||
debug ("voltage_set: " |
|
||||||
PCMCIA_BOARD_MSG |
|
||||||
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", |
|
||||||
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); |
|
||||||
|
|
||||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); |
|
||||||
/*
|
|
||||||
* Disable PCMCIA buffers (isolate the interface) |
|
||||||
* and assert RESET signal |
|
||||||
*/ |
|
||||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
|
||||||
reg = PCMCIA_PGCRX(_slot_); |
|
||||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
|
||||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
|
||||||
PCMCIA_PGCRX(_slot_) = reg; |
|
||||||
udelay(500); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Turn off all power (switch to high impedance) |
|
||||||
*/ |
|
||||||
debug ("PCMCIA power OFF\n"); |
|
||||||
val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; |
|
||||||
i2c_set_bus_num(0); |
|
||||||
i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); |
|
||||||
|
|
||||||
val = 0; |
|
||||||
switch(vcc) { |
|
||||||
case 0: break; |
|
||||||
case 33: val = MAX1604_VCC_35; break; |
|
||||||
case 50: break; |
|
||||||
default: goto done; |
|
||||||
} |
|
||||||
|
|
||||||
/* Checking supported voltages */ |
|
||||||
|
|
||||||
debug ("PIPR: 0x%x --> %s\n", |
|
||||||
pcmp->pcmc_pipr, |
|
||||||
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); |
|
||||||
|
|
||||||
i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); |
|
||||||
if (val) { |
|
||||||
debug ("PCMCIA powered at %sV\n", |
|
||||||
(val & MAX1604_VCC_35) ? "3.3" : "5.0"); |
|
||||||
} else { |
|
||||||
debug ("PCMCIA powered down\n"); |
|
||||||
} |
|
||||||
|
|
||||||
done: |
|
||||||
debug ("Enable PCMCIA buffers and stop RESET\n"); |
|
||||||
reg = PCMCIA_PGCRX(_slot_); |
|
||||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ |
|
||||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ |
|
||||||
PCMCIA_PGCRX(_slot_) = reg; |
|
||||||
udelay(500); |
|
||||||
|
|
||||||
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", |
|
||||||
slot+'A'); |
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
#endif /* CONFIG_PCMCIA */ |
|
||||||
@ -1,122 +0,0 @@ |
|||||||
/* |
|
||||||
* (C) Copyright 2001 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc) |
|
||||||
/* Do we need any of these for elf? |
|
||||||
__DYNAMIC = 0; */ |
|
||||||
SECTIONS |
|
||||||
{ |
|
||||||
/* Read-only sections, merged into text segment: */ |
|
||||||
. = + SIZEOF_HEADERS; |
|
||||||
.interp : { *(.interp) } |
|
||||||
.hash : { *(.hash) } |
|
||||||
.dynsym : { *(.dynsym) } |
|
||||||
.dynstr : { *(.dynstr) } |
|
||||||
.rel.text : { *(.rel.text) } |
|
||||||
.rela.text : { *(.rela.text) } |
|
||||||
.rel.data : { *(.rel.data) } |
|
||||||
.rela.data : { *(.rela.data) } |
|
||||||
.rel.rodata : { *(.rel.rodata) } |
|
||||||
.rela.rodata : { *(.rela.rodata) } |
|
||||||
.rel.got : { *(.rel.got) } |
|
||||||
.rela.got : { *(.rela.got) } |
|
||||||
.rel.ctors : { *(.rel.ctors) } |
|
||||||
.rela.ctors : { *(.rela.ctors) } |
|
||||||
.rel.dtors : { *(.rel.dtors) } |
|
||||||
.rela.dtors : { *(.rela.dtors) } |
|
||||||
.rel.bss : { *(.rel.bss) } |
|
||||||
.rela.bss : { *(.rela.bss) } |
|
||||||
.rel.plt : { *(.rel.plt) } |
|
||||||
.rela.plt : { *(.rela.plt) } |
|
||||||
.init : { *(.init) } |
|
||||||
.plt : { *(.plt) } |
|
||||||
.text : |
|
||||||
{ |
|
||||||
/* WARNING - the following is hand-optimized to fit within */ |
|
||||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
|
||||||
|
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
|
||||||
common/dlmalloc.o (.text) |
|
||||||
lib/vsprintf.o (.text) |
|
||||||
lib/crc32.o (.text) |
|
||||||
arch/powerpc/lib/extable.o (.text) |
|
||||||
|
|
||||||
. = env_offset; |
|
||||||
common/env_embedded.o(.text) |
|
||||||
|
|
||||||
*(.text) |
|
||||||
*(.got1) |
|
||||||
} |
|
||||||
_etext = .; |
|
||||||
PROVIDE (etext = .); |
|
||||||
.rodata : |
|
||||||
{ |
|
||||||
*(.rodata) |
|
||||||
*(.rodata1) |
|
||||||
*(.rodata.str1.4) |
|
||||||
*(.eh_frame) |
|
||||||
} |
|
||||||
.fini : { *(.fini) } =0 |
|
||||||
.ctors : { *(.ctors) } |
|
||||||
.dtors : { *(.dtors) } |
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */ |
|
||||||
. = (. + 0x0FFF) & 0xFFFFF000; |
|
||||||
_erotext = .; |
|
||||||
PROVIDE (erotext = .); |
|
||||||
.reloc : |
|
||||||
{ |
|
||||||
*(.got) |
|
||||||
_GOT2_TABLE_ = .; |
|
||||||
*(.got2) |
|
||||||
_FIXUP_TABLE_ = .; |
|
||||||
*(.fixup) |
|
||||||
} |
|
||||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
|
||||||
|
|
||||||
.data : |
|
||||||
{ |
|
||||||
*(.data) |
|
||||||
*(.data1) |
|
||||||
*(.sdata) |
|
||||||
*(.sdata2) |
|
||||||
*(.dynamic) |
|
||||||
CONSTRUCTORS |
|
||||||
} |
|
||||||
_edata = .; |
|
||||||
PROVIDE (edata = .); |
|
||||||
|
|
||||||
|
|
||||||
. = ALIGN(4); |
|
||||||
.u_boot_list : { |
|
||||||
KEEP(*(SORT(.u_boot_list*))); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
__start___ex_table = .; |
|
||||||
__ex_table : { *(__ex_table) } |
|
||||||
__stop___ex_table = .; |
|
||||||
|
|
||||||
. = ALIGN(4096); |
|
||||||
__init_begin = .; |
|
||||||
.text.init : { *(.text.init) } |
|
||||||
.data.init : { *(.data.init) } |
|
||||||
. = ALIGN(4096); |
|
||||||
__init_end = .; |
|
||||||
|
|
||||||
__bss_start = .; |
|
||||||
.bss : |
|
||||||
{ |
|
||||||
*(.sbss) *(.scommon) |
|
||||||
*(.dynbss) |
|
||||||
*(.bss) |
|
||||||
*(COMMON) |
|
||||||
} |
|
||||||
__bss_end = . ; |
|
||||||
PROVIDE (end = .); |
|
||||||
} |
|
||||||
@ -1,3 +0,0 @@ |
|||||||
CONFIG_PPC=y |
|
||||||
CONFIG_8xx=y |
|
||||||
CONFIG_TARGET_LWMON=y |
|
||||||
@ -1,587 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2001-2005 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* board/config.h - configuration options, board specific |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/* External logbuffer support */ |
|
||||||
#define CONFIG_LOGBUFFER |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_MPC823 1 /* This is a MPC823E CPU */ |
|
||||||
#define CONFIG_LWMON 1 /* ...on a LWMON board */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
|
||||||
|
|
||||||
/* Default Ethernet MAC address */ |
|
||||||
#define CONFIG_ETHADDR 00:11:B0:00:00:00 |
|
||||||
|
|
||||||
/* The default Ethernet MAC address can be overwritten just once */ |
|
||||||
#ifdef CONFIG_ETHADDR |
|
||||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ |
|
||||||
#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init() */ |
|
||||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ |
|
||||||
|
|
||||||
#define CONFIG_LCD 1 /* use LCD controller ... */ |
|
||||||
#define CONFIG_MPC8XX_LCD |
|
||||||
#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ |
|
||||||
|
|
||||||
#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ |
|
||||||
#define CONFIG_LCD_INFO 1 /* ... and some board info */ |
|
||||||
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ |
|
||||||
|
|
||||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
|
||||||
#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */ |
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */ |
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
|
||||||
|
|
||||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
|
||||||
|
|
||||||
/* pre-boot commands */ |
|
||||||
#define CONFIG_PREBOOT "setenv bootdelay 15" |
|
||||||
|
|
||||||
#undef CONFIG_BOOTARGS |
|
||||||
|
|
||||||
/* POST support */ |
|
||||||
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
|
||||||
CONFIG_SYS_POST_WATCHDOG | \
|
|
||||||
CONFIG_SYS_POST_RTC | \
|
|
||||||
CONFIG_SYS_POST_MEMORY | \
|
|
||||||
CONFIG_SYS_POST_CPU | \
|
|
||||||
CONFIG_SYS_POST_UART | \
|
|
||||||
CONFIG_SYS_POST_ETHER | \
|
|
||||||
CONFIG_SYS_POST_I2C | \
|
|
||||||
CONFIG_SYS_POST_SPI | \
|
|
||||||
CONFIG_SYS_POST_USB | \
|
|
||||||
CONFIG_SYS_POST_SPR | \
|
|
||||||
CONFIG_SYS_POST_SYSMON) |
|
||||||
|
|
||||||
/*
|
|
||||||
* Keyboard commands: |
|
||||||
* # = 0x28 = ENTER : enable bootmessages on LCD |
|
||||||
* 2 = 0x3A+0x3C = F1 + F3 : enable update mode |
|
||||||
* 3 = 0x3C+0x3F = F3 + F6 : enable test mode |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND "source 40040000;saveenv" |
|
||||||
|
|
||||||
/* "gatewayip=10.8.211.250\0" \ */ |
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"kernel_addr=40080000\0" \
|
|
||||||
"ramdisk_addr=40280000\0" \
|
|
||||||
"netmask=255.255.192.0\0" \
|
|
||||||
"serverip=10.8.2.101\0" \
|
|
||||||
"ipaddr=10.8.57.0\0" \
|
|
||||||
"magic_keys=#23\0" \
|
|
||||||
"key_magic#=28\0" \
|
|
||||||
"key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
|
|
||||||
"key_magic2=3A+3C\0" \
|
|
||||||
"key_cmd2=echo *** Entering Update Mode ***;" \
|
|
||||||
"if fatload ide 0:3 10000 update.scr;" \
|
|
||||||
"then source 10000;" \
|
|
||||||
"else echo *** UPDATE FAILED ***;" \
|
|
||||||
"fi\0" \
|
|
||||||
"key_magic3=3C+3F\0" \
|
|
||||||
"key_cmd3=echo *** Entering Test Mode ***;" \
|
|
||||||
"setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
|
|
||||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
|
|
||||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
||||||
"addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
|
|
||||||
"addip=setenv bootargs $bootargs " \
|
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
|
|
||||||
"panic=1\0" \
|
|
||||||
"add_wdt=setenv bootargs $bootargs $wdt_args\0" \
|
|
||||||
"add_misc=setenv bootargs $bootargs runmode\0" \
|
|
||||||
"flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
|
|
||||||
"bootm $kernel_addr\0" \
|
|
||||||
"flash_self=run ramargs addip add_wdt addfb add_misc;" \
|
|
||||||
"bootm $kernel_addr $ramdisk_addr\0" \
|
|
||||||
"net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
|
|
||||||
"run nfsargs addip add_wdt addfb;bootm\0" \
|
|
||||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
|
||||||
"load=tftp 100000 /tftpboot/u-boot.bin\0" \
|
|
||||||
"update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
|
|
||||||
"wdt_args=wdt_8xx=off\0" \
|
|
||||||
"verify=no" |
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
||||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
|
||||||
|
|
||||||
#define CONFIG_WATCHDOG 1 /* watchdog enabled */ |
|
||||||
#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 20) |
|
||||||
|
|
||||||
#undef CONFIG_STATUS_LED /* Status LED disabled */ |
|
||||||
|
|
||||||
/* enable I2C and select the hardware/software driver */ |
|
||||||
#define CONFIG_SYS_I2C |
|
||||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
|
||||||
#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ |
|
||||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE |
|
||||||
/*
|
|
||||||
* Software (bit-bang) I2C driver configuration |
|
||||||
*/ |
|
||||||
#define PB_SCL 0x00000020 /* PB 26 */ |
|
||||||
#define PB_SDA 0x00000010 /* PB 27 */ |
|
||||||
|
|
||||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
|
||||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
|
||||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
|
||||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
|
||||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
|
||||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
|
||||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
|
||||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
|
||||||
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_ASKENV |
|
||||||
#define CONFIG_CMD_BMP |
|
||||||
#define CONFIG_CMD_BSP |
|
||||||
#define CONFIG_CMD_DATE |
|
||||||
#define CONFIG_CMD_DHCP |
|
||||||
#define CONFIG_CMD_EEPROM |
|
||||||
#define CONFIG_CMD_FAT |
|
||||||
#define CONFIG_CMD_I2C |
|
||||||
#define CONFIG_CMD_IDE |
|
||||||
#define CONFIG_CMD_NFS |
|
||||||
#define CONFIG_CMD_SNTP |
|
||||||
|
|
||||||
#ifdef CONFIG_POST |
|
||||||
#define CONFIG_CMD_DIAG |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_MAC_PARTITION |
|
||||||
#define CONFIG_DOS_PARTITION |
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_SUBNETMASK |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* When the watchdog is enabled, output must be fast enough in Linux. |
|
||||||
*/ |
|
||||||
#ifdef CONFIG_WATCHDOG |
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 57600, 115200 } |
|
||||||
#endif |
|
||||||
|
|
||||||
/*----------------------------------------------------------------------*/ |
|
||||||
#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */ |
|
||||||
#undef CONFIG_MODEM_SUPPORT_DEBUG |
|
||||||
|
|
||||||
#define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */ |
|
||||||
#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ |
|
||||||
#if 0 |
|
||||||
#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ |
|
||||||
#define CONFIG_AUTOBOOT_PROMPT \ |
|
||||||
"\nEnter password - autoboot in %d sec...\n", bootdelay |
|
||||||
#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ |
|
||||||
#endif |
|
||||||
/*----------------------------------------------------------------------*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Low Level Configuration Settings |
|
||||||
* (address mappings, register initial values, etc.) |
|
||||||
* You should know what you are doing if you make changes here. |
|
||||||
*/ |
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Internal Memory Mapped Register |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration |
|
||||||
* (Set up by the startup code) |
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
|
||||||
#if defined(DEBUG) || defined(CONFIG_CMD_IDE) |
|
||||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH organization |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
|
||||||
#define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */ |
|
||||||
/* Buffer size.
|
|
||||||
We have two flash devices connected in parallel. |
|
||||||
Each device incorporates a Write Buffer of 32 bytes. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_FLASH_BUFFER_SIZE (2*32) |
|
||||||
|
|
||||||
/* Put environment in flash which is much faster to boot than using the EEPROM */ |
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_ADDR 0x40040000 /* Address of Environment Sector */ |
|
||||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */ |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* I2C/EEPROM Configuration |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_I2C_AUDIO_ADDR 0x28 /* Audio volume control */ |
|
||||||
#define CONFIG_SYS_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */ |
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ |
|
||||||
#define CONFIG_SYS_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */ |
|
||||||
#define CONFIG_SYS_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */ |
|
||||||
#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ |
|
||||||
#define CONFIG_SYS_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */ |
|
||||||
|
|
||||||
#undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */ |
|
||||||
|
|
||||||
#ifdef CONFIG_USE_FRAM /* use FRAM */ |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */ |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
|
||||||
#else /* use EEPROM */ |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ |
|
||||||
#endif /* CONFIG_USE_FRAM */ |
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
|
||||||
|
|
||||||
/* List of I2C addresses to be verified by POST */ |
|
||||||
#ifdef CONFIG_USE_FRAM |
|
||||||
#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \ |
|
||||||
CONFIG_SYS_I2C_SYSMON_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_RTC_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_POWER_A_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_POWER_B_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_KEYBD_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_PICIO_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR, \
|
|
||||||
} |
|
||||||
#else /* Use EEPROM - which show up on 8 consequtive addresses */ |
|
||||||
#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \ |
|
||||||
CONFIG_SYS_I2C_SYSMON_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_RTC_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_POWER_A_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_POWER_B_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_KEYBD_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_PICIO_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR+0, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR+1, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR+2, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR+3, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR+4, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR+5, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR+6, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR+7, \
|
|
||||||
} |
|
||||||
#endif /* CONFIG_USE_FRAM */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Cache Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SYPCR - System Protection Control 11-9 |
|
||||||
* SYPCR can only be written once after reset! |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
|
||||||
*/ |
|
||||||
#if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
|
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
|
||||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SIUMCR - SIU Module Configuration 11-6 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* PCMCIA config., multi-function pin tri-state |
|
||||||
*/ |
|
||||||
/* EARB, DBGC and DBPC are initialised by the HCW */ |
|
||||||
/* => 0x000000C0 */ |
|
||||||
#define CONFIG_SYS_SIUMCR (SIUMCR_GB5E) |
|
||||||
/*#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* TBSCR - Time Base Status and Control 11-26 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
|
||||||
* interrupt status bit, set PLL multiplication factor ! |
|
||||||
*/ |
|
||||||
/* 0x00405000 */ |
|
||||||
#define CONFIG_SYS_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */ |
|
||||||
#define CONFIG_SYS_PLPRCR \ |
|
||||||
( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
|
|
||||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
|
|
||||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
|
||||||
PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
|
|
||||||
) |
|
||||||
|
|
||||||
#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*13200000) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SCCR - System Clock and reset Control Register 15-27 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Set clock output, timebase and RTC source and divider, |
|
||||||
* power management and some other internal clocks |
|
||||||
*/ |
|
||||||
#define SCCR_MASK SCCR_EBDF11 |
|
||||||
/* 0x01800000 */ |
|
||||||
#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ |
|
||||||
SCCR_RTDIV | SCCR_RTSEL | \
|
|
||||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
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SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
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SCCR_DFBRG00 | SCCR_DFNL000 | \
|
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||||||
SCCR_DFNH000 | SCCR_DFLCD100 | \
|
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SCCR_DFALCD01) |
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||||||
|
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||||||
/*-----------------------------------------------------------------------
|
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||||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
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||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
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||||||
/* 0x00C3 => 0x0003 */ |
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||||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
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|
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||||||
|
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||||||
/*-----------------------------------------------------------------------
|
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||||||
* RCCR - RISC Controller Configuration Register 19-4 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
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||||||
#define CONFIG_SYS_RCCR 0x0000 |
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||||||
|
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||||||
/*-----------------------------------------------------------------------
|
|
||||||
* RMDS - RISC Microcode Development Support Control Register |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_RMDS 0 |
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||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* |
|
||||||
* Interrupt Levels |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
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||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PCMCIA stuff |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0x50000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
|
||||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0x54000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
|
||||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x58000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
|
||||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0x5C000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
|
||||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
|
||||||
|
|
||||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
|
||||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
|
||||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
|
||||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
|
||||||
|
|
||||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
|
||||||
|
|
||||||
/* Offset for data I/O */ |
|
||||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
|
||||||
|
|
||||||
/* Offset for normal register accesses */ |
|
||||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
|
||||||
|
|
||||||
/* Offset for alternate registers */ |
|
||||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
|
||||||
|
|
||||||
#define CONFIG_SUPPORT_VFAT /* enable VFAT support */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_DER 0 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Init Memory Controller: |
|
||||||
* |
|
||||||
* BR0/1 and OR0/1 (FLASH) - second Flash bank optional |
|
||||||
*/ |
|
||||||
|
|
||||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
|
||||||
#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */ |
|
||||||
|
|
||||||
/* used to re-map FLASH:
|
|
||||||
* restrict access enough to keep SRAM working (if any) |
|
||||||
* but not too much to meddle with FLASH accesses |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_REMAP_OR_AM 0xFF000000 /* OR addr mask */ |
|
||||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */ |
|
||||||
|
|
||||||
/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ |
|
||||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK) |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ |
|
||||||
CONFIG_SYS_OR_TIMING_FLASH) |
|
||||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ |
|
||||||
CONFIG_SYS_OR_TIMING_FLASH) |
|
||||||
/* 16 bit, bank valid */ |
|
||||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
|
||||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
|
||||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR3/OR3: SDRAM |
|
||||||
* |
|
||||||
* Multiplexed addresses, GPL5 output to GPL5_A (don't care) |
|
||||||
*/ |
|
||||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ |
|
||||||
#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */ |
|
||||||
#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ |
|
||||||
|
|
||||||
#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) |
|
||||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR5/OR5: Touch Panel |
|
||||||
* |
|
||||||
* AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 |
|
||||||
*/ |
|
||||||
#define TOUCHPNL_BASE 0x20000000 |
|
||||||
#define TOUCHPNL_OR_AM 0xFFFF8000 |
|
||||||
#define TOUCHPNL_TIMING OR_SCY_0_CLK |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ |
|
||||||
TOUCHPNL_TIMING ) |
|
||||||
#define CONFIG_SYS_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMORY_75 |
|
||||||
#undef CONFIG_SYS_MEMORY_7E |
|
||||||
#undef CONFIG_SYS_MEMORY_8E |
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory Periodic Timer Prescaler |
|
||||||
*/ |
|
||||||
|
|
||||||
/* periodic timer for refresh */ |
|
||||||
#define CONFIG_SYS_MPTPR 0x200 |
|
||||||
|
|
||||||
/*
|
|
||||||
* MAMR settings for SDRAM |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MAMR_8COL 0x80802114 |
|
||||||
#define CONFIG_SYS_MAMR_9COL 0x80904114 |
|
||||||
|
|
||||||
/*
|
|
||||||
* MAR setting for SDRAM |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MAR 0x00000088 |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
Loading…
Reference in new issue