Add Ethernet PHY for BCM Cygnus SoC
Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
With commit e3a77218a2 the MII bus is only
reset if a reset handler is registered. If there is no reset handler there
is no need to wait for a device to come out of the reset.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
The rxbd is not correctly handled in case of a frame physical error
(FPE) or frame size error (FSE). The rxbd must be cleared and
advanced in case of an error to avoid receive stall.
Signed-off-by: Daniel Inderbitzin <daniel.inderbitzin@gmail.com>
LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.
It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.
Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
This change rearranges general MAC configuration and PHY specific
configuration of MAC registers (duplex mode and speed), before this
change set bits related to PHY configuration in MAC2 and COMMAND
registers are rewritten by the following writing to the registers.
Without the change auto negotiation on boot quite often is not
completed in reasonable time:
Waiting for PHY auto negotiation to complete......... TIMEOUT !
Additionally MAC1_SOFT_RESET clear bit is removed since it is done in
preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead
added missing MCFG_RESET_MII_MGMT on device initialization.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX
MAC to some specified phy by phy id, by chance the single user of
lpc32xx_eth has CONFIG_PHY_ADDR set to 0, however other boards may
have non-zero CONFIG_PHY_ADDR value, fix it.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
According to LPC32x0 User Manual the following bits in Command
register 0x3106_0100 are defined:
Bit Symbol
2 - Unused
3 RegReset
4 TxReset
5 RxReset
Fix wrong (1-bit shifted right) COMMAND_RESETS value, which sets
an unused bit, but neglects RxReset.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tearing down an unitialized rx channel causes a pending address hole
event to be queued. When booting linux it will report this pending
as something like "Address Hole seen by USB_OTG at address 57fff584",
since u-boot did not handled this interrupt. Prevent that by not
tearing down the rx channel, when not receiving.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Support the 88E1510 PHY which is very similar to the 88E1518.
I also set the INTn output and configured the LEDs.
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
- The EEE fixup magic should also be enabled for RGMII
- Improved comments
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch refer to linux kernel commit: d8b763e1e79f
net/macb: add TX multiqueue support for gem
by: Cyrille Pitchen
1. macb driver will check the register to find how many queues support for
this chip.
2. Then as we only use queue0 for tx, so we will set up all other queues
use a dummy descriptor, which USED bit is set. So those queues are not used.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
remove unnecessary clearing of SWSM.SWSM_SMBI when obtaining the SW
semaphore. This was introduced in 951860634f
while adding i210 support and should be now resolved by releasing the
semaphore when no longer needed.
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This reverts commit 17da712024.
The i210/i211 do have the SW_FW_SYNC (0x5b5c) register and this is what should
be used when acquiring the semaphore.
I believe the issue that this patch was trying to resolve is now resolved
by properly releasing the semaphore once no longer needed.
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Once the hwsw semaphore is acquired, it must be released when access to the
hw is completed. Without this subsequent calls to acquire will timeout
obtaining the semaphore.
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Currently the serial code assumes that there is always at least one serial
port (and panics / crashes due to null pointer dereferences when there is
none).
This makes it impossible to use u-boot on boards where there is no (debug)
serial port, because e.g. all uart pins are muxed to another function.
This commit adds a CONFIG_REQUIRE_SERIAL_CONSOLE Kconfig option, which
defaults to y (preserving existing behavior), which can be set to n on
such boards to make them work.
This commit only implements this for CONFIG_DM_SERIAL=y configs, as allowing
running without a serial port for CONFIG_DM_SERIAL=n configs is non trivial,
and is not necessary at this moment.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add composite video out support.
This only gets enabled on the Mele M3 for now, since that is were it
was tested. It will be enabled on more boards after testing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for interlaced modes, this is a preparation patch for adding
composite out support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a few extra sunxi display registers and constant defines.
Also rename some existing defines (e.g. dropping _GCTRL) and make
some more generic (e.g. dropping the 2x scaling from
SUNXI_LCDC_TCON1_TIMING_V_TOTAL).
This is a preparation patch for adding composite video out support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We should only subtract 2 from the vblank time when using tcon1.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
All the #ifdef-ery in selecting the default and fallback monitor type is
becoming unyielding and makes the code hard to read, replace it with a few
helper functions.
This will also be useful with the upcoming CHIP board which has display
adapter daughterboards which should be runtime detectable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Jesurun Q5 has the musb hooked up to an usb-a receptacle, enable it
in host-only mode.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Do not add a bogus (pointing to a non existing serial port) stdout-path
alias to dts on boards without a serial port.
Note that we still define CONS_INDEX as this is used by the SPL where we do
not use DM_SERIAL and thus CONFIG_REQUIRE_SERIAL_CONSOLE is not honored.
We are getting away with this because the sun5i die actually has
an uart0, which in the A13 package is not routed to the outside,
so we are simply sending SPL bootup messages to the tx pin at the
edge of the die, and they go no further from there...
And sofar we only have one A13 board which does not have a serial
port, all others do have a serial port. This kinda makes sense since
the A13 is a much lower pincount package compared to all the other
sunxi SoCs.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Now that we have code to check the id-pin and detect usb-host adapters
plugged into the otg port that way, enable it on the tablets which I own.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
USB devices are not really designed to get the power bounced off and on
at them. Esp. USB powered harddisks do not like this.
Currently we power off the USB ports both on a "usb reset" and when
booting the kernel, causing the usb-power to bounce off and then back
on again.
This patch removes the powering off calls, fixing the undesirable power
bouncing.
Note this requires some special handling for the OTG port:
1) We must skip the external vbus check if we've already enabled our own
vbus to avoid false positives
2) If on an usb reset we no longer detect that the id-pin is grounded, turn
off vbus as that means an external vbus may be present now
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
When SPL_NAND_SUNXI option is selected in config, set some configuration
options for sunxi NAND.
This commit also introduces the configurable options in Kconfig.
Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This driver adds NAND support to SPL.
It was tested on Allwinner A20.
Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
To enable NAND flash in sunxi SPL,
pins 0-6, 8-22 and 24 on port C are configured.
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Enable the otg/drc usb controller on the Wexler TAB7200 tablet.
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add code which uses the new functions for obtaining FPGA ID from
the scan manager. This new code prints the FPGA model attached to
the SoCFPGA during boot and sets environment variable "fpgatype",
which can be used to determine the FPGA model in U-Boot scripts.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Add code to get the FPGA type for Altera's SoCFPGA family of FPGA. The code
uses the scan manager to send jtag pulses that will return the FPGA ID.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Factor out the code which sends JTAG instruction followed by data
into separate function to tidy the code up a little.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Clean up the horrible macros present in the scan_manager.h . Firstly,
the function scan_mgr_io_scan_chain_prg() is static, yet all the macros
are used only within it, thus there is no point in having them in the
header file. Moreover, the macros are just making the code much less
readable, so remove them instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce generic function for accessing the JTAG scan chains in the
SCC manager. Make use of this function throughout the SCC manager to
replace the ad-hoc writes to registers and make the code less cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Rework this function so it's clear that it is only polling for certain
bits to be cleared. Add kerneldoc. Fix it's return value to be either
0 on success and -ETIMEDOUT on error and propagate this through the
scan manager code.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Fix most of the dangling checkpatch issues, no functional change.
There are still 7 warnings, 1 checks , but those are left in place
for the sake of readability of the code.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Actually convert the sequencer code to use socfpga_sdram_misc_config
instead of the various macros. This is just an sed exercise here, no
manual coding needed.
This patch actually removes the need to include any board-specific
files in sequencer.c , so sequencer.c namespace is now no longer
poluted by QTS-generated macros.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This is another macro used to obfuscate the real code. The
T(INIT|RESET)_CNTR._VAL is always defined, so this indirection
is unnecessary. Get rid of this.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Actually convert the sequencer code to use socfpga_sdram_io_config
instead of the IO_* macros. This is just an sed excercise here, no
manual coding needed.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Actually convert the sequencer code to use socfpga_sdram_rw_mgr_config
instead of the RW_MGR_* macros. This is just an sed exercise here, no
manual coding needed.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce two wrapper functions, socfpga_get_seq_ac_init() and
socfpga_get_seq_inst_init() to avoid direct inclusion of the
sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS
generated files. This reduces namespace pollution again.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Jiandong Zheng
Jörg Krause
Daniel Inderbitzin
Vladimir Zapolskiy
Jeroen Hofstee
Clemens Gruber
Wu, Josh
Shengzhou Liu
Tim Harvey
Tom Rini
Hans de Goede
Piotr Zierhoffer
Karol Gugala
Aleksei Mamlin
Dinh Nguyen
Marek Vasut