This patch adds CFG_OHCI_USE_NPS to the common USB-OHCI driver. This
way a board just needs to define this new option to enable the "force
NoPowerSwitching mode" instead of adding new CPU/architecture defines
to the USB source itself.
This new option will be used first with the new AMCC 460EX Canyonlands
board port, which will be posted in a few days.
This patch also fixes a small compilation problem when DEBUG is enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
When rtl_recv() of rtl8169 is called, OWNbit of status register
is not enable occasionally.
rtl_recv() doesn't work normally when the driver doesn't do
appropriate processing.
This patch fix this problem.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
allow u-boot to recover (and, e.g., switch to another interface) in the
case where a PHY does not report autonegotiation is complete within its
two second timeout value.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Fix a typo in qe_upload_firmware() that prevented uploading firmware on
systems with more than one RISC core.
Signed-off-by: Timur Tabi <timur@freescale.com>
erratum 5.6 states the autoneg completion bit is functional only if the
autoneg bit is asserted.
This fixes any secondarily-issued networking commands on non-gigabit
links on the mpc8360 mds board.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
When the LM75 temperature sensor measures a temperature below 0 C, the
current driver does not perform sign extension, so the result returned is
256 C too high. This patch fixes the problem.
Signed-off-by: Larry Johnson <lrj@acm.org>
Do not use uninitialized cmd_reset; issue both AMD and Intel reset
commands instead
From a short test, it looks like AMD-style flash roms treat *any* unknown
command write as a reset, at least when in CFI Query mode, so issuing the
Intel reset command to AMD-style flashs seems safe (from the small sample I
have), plus the 3-cycle magic sequence should kick the state machine into
the right state even without a reset command. Since the AMD-style flashs
require the unlock sequence for real operation, I chose to try the AMD reset
command first, so that Intel flashs do no see an invalid command prior to
the CFI query.
I have tested the patch on AM29LV320-style flashs from Fujitsu and Macronix,
plus Intel StrataFlash.
Signed-off-by: Michael Schwingen <michael@schwingen.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch tries to get rid of some assembler warnings about
changed .got2 section type while compiling x86 bios emulator
code.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This patch extends PCI device id table of the
radeon driver so that the driver will also support
Radeon Mobility 9200 (M9+) based boards.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Move the flat device tree setup for QE related devices into
a common file shared between 83xx & 85xx platforms that have QE's.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move the flat device tree setup for QE related devices into
a common file shared between 83xx & 85xx platforms that have QE's.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
According to the OMAP5912 Serial Interfaces Reference Guide (see
http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the
FIFO_EN enable bit in the FIFO Control Register (FCR) can only be
changed when the baud clock is not running, i. e. when both DLL and
DLH are set to 0.
Thus make sure that DLL and DLH are 0 when writing the FCR.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This driver should only compile if CONFIG_MPC8XXX_SPI is set
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch adds support for the SPI controller found on Freescale PowerPC
processors such as the MCP834x family. Additionally, a new config option,
CONFIG_HARD_SPI, is added for general purpose SPI controller use.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch fixed wrong SH7720 CPU macro and changed macro that
calculated value of SCBRR register.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move the initialization of the LAWs into C code and provide an API
to allow modification of LAWs after init.
Board code is responsible to provide a law_table and num_law_entries.
We should be able to use the same code on 86xx as well.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
rx_status on the memory is basically in LE, but needs to be handled in CPU
endian. le32_to_cpu() takes up this mission. Even if on the sane hardware,
it'll work fine.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Cc: Masami Komiya <mkomiya@sonare.it>
Cc: Lucas Jin <lucasjin@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Current driver is meant for cache coherent systems. This patch adds
flush_cache() routines to support cache non-coherent systems.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Cc: Masami Komiya <mkomiya@sonare.it>
Cc: Lucas Jin <lucasjin@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
"to = (currticks() + RTL_TIMEOUT)" has possibilities to wrap around. If it
does, the condition "(currticks() < to)" becomes invalid and immediately
leads to tx timeout error. This patch introduces the fine-graded udely(10)
loops to ease the impact of wrapping around.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Cc: Masami Komiya <mkomiya@sonare.it>
Cc: Lucas Jin <lucasjin@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Add the support of RealTek RTL8211B PHY, the RTL8211B
PHY only supports RGMII and MII mode.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
PHY less board prints out lots of "read wrong ...":
read wrong value : mii_id 3,mii_reg 2, base e0102320
read wrong value : mii_id 3,mii_reg 3, base e0102320
UEC: PHY is Generic MII (ffffffff)
read wrong value : mii_id 3,mii_reg 4, base e0102320
read wrong value : mii_id 3,mii_reg 0, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 5, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 5, base e0102320
FSL UEC0: Full Duplex
FSL UEC0: Speed 100BT
FSL UEC0: Link is up
Using FSL UEC0 device
Make this printout depend on UEC_VERBOSE_DEBUG and
remove its definition in uec_phy.c
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
actually polling for PHY autonegotiation to finish enables us to remove the
5 second boot prompt latency present on QE based boards.
call to qe_set_mii_clk_src in init_phy, and mv call to init_phy from
uec_initialize to uec_init by Joakim Tjernlund; autonegotiation wait
code shamelessly stolen from tsec driver.
also rm unused CONFIG_RMII_MODE code.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The current TSEC driver limits MDIO access to the devices that have been configured as attached
to a TSEC MAC. This patch allows access to any PHY device on the MDIO bus through the 'mii' commands.
Signed-off-by: Michael Firth <michael.firth@bt.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch extends the number of supported UECs to 4. Note that the
problem of QE thread resources exhaustion is resolved by setting the
correct number of QE threads according to Ethernet type (GBE or FE).
Signed-off-by: David Saada <david.saada@ecitele.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
SH7710/SH7712 of SH3 CPU are supported.
SH771X is called SH-Ether, and has the Ether controller in CPU.
The driver of Ether is not included in this patch.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Wolfgang Denk
Tor Krill
Stefan Roese
Nobuhiro Iwamatsu
Kim Phillips
Timur Tabi
Larry Johnson
Jean-Christophe PLAGNIOL-VILLARD
Michael Schwingen
Anatolij Gustschin
Vlad Lungu
Stelian Pop
Stelian Pop
Kumar Gala
Mike Frysinger
Ben Warren
Becky Bruce
TsiChungLiew
Shinya Kuribayashi
Dave Liu
Joakim Tjernlund
michael.firth@bt.com
Anton Vorontsov
Kyungmin Park
David Saada
Yoshihiro Shimoda