To make this driver easier to be reused, dual-license DDR driver.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Simon Glass <sjg@chromium.org>
CC: Tom Rini <trini@konsulko.com>
CC: Heinrich Schuchardt <xypron.glpk@gmx.de>
CC: Thomas Schaefer <thomas.schaefer@kontron.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Robert P. J. Day <rpjday@crashcourse.ca>
CC: Alexander Merkle <alexander.merkle@lauterbach.com>
CC: Joakim Tjernlund <joakim.tjernlund@transmode.se>
CC: Curt Brune <curt@cumulusnetworks.com>
CC: Valentin Longchamp <valentin.longchamp@keymile.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
CC: Ira W. Snyder <iws@ovro.caltech.edu>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Kyle Moffett <Kyle.D.Moffett@boeing.com>
CC: Sebastien Carlier <sebastien.carlier@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Peter Tyser <ptyser@xes-inc.com>
CC: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: Peter Tyser <ptyser@xes-inc.com>
CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.
Signed-off-by: York Sun <york.sun@nxp.com>
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.
Signed-off-by: Tom Rini <trini@konsulko.com>
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Signed-off-by: York Sun <yorksun@freescale.com>
By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.
Signed-off-by: York Sun <yorksun@freescale.com>
In case SPD address changes between board revisions, updating SPD
address can be called from board file.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.
Signed-off-by: York Sun <yorksun@freescale.com>
Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
Signed-off-by: York Sun <yorksun@freescale.com>
U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.
Signed-off-by: York Sun <yorksun@freescale.com>
Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.
Signed-off-by: York Sun <yorksun@freescale.com>
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl
Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
This patch adds the ability for the FSL DDR interactive debugger to
automatically run the sequence of commands stored in the ddr_interactive
environment variable. Commands are separated using ';'.
ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Interactive DDR debugging provides a user interface to view and modify SPD,
DIMM parameters, board options and DDR controller registers before DDR is
initialized. With this feature, developers can fine-tune DDR for board
bringup and other debugging without frequently having to reprogram the flash.
To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
file and set an environment variable to activate it. Syntax:
setenv ddr_interactive on
After reset, U-boot prompts before initializing DDR controllers
FSL DDR>
The available commands are
print print SPD and intermediate computed data
reset reboot machine
recompute reload SPD and options to default and recompute regs
edit modify spd, parameter, or option
compute recompute registers from current next_step to end
next_step shows current next_step
help this message
go program the memory controller and continue with u-boot
The first command should be "compute", which reads data from DIMM SPDs and
board options, performs the calculation then stops before setting DDR
controller. A user can use "print" and "edit" commands to view and modify
anything. "Go" picks up from current step with any modification and
compltes the calculation then enables the DDR controller to continue u-boot.
"Recompute" does it over from fresh reading.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We used to have fixed parameters for soldered DDR chips. This patch
introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing
data from DDR chip datasheet, implemneted in board-specific files or header
files.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
When DDR data rate is higher than 1200MT/s or controller interleaving is
enabled, additional cycle for write-to-read turnaround is needed to satisfy
dynamic ODT timing.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.
Also check dimm size and rank size for memory controller interleaving
Signed-off-by: York Sun <yorksun@freescale.com>
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
The ddr code computes most things as 64-bit quantities and had some places
in the middle that it was using phy_addr_t and phys_size_t.
Instead we use unsigned long long through out and only at the last stage of
setting the LAWs and reporting the amount of memory to the board code do we
truncate down to what we can cover via phys_size_t.
This has the added benefit that the DDR controller itself is always setup
the same way regardless of how much memory we have. Its only the LAW
setup that limits what is visible to the system.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.
* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
The main purpose of this rewrite it to be able to share the same
initialization code on all FSL PowerPC products that have DDR
controllers. (83xx, 85xx, 86xx).
The code is broken up into the following steps:
GET_SPD
COMPUTE_DIMM_PARMS
COMPUTE_COMMON_PARMS
GATHER_OPTS
ASSIGN_ADDRESSES
COMPUTE_REGS
PROGRAM_REGS
This allows us to share more code an easily allow for board specific code
overrides.
Additionally this code base adds support for >4G of DDR and provides a
foundation for supporting interleaving on processors with more than one
controller.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Tom Rini
York Sun
Shengzhou Liu
York Sun
York Sun
Priyanka Jain
James Yang
Kumar Gala
Haiying Wang
Stefan Roese
Peter Tyser
Jean-Christophe PLAGNIOL-VILLARD