The RX Control/Status register has bits that we want to preserve, so don't
just write out a single bit. Preserve the others bits in the process.
The original code posted to the u-boot list had this behavior, but looks
like it was lost somewhere along the way to merging.
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
The multipoint handling under MUSB is optional, and some parts (like the
Blackfin processor) do not implement support for it.
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
The dynamic FIFO handling under MUSB is optional, and some parts (like
the Blackfin processor) do not implement support for it.
Due to this, the FIFO reading/writing steps need special handling, so
mark the common versions weak so drivers can override.
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Adding USB configuration. Default is set for USB MSC host.
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
Added DA8xx GPIO base addresses in gpio_defs.h and pointers
to different BANKs which can be used to program GPIOs.
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
USB0_DRVVBUS pinmux configuration is required for USB functinality
in uboot.
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
Add support to configure bus parking mode and master in bus arbitration
configuration (ACR). Add this for the kmeter1 port:
Configure bus arbiter with recommended values from Freescale
to improve bus latency/throughput for application with
intensive QuiccEngine activity.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Remove PCI reset, if there is a monarch PMC module.
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
convert clrbits_be32 + setbits_be32 to clrsetbits_be32, use out_be32 to set gcr.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The caddy2 is a variant of the already supported vme8349. So we just
add the differences to this board port. To better support those two
boards we switched from fixed SDRAM configuration to usage of
spd_sdram(). This is done by providing a board specific SPD EEPROM
routine with different values for both boards.
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
changed to use mkconfig -t option instead, plus misc codingstyle fixes.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The memory controller could already be enabled, when spd_sdram() is
called. This could be the case for example, when the SDRAM is initialized
by the JTAG debugger.
The "sync" after the register access via the accessor function is
still needed, because the macro uses the sync before the real write
is done. So until not all accesses are converted to using accessor
functions, this sync still needs to be made "manually" here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd.eu>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The core support for NAND booting is there already, so this patch
is pretty straightforward.
There is one trick though: top level Makefile expects nand_spl to
be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code
from mpc8313erdb boards, and so to not duplicate the code we just
symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
o silence make during ln echo
o update documentation
o and avoid:
$ ./MAKEALL MPC8315ERDB_NAND
Configuring for MPC8315ERDB board...
sdram.o: In function `fixed_sdram':
/home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay'
by renaming udelay -> __udelay in the spirit of commit
3eb90bad65 "Generic udelay() with watchdog
support".
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch fixes the compile error while trying to
compile for omap3evm.
env_onenand.c: In function 'env_relocate_spec':
env_onenand.c:70: error: 'CONFIG_ENV_ADDR_FLEX' undeclared
(first use in this function)
env_onenand.c:70: error: (Each undeclared identifier is re
ported only once
env_onenand.c:70: error: for each function it appears in.)
env_onenand.c: In function 'saveenv':
env_onenand.c:106: error: 'CONFIG_ENV_ADDR_FLEX' undeclare
d (first use in this function)
env_onenand.c:107: error: 'CONFIG_ENV_SIZE_FLEX' undeclare
d (first use in this function)
Signed-off-by: Sanjeev Premi <premi@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
Introduces various optimisations that approximately triple the
read data rate from NAND when run on da830evm.
Most of these optimisations depend on the endianess of the machine
and most of them are very similar to optimisations already present
in the Linux Kernel.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
add the override for write leveling sampling and
start time according to specific board.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
We are setting the mode register MR0[A12]='1'
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor
Family Reference Manual, Rev. 0" document, which describes all eSDHC
pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL
backwards so we report the wrong frequency.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We already map the page cache-inhibited. There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Various SoC errata are specific to a given revision of silicon. This
patch gives us a simple macro to use when doing such tests.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We need to add the readback to bootpage translation LAW
to make it effect.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Rather than hard coding which TLB entry the FLASH is mapped with we can
use find_tlb_idx to determine the entry.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Now that we dynamically determine TLB CAM entries to use we dont need
CONFIG_SYS_DDR_TLB_START anymore.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Now that we track which TLB CAM entries are used we can allocate
entries on the fly. Change the SPD DDR TLB setup code to assume
we use at most 8 TLBs (or the number free, which ever is fewer).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code. For example the SPD
DDR code today hard codes which TLB entries it uses. We can now make
that pick entries that are free.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We can use fsl_setup_hose to determine if we are a agent/end-point or
a host. Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We can use fsl_setup_hose to determine if we are a agent/end-point or
a host. Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We can use fsl_setup_hose to determine if we are a agent/end-point or
a host. Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We can use fsl_setup_hose to determine if we are a agent/end-point or
a host. Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
1. Modified the tsec_mdio structure to include the new regs
2. Modified the MDIO_BASE_ADDR so that it will handle both
older version and new version of etsec.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Moved the mdio regs out of the tsec structure,and
provided different offsets for tsec base and mdio
base so that provision for etsec2.0 can be provided.
This patch helps in providing the support for etsec2.0
In etsec2.0, the MDIO register space and the etsec reg
space are different.
Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into
platform specific files.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The FSL_CORENET platforms use a completely different means to determine
which PCIe port is enabled as well as if its a host or agent/end-point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Added immap definition for SERDES registers on p4080, the USB offset
(since it was missing) and a GPL header.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.
We use the following equation to set the various stash-ids:
32 + coreID*2 + 0(L1) or 1(L2)
The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Bryan Wu
Mike Frysinger
Ajay Kumar Gupta
Heiko Schocher
Reinhard Arlt
Stefan Roese
Anton Vorontsov
Sanjeev Premi
Nick Thompson
Tom Rix
Becky Bruce
Dave Liu
Kumar Gala
Li Yang
Mingkai Hu
Sandeep Gopalpet