We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the
same place across all versions. This change adds two more banks, for up to
96 GPIOS.
BUT:
- Not all chipsets have the same number of GPIOs
- Not all chipsets have the same number of GPIO banks
- Not all chipsets put the additional banks at the same offset from GPIOBASE
- There so many chipset variants that it's pretty much impossible to support
them all, or even keep track of the new ones.
So, although this adds suppport for the additional banks that seem to work
for the particular variants of CougarPoint Mobile chipsets that we've tried,
there's no chance it will support everything Intel produces. Good luck.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Since the top-level README file refers the reader to the CHANGELOG,
it's worth mentioning how to generate it.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Current "led" help and usage info has redundancy and extraneous
newlines, tweak it to be consistent with other commands.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Use the printf command to convert the number in any valid format into
the expected decimal format. The resulting errors should be printed to
stderr.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
In order to calculate the capability, we use the below expression to check:
((dev_desc->lba * dev_desc->blksz)>0L)
If the capability is greater than 4GB (e.g. 8GB = 8 * 1024 * 104 * 1024),
the result will overflow, the low 32bit may be zero.
Therefore, change to check each variable to fix this potential issue.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Updated code taken from latest lzma sdk release 9.20 at
http://downloads.sourceforge.net/sevenzip/lzma920.tar.bz2
This generates quite a lot of checkpatch warnings, but I guess we
need to keep the code style as is to avoid a massive job each time we
update this.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
--continue will allow you to <ctrl-c> the MAKEALL and pick up where
you left off.
--rebuild-errors will allow you to rebuild only those boards which
had trouble on the last run of MAKEALL, allowing you to quickly test
a simple fix on just those boards.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
When building in parallel, make sure that we look up the children
based on the the actual process group id instead of just assuming
that the MAKEALL pid is the process group id.
Also ensure that logs from incomplete builds are deleted in the
process.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This patch fixes an issue with overlapping PCI regions
on boards with more than 64MB RAM.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This new make target "u-boot-img.bin" consists of the U-Boot
SPL image with the real, full-blown U-Boot image directly
attached to it. The full-blown U-Boot image has the mkimage
header included, with its load-address and entry-point.
This will be used by the upcoming a3m071 MPC5200 board port.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enabled boards using the SPL framework to set
an entry point in the U-Boot mkimage image "u-boot.img".
Until now the entry point in the header has been set to 0.
By setting CONFIG_SYS_UBOOT_START in the board header, boards
can override this default location.
This will be used by the upcoming a3m071 MPC5200 board port.
Signed-off-by: Stefan Roese <sr@denx.de>
With this patch, getenv_f() can be included easily into the SPL
binary. With this, SPL boards can now use getenv_f() to read
environment variables (e.g. to detect if the OS or U-Boot shall
be executed).
In the approach this is done for env stored in NOR flash, as this
will be used by an upcoming MPC5200 board port.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables the SPL framework to be used on powerpc platforms
and not only ARM.
timer_init() does not exist on PPC systems. The timer (decrementer) is
initialized and enabled in interrupt_init() here. And currently
interrupt_init() is called after relocation to SDRAM. Since the only
powerpc SPL implementation (a3m071) doesn't need a timer, let's remove
this timer_init() call for PPC systems.
Signed-off-by: Stefan Roese <sr@denx.de>
By extracting these defines into a header, they can be re-used by other
C sources as well. This will be done by the SPL framework OS boot
support.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch prevents u-boot from "spamming" random progress codes on
a port 80 "post card".
The previous version of this patch just removed the delays in the "slow"
IO functions, as they do not need to be slow, however, this patch is
less intrusive.
It uses another unused port that is often used by BIOSes (and the Linux
Kernel) for small delay timing purposes.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The i386 version of io.h depends on the phys_addr_t type which is defined in
types.h. It wasn't including that explicitly, and was working presumably
because the other files including it had already included types.h themselves
directly or indirectly. This change fixes that.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The microsecond timer is not currently implemented, but add a dummy
implementation for now.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This function provides an opportunity for some last minute cleanup and
reconfiguration before control is handed over to Linux. It's possible this
may need to do something in the future, but for now it's left empty. It's set
up as a weak symbol so it can be overridden if necessary on a case by case
basis.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The device tree now includes the necessary console configuration
information.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This change adds a pointer to the global data structure in x86 to point to
the device tree. This mirrors an identical pointer in ARM.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
We don't want this for coreboot, so provide a way of compiling it out.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This command is useful to allow to observe messages generated by
coreboot and u-boot until present. In particular it is handy when
u-boot is instrumented to fall through into console mode on startup
errors.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch builds upon the recently introduced CBMEM console
feature of coreboot.
CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.
Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.
>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:
vvvvvvvvvvvvvvvvv
SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^
Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for decoding tags for GPIOs, compile/build info, cbmem and
other features.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
sysinfo.c only contains the lib_sysinfo data structure which
is used/filled by tables.c. This split was introduced by importing
code from libpayload originally, but to keep the code simple, add
the single line of actual code to tables.c
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
When __BYTEORDER_HAS_U64__ is not defined, we got warning following:
-----
/tmp/include/linux/byteorder/little_endian.h: In function ‘__cpu_to_be64p’:
/tmp/include/linux/byteorder/little_endian.h:71:2: warning: implicit declaration of function ‘__swab64p’
[-Wimplicit-function-declaration]
-----
Usually, __arch__swab64* required for __fswab64, __swab64p and __swab64s
is defined. Therefore, __BYTEORDER_HAS_U64__ is unnecessary.
This removes __BYTEORDER_HAS_U64__.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Kim Phillips <kim.phillips@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
On kzm9g board (rmobile SoC), autoboot fails if serial console cable is not
connected. When serial cable is not connected, serial error occurs and
some garbage comes in data register.
sh_serial_tstc() in serial_sh.c does not check error status and misunderstand
there is some input data. It is the reason that autoboot fails.
This patch adds checking error status in sh_serial_tstc().
This patch is based on v2013.01-rc1 tag of u-boot master git.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The function should set BL bit, but it should not clear other flags.
So, the patch uses set_bl_bit() instead of a local asm code.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
We need an extra condition here in case we want to use fdt without the
silent console/cmdline editing/post options. It is easier to just remove
the #ifdef.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.
Signed-off-by: Simon Glass <sjg@chromium.org>
A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.
On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly. This fixes the
EHCI PCI driver initialization on Stumpy.
This was tested as follows:
Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This prevents the preprocessor from complaining when processing
variadic macros
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some
point.
It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
Bill Richardson
Simon Glass
Luka Perkov
Robert P. J. Day
Joe Hershberger
Jerry Huang
Stefan Reinauer
Matthias Fuchs
Stefan Roese
Tom Rini
Gabe Black
Vadim Bendebury
Nobuhiro Iwamatsu
Tetsuyuki Kobayashi
Yoshihiro Shimoda