Add ddr3 commands:
test <start_addr in hex> <end_addr in hex> - test DDR from start\n
address to end address\n
ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n
compare DDR data of (size) bytes from start address to end
address\n
ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n
in DDR data at <addr>, the command will read a 32-bit data\n
from <addr>, and write (data ^ bit_err) back to <addr>\n
Delete CONFIG_MAX_UBOOT_MEM_SIZE, as it was supposed to be used
for ddr3 commands and for now it's not needed any more.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.
By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.
An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The EDMA3 controller’s primary purpose is to service data transfers
that you program between two memory-mapped slave endpoints on the device.
Typical usage includes, but is not limited to the following:
- Servicing software-driven paging transfers (e.g., transfers from external
memory, such as SDRAM to internal device memory, such as DSP L2 SRAM)
- Servicing event-driven peripherals, such as a serial port
- Performing sorting or sub-frame extraction of various data structures
- Offloading data transfers from the main device DSP(s)
- See the device-specific data manual for specific peripherals that are
accessible via the EDMA3 controller
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The new Marvel PHY (88E1514) used on K2L/K2E EVM requires longer time
to auto negotiate with SoC's SGMII port.
It can take about 3 sec to up the PHY after reset, so add code to
expose sgmii auto negotiation waiting process.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The Keystone2 Edison SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2E SoCs.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Keystone2 Edison SoC uses the same keystone SerDes driver.
This patch adds support for K2E SoCs.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The phy framework has function to get link, so use it
instead of own implementation.
There is no reason to check SGMII link while sending each
packet, phy link is enough. Check SGMII link only while
ethernet open.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
As MDIO bus has been added we can register PHYs with it.
After registration, the PHY driver will be probed according to the
hardware on board.
Startup PHY at the ethernet open.
Use phy_startup() instead of keystone_get_link_status() when eth open,
as it verifies PHY link inside and SGMII link is checked before.
For K2HK evm PHY configuration at init was absent, so don't enable
phy config at init for k2hk evm.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Currently MDIO framework is not used to configure Ethernet PHY.
As result some of already implemented functions are duplicated.
So register MDIO bus in order to use it. On that stage it's just
registered, it'll be used as we start to use PHY framework.
Use mdio bus read/write/reset functions in the driver.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Don't use mdio_enable twice while eth open. Also rename it to
keystone2_mdio_reset as more appropriate name.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
In case when several Ethernet ports are supported it's
convenient to see the number of phy that is not found.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The cmu, comlane, lane configuration mechanism are similar for sub
systems as well such as PCI or sRIO, but they have different values
based on input clock and output bus rate. According to this compact
driver to simplify adding different configuration settings based
on clock and rate.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
SerDes driver is used by other sub systems like PCI, sRIO etc.
So modify it to be more general. The SerDes driver provides common
API's that can also be extended for other peripherals SerDes
configurations.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Enhance the driver to use cmu/comlane/lane specific configurations
instead of 1 big array of configuration.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patch split the Keystone II SGMII SerDes related code from
Ethernet driver and create a separate SGMII SerDes driver.
The SerDes driver can be used by others keystone subsystems
like PCI, sRIO, so move it to driver/soc/keystone directory.
Add soc specific drivers directory like in the Linux kernel.
It is going to be used by keysotone soc specific drivers.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Remove unused tx_send_loop variable.
Removes duplicated get_link_status() call from the
keystone2_eth_send_packet().
The emac_gigabit_enable() is called at opening Ethernet and there is no
need to enable it on sending each packet. So remove that call
from keystone2_eth_send_packet() as well.
The calling of power/clock up functions are mostly the responsibility
of SoC/board code, so move these functions to appropriate place.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
With MAC_PHY sgmii configuration, u-boot checks PHY link status before
sending each packet. Increasing MDIO frequency increases overall tftp
speed. We set it to maximum 2.5MHz.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The header file for the driver should be in correct place.
So move it to "arch/arm/include/asm/ti-common/keystone_net.h"
and correct driver's external dependencies. At the same time
align and correct some definitions.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Currently the network driver is used only by k2hk evm board.
The k2hk SoC contains NETCP v1.0, but Keystone2 SoCs, like k2e
contain NETCP v1.5. So driver should be able to work with such kind
of NETCP. This commit adds this opportunity. The main difference in
masks and some registers, the logic is the same, so only definitions
should be changed. To differentiate between versions add KS2_NETCP_V1_0
and KS2_NETCP_V1_5. Also remove unused and no more needed defines.
The port number is specific for each board so move this parameter to
configuration.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patch removes K2HK SOC specifc emac_regs structure, it uses
soc specific register offset to keep the network driver common across
all the Keystone II EVMs.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Currently keystone has misc_init_r where all DSPS are turned off
by default. So enable this function.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patches enables the On-chip Shared Ram clock domain for K2L SoC.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The initialization of PLLs is a part of board specific code, so
move it appropriate places.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patch adds Keystone II Lamar (K2L) SoC specific definitions
to support MSMC cache coherency.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patch adds clock definitions and commands to support Keystone II
K2L SOC.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patch adds hardware definitions specific to Keystone II
Lamar (K2L) SoC.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The usage description of commands refers to headers of sources,
that is not correct. This patch is intended to fix it.
Also generalize code in order to reduce SoC dependent #ifdefs.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Add support of usb xhci. xHCI controls all USB speeds of the Host
mode, that is, the SS through the SS PHY, as well as the HS, FS, and
LS through the USB2 PHY. xHCI replaces and supersedes all previous
host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not
backwards compatible with any of them. The USB3SS’s USB Controller is
fully compliant with xHC.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The keystone_nav driver is general driver intended to be used for
working with queue manager and pktdma for different IPs like NETCP,
AIF, FFTC, etc. So the it's API shouldn't be named like it works only
with one of them, it should be general names. The names with prefix
like netcp_* rather do for drivers/net/keystone_net.c driver. So it's
good to generalize this driver to be used for different IP's and
delete confusion with real NETCP driver.
The current netcp_* functions of keystone navigator can be used for
other settings of pktdma, not only for NETCP. The API of this driver
is used by the keystone_net driver to work with NETCP, so net driver
also should be corrected. For convenience collect pkdma
configurations in drivers/dma/keystone_nav_cfg.c.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The keystone_nav is used by drivers/net/keystone_net.c driver to
send and receive packets, but currently it's placed at keystone
arch sources. So it should be in the drivers directory also.
It's separate driver that can be used for sending and receiving
pktdma packets by others drivers also.
This patch just move this driver to appropriate directory and
doesn't add any functional changes.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Use definitions in netcp_pktdma instead direct addresses.
The definitions can be set specifically for SoC, so there
is no reason to check SoC type while initialization.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Use definitions in qm_config. The definitions can be set specifically
for SoC, so there is no reason to check SoC type while initialization.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Add target to build it automatically upon "make" / MAKEALL. This can/should
be set by board / cpu specific headers if a special U-Boot image is
required for this SoC / board.
E.g. used by Marvell Armada XP to automatically build the u-boot.kwb
target.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
This patch integrates the Barebox version of this kwbimage.c file into
U-Boot. As this version supports the image version 1 type for the
Armada XP / 370 SoCs.
It was easier to integrate the existing and known to be working Barebox
source than to update the current U-Boot version to support this
v1 image header format. Now all Marvell MVEBU SoCs are supported:
Image type 0: Kirkwood & Dove
Image type 1: Armada 370 & Armada XP
Please note that the current v1 support has this restuction (same as
has Barebox version):
Not implemented: support for the register headers and secure headers
in v1 images
Tested on Marvell DB-78460-BP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
The barebox version of the kwboot tool has evolved a bit. To support
Armada XP and Dove. Additionally a few minor fixes have been applied.
So lets sync with the latest barebox version.
Please note that the main difference between both versions now is, that
the U-Boot version still supports the -p option, to dynamically patch
an image for UART boot mode. I didn't test it now though.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
The maxBCM board is equipped with the Marvell Armada-XP MV78460 SoC. It
integrates an SPI NOR flash and an Marvell 88E6185 switch.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds basic support for the Marvell DB-MV784MP-GP evaulation
board. This is the first board that uses the recently created
Armada XP 78460 SoC support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
This basic support for the Marvell Armada XP is base on the existing kirkwood
support. Which has been generatized by moving some common files into
common marvell locations.
This is in preparation for the upcoming Armada XP MV78460 support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
To support the Armada XP SoC, we just need to include the correct header.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
The Marvell MV78460 eval board DB-78460-BP seems to need a longer
PHY autonegotiation timeout than the "standard" 4 seconds. So lets
make this timeout configurable. If not defined in the board config
header the original 4000ms is used.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
This patch adds support for the NETA ethernet controller which is integrated
in the Marvell Armada XP SoC's. This port is based on the Linux driver which
has been stripped of the in U-Boot unused portions.
Tested on the Marvell MV78460 eval board db-78460-bp.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Additionally the SDRAM address decoding register address is not hard coded
in the C code any more. A define is introduced for this base address.
This makes is possible to use those gpio functions from other MVEBU SoC's
as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Stefan Herbrechtsmeier
Hao Zhang
Vitaly Andrianov
Khoronzhuk, Ivan
WingMan Kwok
Stefan Roese