When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow registers
with the corresponding status registers here during the boot.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
A generic is_dra7xx cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Based on the definitive guide to EMIF configuration[1] certain registers
that we have been modifying (and are documented registers) should be
left in their reset values rather than modified. This has been tested
on AM335x GP EVM and Beaglebone White.
[1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Javier Martinez Canillas <javier@dowhile0.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Matt Porter <matt.porter@linaro.org>
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Enable Atmel sama5d3xek boart spl boot support, which can load u-boot
from SD card with FAT file system.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The MPDDRC supports different type of SDRAM
This patch add ddr2 initialization function
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The offset of MULA field in PLLA register in sama5d3 is 18,
and the length only 7 bits.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The SAMA5D36 chip is the superset product of SAMA5D3x family.
For detail information please refer to:
http://www.atmel.com/Microsite/sama5d3/default.aspx
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)
We don't need to provide Linux copatibility any more.
This commit deletes include/linux/config.h
and fixes source files not to include this.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Roger Meier <r.meier@siemens.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add usb host support for at91sam9n12ek board.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The change from 0x64656465 to 0x64646464 is to remove the weak pull
enabled on DQS, nDQS lines. This pulls the differential signals in the
same direction which is not intended. So disabling the weak pulls improves
signal integrity.
On the uEVM there are 4 DDR3 devices. The VREF for 2 of the devices is powered by
the OMAP's VREF_CA_OUT pins. The VREF on the other 2 devices is powered by the OMAP's
VREF_DQ_OUT pins. So the net effect here is that only half of the DDR3 devices were being
supplied a VREF! This was clearly a mistake. The second change improves the robustness of
the interface and was specifically seen to cure corruption observed at high temperatures
on some boards.
With the above two changes better memory stability was observed with extended
temperature ranges around 100C.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
UART booting is supported on this SoC, but via UART3 rather than UART1.
Because of this we must change the board to use UART3 for all console
access (only one UART is exposed on this board and a slight HW mod is
required to switch UARTs).
Signed-off-by: Minal Shah <minal.shah@ti.com>
[trini: Make apply to mainline, reword commit]
Signed-off-by: Tom Rini <trini@ti.com>
This removes the PAD_CTL_DSE_120ohm as done for i.MX6Q's IPU1_DI0_PIN4
pin definition and makes it aligned with 3.0.35-4.1.0 and 3.12
mainline kernel.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support booting via eMMC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Add the support for the am437x xhci usb host.
The xHCI host on AM437 is connected to a usb2 phy so need to
add support to enable those clocks.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Add the support for the dra7xx xhci usb host.
dra7xx does not contain an EHCI controller so the headers
can be removed from the board file.
The xHCI host on dra7xx is connected to a usb2 phy so need to
add support to enable those clocks.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.
New API allows selective initialization of USB controllers whenever needed.
Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Add the OMAP file for the xHCI Host controller
This code will initilialize the proper components within the
OMAP5 to enable the xHCI host controller.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Adding methods to turn on/off power to USB3.0 type PHY
as and when required by the controller.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
This adds driver layer for xHCI controller in Samsung's
exynos5 soc. This interacts with xHCI host controller stack.
Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
In case the MX23/MX28 is switched into JTAG mode via the BootMode select
switches, the BootROM bypasses the CPU core registers initialization.
This in turn means that the Stack Pointer (SP) register is not set as
it is in every other mode of operation, but instead is only zeroed out.
To prevent U-Boot SPL from crashing in this obscure JTAG mode, configure
the SP to point at the CONFIG_SYS_INIT_SP_ADDR if the SP is zeroed out.
Note that in case the SP is already configured, we must preserve that exact
SP value and must not modify it. This is important since in every other mode
but the JTAG mode, the SPL returns into the BootROM and BootROM in turn loads
U-Boot itself. If the SP were to be corrupted, the BootROM won't be able to
continue it's operation after returned from SPL and the system would crash.
Finally, add the JTAG mode switch identifier, so it's not recognised as
Unknown mode.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Add a MAC address create based on the OMAP die ID registers.
Then poplulate the ethaddr enviroment variable so that the device
tree alias can be updated prior to boot.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Since SPI register access is so expensive, it is worth transferring data
a word at a time if we can. This complicates the driver unfortunately.
Use the byte-swapping feature to avoid having to convert to/from big
endian in software.
This change increases speed from about 2MB/s to about 4.5MB/s.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
We can run the DDR at 400MHz, so update the timings for that purpose.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).
The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.
In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.
The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.
The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.
The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.
We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.
Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
(GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
(GICD_IGROUPRn = 0xFFFFFFFF)
The core specific GIC setup is then done in the assembly routine.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.
Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
(GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
(GICC_PMR = 0xFF)
Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.
The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.
After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
This patch adds the pad to i.MX6DQ and changes the i.MX6DLS
declaration to match the Linux kernel declaration.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Viktar Palstsiuk
Michael Trimarchi
Roger Quadros
SRICHARAN R
Tom Rini
Ilya Ledvich
Chin Liang See
Heiko Schocher
Bo Shen
Wu, Josh
Andreas Bießmann
Masahiro Yamada
Roger Meier
Rob Herring
Minal Shah
Otavio Salvador
Rajeshwari Shinde
Dan Murphy
Mateusz Zalega
Troy Kisky
Vivek Gautam
Marek Vasut
Pierre Aubert
Wolfgang Denk
Matt Porter
Enric Balletbo i Serra
Andre Przywara
Eric Nelson