The command "reginfo" got an overhaul for the ppc4xx. It dumps all the
relevant HW configuration registers (address, symbolic name, content).
This allows to easily detect errors in *.h files and changes in the HW
configuration.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Here you find all the changes in the include directory for new register names
and adapting other ones to the names used by AMCC in their manuals, e.g.
For 440EPx/GRPPC440EPx/GRX, Revision 1.15 – September 22, 2008
For PPC405GP Embedded Processor, Revision 1.02 – March 22, 2006
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older
405EX(r) parts. Here a list:
0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec
0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec
Since there are only a few older parts in the field, this patch now
changes the PVR's above to represent the new Rev D versions.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phong Vo" <pvo@amcc.com>
This message is printed upon PCIe bus scan, not only upon error, but also
if no PCIe device is detected at all. Since this is not an error, let's
remove this message in this case. We already have the message
"link is not up." if there is no PCIe device present.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.
Signed-off-by: Mike Nuss <mike@terascala.com>
Signed-off-by: Stefan Roese <sr@denx.de>
As discussed on mailing list, <0 indicates failure, >=0 indicates number
of interfaces found.
Also added blurb about private data
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
if link up detection code is disabled through config option, it gives build warning.
This patch fixes the same
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
All in-tree boards that use this controller have CONFIG_NET_MULTI
added
Also:
- changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111
- cleaned up line lengths
- modified all boards that override weak function in this driver
- modified all eeprom standalone apps to work with new driver
- updated blackfin standalone EEPROM app after testing
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
following build warning was observed
mv88e61xx.c: In function ‘mv88e61xx_busychk’:
mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules
This patch fixes the same
Patch tested for rd6281a board build
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
On 405EZ the RX-/TX-interrupts are coalesced into one IRQ bit in the
UIC. We need to acknowledge the RX-/TX-interrupts in the
SDR0_ICINTSTAT reg as well.
This problem was introduced with commit
d1631fe1 [ppc4xx: Consolidate PPC4xx UIC defines]
Signed-off-by: James Clough <james@rtetc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The random_port() is meant to be used by other net code, but without a
prototype, we get fun warnings like:
dns.c: In function 'DnsSend':
dns.c:89: warning: implicit declaration of function 'random_port'
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch adds support to detect the amount of DDR2 SDRAM
on PMC440 modules. Detection is done by probing through
a list of available and supported hardware configurations
from 1GByte down to 256MB.
The static TLB entry is replaced by dynamically created entries.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.
Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.
Tested on Kilauea (no ECC) and Katmai (with and without ECC).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The Linux kernel has changed the way it numbers serial ports, so update
the default command line to match it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The u-boot image has outgrown the current space and overflowed into the
env sector. So move the env to the next available sector (we've already
allocated the first few sectors anyways for u-boot).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The MPC8536E is capable of booting from the on-chip ROM - boot from
eSDHC and boot from eSPI. When power on, the porcessor excutes the
ROM code to initialize the eSPI/eSDHC controller, and loads the mian
U-Boot image from the memory device that interfaced to the controller,
such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
L2SRAM, then boot from it.
The memory device should contain a specific data structure with control
word and config word at the fixed address. The config word direct the
process how to config the memory device, and the control word direct
the processor where to find the image on the memory device, or where
copy the main image to. The user can use any method to store the data
structure to the memory device, only if store it on the assigned address.
The on-chip ROM code will map the whole 4GB address space by setting
entry0 in the TLB1, so the main image need to switch to Address space 1
to disable this mapping and map the address space again.
This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.
This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
By nature of being based off the MPC8548CDS board, this
board inherited an ENV_SIZE setting of 256k. But since
it has a smaller flash device (8MB soldered on), it has
a native sector size of 128k, and hence the ENV_SIZE was
causing 2 sectors to be used for the environment.
By removing the unused sector, we can push TEXT_BASE up
closer to the end of address space and reclaim that
sector for any other application. This also fixes the
mismatch between TEXT_BASE and MONITOR_LEN reported by
Kumar earlier.
Since this board also supports the ability to boot off
the 64MB SODIMM flash, this change is forward looking
with that in mind; i.e. the settings for MONITOR_LEN
and ENV_SIZE will work when the 512k sectors of the
SODIMM flash are used for alternate boot in the future.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Converted all white space to tabs
* Converted all types to u8/u16/u32
* Reduce lines to fit in 80 columns
* Renamed MPC85xx_{Q,B}MAN -> FSL_CORENET_{Q,B}MAN
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Refactoring the OneNAND IPL code
and some minor fixed:
- Remove unnecessary header file
- Fix wrong access at read interrupt
- The recent OneNAND has 4KiB pagesize
Also Board can override OneNAND IPL image
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
The commit ecad289fc6 (OneNAND: Remove
unused read_spareram and add unlock_all as kernel does) forgot to remove
a local reference to read_spareram in board/micronas/vct/ebi_onenand.c,
which causes the following build failure when configured with OneNAND:
ebi_onenand.c: In function 'onenand_board_init':
ebi_onenand.c:196: error: 'struct onenand_chip' has no member named 'read_spareram'
make[1]: *** [ebi_onenand.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [board/micronas/vct/libvct.a] Error 2
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Files in directories which are symlinked to were not dereferenced
correctly in last commit. E.g., with a symlink
/boot/lnk -> /boot/real_dir
loading
/boot/lnk/uImage
will fail. This patch fixes that by simply seeing to it that the target
base directory has a slash after it.
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Stefan Roese <sr@denx.de>
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).
Signed-off-by: Stefan Roese <sr@denx.de>
The latest PPC4xx register cleanup patch missed the UIC defines.
This patch now changes lower case UIC defines to upper case.
Signed-off-by: Stefan Roese <sr@denx.de>
__i2c_read always ends with a STOP condition thereby releasing
the bus. It is cleaner to do the STOP magic in i2c_read(), like
i2c_write() does. This may also help future multimaster systems which
wants to hold on to the bus until all transactions are finished.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
The latest AN2919 has changed the way FDR/DFSR should be calculated.
Update the driver according to spec. However, Condition 2
is not accounted for as it is not clear how to do so.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Wolfgang Grandegger <wg@grandegger.com>
Some boards need a higher DFSR value than the spec currently
recommends so give these boards the means to define there own.
For completeness, add CONFIG_FSL_I2C_CUSTOM_FDR too.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
After issuing a STOP one must wait until the STOP has completed
on the bus before doing something new to the controller.
Also add an extra read of SR as the manual mentions doing that
is a good idea.
Remove surplus write of CR just before a write, isn't required and
could potentially disturb the I2C bus.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.
Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS_<registername>_<bitfield> assignments in the board
config file.
also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.
also start to use i/o accessors.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Commit 804d83a5 allows us to move all the configuration
variation tweaks out of the top level Makefile and down
into the board config header. This takes advantage of
that for the sbc8349 board.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
With this patch we can change QE USB mode without need to hand-edit
the device tree.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch fixes various ethernet issues with gigabit links handling
in U-Boot. The workarounds originally implemented by Kim Phillips for
Linux kernel.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Since commit 5c2ff323a9 ("mpc8360emds:
rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux.
Though, it appears that QE Ethernet in Gigabit mode can't transmit
large packets when it tries to work with a data in LBC SDRAM (memtest
didn't discover any issues, is LBC SDRAM just too slow?).
With this patch we can still use the board without DDR memory, but
if DDR is available, we don't use LBC SDRAM.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Niklaus Giger
Stefan Roese
Mike Nuss
Ben Warren
Mike Frysinger
Prafulla Wadaskar
James Clough
Wolfgang Denk
Matthias Fuchs
Felix Radensky
Kumar Gala
Mingkai Hu
Paul Gortmaker
Scott Wood
Kyungmin Park
Shinya Kuribayashi
Simon Kagstrom
Joakim Tjernlund
Kim Phillips
Anton Vorontsov