A delay of approximately 250 ms after PCI bus reset in
pci_mpc5xxx_init() is needed to recognize the Coral-PA
controller on the graphic extention board.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Add axi_ethernet driver for little-endian Microblaze.
RX/TX BDs and rxframe buffer are shared among all axi_ethernet MACs.
Only one MAC can work in one time.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Mike Frysinger <vapier@gentoo.org>
fdt_create_phandle() was ignoring errors from fdt_set_phandle(). If an
error occurs, print an error message and return 0, which is an invalid
phandle. We also need to change the return type for fdt_create_phandle()
to indicate that it cannot return an error code.
Signed-off-by: Timur Tabi <timur@freescale.com>
The do_fixup_by_path_string() will set the specified node's property to the
value contained in "status". It would just be an inline wrapper for
do_fixup_by_path() that calls strlen on the argument.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
With older compilers (gcc-4.2.x) we run into issues that resulting image
is too large. We can save a bunch of space by removing the video support.
In general video support on these boards is a nice to have since it
requires a PCIe add-on card.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- Rework tlb and law tables.
- PCI2 is not available on MPC8548CDS, so remove it.
- Move the memory map to the board config file.
- Rewrite the board info according to the manual.
- Remove unnecessary macros and redefine some macros to align with other boards.
- Fix some typos.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device
from Qi hardware:
http://en.qi-hardware.com/wiki/Ben_NanoNotehttp://en.qi-hardware.com/wiki/Main_Pagehttp://en.wikipedia.org/wiki/Qi_hardware
This Jz4740-based clamshell device does not use NOR flash to boot.
The initial bring-up assumes that U-Boot is directly loaded into SDRAM
using USB boot tool, and starts from 0x80100000.
About USB boot tool
-------------------
Jz4740 is one of the XBurst processors with USB boot functionality
supported. The CPU can boot from a small ROM in the LSI, initialize
CPU and USB module, then wait for USB commands from the USB host.
We can send 8 KB binary data to the CPU cache using USB boot tool.
USB boot tool is available to the public at Ingenic website. Also
there is an alternative Debian package named xburst-tools.
Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Daniel <zpxu@ingenic.cn>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Some intip boards don't seem to run stable with CL4, datasheets suggest that
CL5 is the safe value.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Fan PWM lookuptable was modified to start at 46 degrees
celsius instead of 40 degrees celsius.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Use CONFIG_AUTOBOOT_KEYED on intip so that booting can only be
stopped with well defined keypresses.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
MPC8536DS offer booting from SDcard or SPI flash. This patch defined that
u-boot can save the environment variables on SDcard or SPI flash when
booting from the related device. The Env parameter region and linux
kernel region have overlap in SPI-Flash, So change the Env param saving
address.
Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS,
so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width
to 4-bit and enable SPI signals.
2. Add eSPI controller and SPI-FLASH definition.
Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- Increase the size of malloc space.
- Enable e1000 network card.
- Show pci devices on startup.
- Change the location of env address.
- Use hwconfig to turn off ECC by default.
[Kumar Gala] Fixed white space formating for CONFIG_EXTRA_ENV_SETTINGS
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We really shouldn't be overwriting bat registers with translation enabled,
especially when we're executing code using one of them for translating
the current instruction stream. Instead, disable address translation
while doing the final BAT setup.
In order to do this, setup_bats has to move back to asm code, because we
require translation to be enabled to have a stack for C code. The yucky
thing about that is that the assembler doesn't like ULL so we have to
switch to using HIGH/LOW pairs for physical addresses that are > 32 bits
in length.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There were duplicate (and conflicting) defines for the BATs used
to cover SRIO. Drop the bogus set.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The macro CONFIG_ENABLE_36BIT_PHYS is used to indicate that the given SOC is
capable of 36-bit physical addresses, even if such large addresses are not
used. On two boards, this macro was enabled only when building a 36-bit
image.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Interactive DDR debugging provides a user interface to view and modify SPD,
DIMM parameters, board options and DDR controller registers before DDR is
initialized. With this feature, developers can fine-tune DDR for board
bringup and other debugging without frequently having to reprogram the flash.
To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
file and set an environment variable to activate it. Syntax:
setenv ddr_interactive on
After reset, U-boot prompts before initializing DDR controllers
FSL DDR>
The available commands are
print print SPD and intermediate computed data
reset reboot machine
recompute reload SPD and options to default and recompute regs
edit modify spd, parameter, or option
compute recompute registers from current next_step to end
next_step shows current next_step
help this message
go program the memory controller and continue with u-boot
The first command should be "compute", which reads data from DIMM SPDs and
board options, performs the calculation then stops before setting DDR
controller. A user can use "print" and "edit" commands to view and modify
anything. "Go" picks up from current step with any modification and
compltes the calculation then enables the DDR controller to continue u-boot.
"Recompute" does it over from fresh reading.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
While adding asm/cache.h to common.h for PPC targets, I got an
error about multiple definitions of some DBSR_ macros. While
scanning these defines, I noticed that some where defined not
correctly for all PPC variants. So I removed all unused defines,
and corrected the ones really used by bedbug (book-e vs. ppc40x).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
This is needed for the patch "cache: add default setting for
CONFIG_SYS_CACHELINE_SIZE" from Anton Staaf. As cache.h defines
CONFIG_SYS_CACHELINE_SIZE for PPC targets.
This will remove the following warnings/errors:
include/common.h:819:2: warning: #warning CONFIG_SYS_CACHELINE_SIZE not defined, using __BIGGEST_ALIGNMENT__
cache.c:33: error: '__BIGGEST_ALIGNMENT__' undeclared (first use in this function)
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Staaf <robotboy@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Now that none of the core checks CONFIG_NET_MULTI, there's not much point
in boards defining it. So scrub all references to it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This is long over due. All but two net drivers have been converted, but
those have now been dropped.
The only thing left to do is actually delete all references to NET_MULTI
and code that is compiled when that is not defined. So here we scrub the
core code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
These drivers have never been converted to NET_MULTI, and they are only
used by one board (BMW). So drop the drivers until someone feels like
rewriting them for NET_MULTI support.
Rather than punting the BMW board completely, just disable net support
in its board config. Seems to build fine without it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This pushes the ugly duplicated arch ifdef lists we maintain in various
image related files out to the arch headers themselves.
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current km_arm boards have a Power-On test jumper. When this
jumper is set, this triggers some Power-On tests on the board.
This patch enables the support of this jumper for starting the
memory_regions test when the jumper is set.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
This allows to test a larger part of the RAM in the memory tests.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
This test is similar to the actual POST memory test but quicker and
far less complete. It checks the address and data lines and then only
tests some regularly placed sub regions of the RAM.
This can be useful when we want to test the RAM but we do not have enough
time to run the full memory test.
The POST memory test code was rearranged in order to avoid code duplication
between the two tests but the memory test functionnality remains the same.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Ackey-by: Mike Frysinger <vapier@gentoo.org>
The predefinde post_word_load/store functions do not fit all boards,
so we introduce a way to define post_word_load/store as externs in
post.h that then can be defined in board specific files. This is done
with the CONFIG_POST_EXTERNAL_WORD_FUNCS #define
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
This reverts commit 60ce53cf9f.
The commit causes build breakage for a number of boards. This results
from the fact that now the arguments of debug() actually get
referenced (even if there is hope that the compiler will optimize
away the debug() call). The obvious fix to that probem (change the
code to always declare the referenced variables and data structures)
increases the code size, and was this rejected. So it was decided to
revert this commit until a better solution is found.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
[scottwood@freescale.com: use chip instead of redundant priv_nand]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each
Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2
Rings per JQ). This just handles RAID Engine in non-DPAA mode.
Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move some SoC/board specific defines out of corenet_ds.h and into the
corresponding P3041DS/P4080DS/P5020.h.
We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060
SoC/reference board does not have these devices and it will share the same
board code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The SoC configuration may have more ports enabled than a given board
actually can utilize. Add a routinue that allows the board code to
disable a port that it knows isn't being used.
fm_disable_port() needs to be called before cpu_eth_init().
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Pre u-boot Flow:
1. User loads the u-boot image in flash
2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000
(Please note that ISBC expects all these addresses, images to be
validated, entry point etc within 0 - 3.5G range)
3. ISBC validates the u-boot image, and passes control to u-boot
at 0xcffffffc.
Changes in u-boot:
1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M
CONFIG_SYS_PBI_FLASH_WINDOW in AS=1.
(The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash
created by PBL/configuration word within 0 - 3.5G memory range. The
u-boot image at this address has been validated by ISBC code)
2. Remove TLB entries for 0 - 3.5G created by ISBC code
3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by
PBL/configuration word after switch to AS = 1
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
Acked-by: Wood Scott-B07421 <B07421@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.
SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
U-Boot BSP handle 0x3 offset for big endian systems.
Little endian Microblaze systems don't use any offset.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Fix the following gcc4.6 problems:
cmd_date.c: In function ‘do_date’:
cmd_date.c:50:6: warning: variable ‘old_bus’ set but not used
[-Wunused-but-set-variable]
asix.c: In function ‘asix_init’:
asix.c:317:6: warning: variable ‘rx_ctl’ set but not used
[-Wunused-but-set-variable]
usb.c: In function ‘usb_parse_config’:
usb.c:331:17: warning: variable ‘ch’ set but not used
[-Wunused-but-set-variable]
usb.c: In function ‘usb_hub_port_connect_change’:
usb.c:1123:29: warning: variable ‘portchange’ set but not used
[-Wunused-but-set-variable]
usb.c: In function ‘usb_hub_configure’:
usb.c:1183:25: warning: variable ‘hubsts’ set but not used
[-Wunused-but-set-variable]
usb_storage.c: In function ‘usb_stor_CB_reset’:
usb_storage.c:466:6: warning: variable ‘result’ set but not used
[-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
The EST SBC8260 is over 10 years old, and the SBC8240 older than
that. With the tiny amount of RAM (by today's standards), there
really isn't anyone interested in running the latest U-boot on
these EOL products anymore.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: jon.diekema@smiths-aerospace.com
When include/linux/compiler.h is included, the associated gcc3
header is required for older build environments.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory
mapped access will be used to read/write the uart registers.
This is especially useful for SoC devices that implement 16550
compatible uarts but that have peripheral access width constraints.
Signed-off-by: Dave Aldridge <fovsoft@gmail.com>
Currently in do_fat_read() when reading FAT sectors, we have to divide down
LINEAR_PREFETCH_SIZE by the sector size, whereas it's defined as 2 sectors
worth of bytes. In order to avoid redundant multiplication/division, introduce
#define PREFETCH_BLOCKS instead of #define LINEAR_PREFETCH_SIZE.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
Apple iPod nanos have sector sizes of 2 or 4 KiB, which crashes U-Boot when it
tries to read the boot sector into 512-byte buffer situated on stack. Make the
FAT code indifferent to the sector size.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
Mike Frysinger
Anatolij Gustschin
Michal Simek
Timur Tabi
Chunhe Lan
Kumar Gala
chenhui zhao
Xiangfu Liu
Dirk Eibach
Xie Xiaobo
Fanzc
Becky Bruce
York Sun
Stefan Roese
Valentin Longchamp
Wolfgang Denk
Marek Vasut
Ruchika Gupta
Shaohui Xie
Paul Gortmaker
Scott McNutt
Dave Aldridge
Sergei Shtylyov