The wake up ARP feature need use the memory to process
wake up packet, we enable auto self refresh to support it.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.
If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields
of TLBs. This is what we should have always been using from the start.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and
maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash.
This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Added a PIXIS_BASE_PHYS for use as the physical address and maintain
PIXIS_BASE as the virtual address of the PIXIS fpga registers.
This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Error with CONFIG_NAND_LEGACY in common/cmd_nand.c:
With current code "nand read.jffs2s" (read and skip bad blocks) is always interpreted as
"nand read.jffs2" (read and fill bad blocks with 0xff). This is because ".jffs2" is
tested before ".jffs2s" and only the first two characters are compared.
Correction:
Test for ".jffs2s" first and compare the first 7 characters.
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
but that's bogus and did not work anyhow.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
We load the secondary stage u-boot image from NAND to
system memory by nand_load, but we did not flush d-cache
to memory, nor invalidate i-cache before we jump to RAM.
When the system has cache enabled and the TLB/page attribute
of system memory is cacheable, it will cause issues.
- 83xx family is using the d-cache lock, so all of d-cache
access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
cache lock. you will see the issue.
This patch fixes the cache issue.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Enable nand lock, unlock and status of lock feature.
Not every device and platform requires this, hence,
it is under define for CONFIG_CMD_NAND_LOCK_UNLOCK
Nand unlock and status operate on block boundary instead
of page boundary. Details in:
http://www.micron.com/products/partdetail?part=MT29C2G24MAKLAJG-6%20IT
Intial solution provided by Vikram Pandita <vikram.pandita@ti.com>
Includes preliminary suggestions from Scott Wood
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Rather than putting the function prototype for board_nand_init() in the one
place where it gets called, put it into nand.h so that every place that also
defines it gets the prototype. Otherwise, errors can go silently unnoticed
such as using the wrong return value (void rather than int) when defining
the function.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
- Add subpage write support
- Add onenand_oob_64/32 ecclayout
This has been missing and without it UBI has some incompatibilies issues
with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is
placed differently (2048 instead of 512) without this fix.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Update OneNAND command to support bad block awareness.
Also change the OneNAND command style to better match the
NAND version.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
The version (ver_id) was not stored in the onenand_chip structure and
because of this the continuous locking scheme could be enabled on some
chips.
Signed-off-by: Stefan Roese <sr@denx.de>
The x86 based version of Darwin behaves the same quirky way as the powerpc
Darwin, so only check HOSTOS when setting up Darwin workarounds.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The code in fdt_resize() to extend the fdt size to end on a page boundary
is wrong for fdt's not located at an address aligned on a page boundary.
What's even worse, the code would make actualsize shrink rather than grow
if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(),
causing fdt_add_mem_rsv to fail.
Fix it by aligning end address (blob + size) to a page boundary instead.
For aligned fdt's this is equivalent to what we had before.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
lowlevel_init of SH was corrected to use the write/readXX macro.
However, there was a problem that was not able to be compiled partially.
This patch corrected this.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Dave Liu
Kumar Gala
Haiying Wang
Mike Frysinger
Wolfgang Denk
Schlaegl Manfred jun
Wolfgang Grandegger
Nishanth Menon
Stefan Roese
Kyungmin Park
Michal Simek
Haavard Skinnemoen
Peter Korsgaard
Jean-Christophe PLAGNIOL-VILLARD
Nobuhiro Iwamatsu
Kieran Bingham